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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci.c
bloba49f41b50b167142e6a6e74ef76fee20f97dd326
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/sdhci-pci-data.h>
28
29 #include "sdhci.h"
30 #include "sdhci-pci.h"
31
32 /*****************************************************************************\
33 * *
34 * Hardware specific quirk handling *
35 * *
36 \*****************************************************************************/
37
38 static int ricoh_probe(struct sdhci_pci_chip *chip)
39 {
40 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
41 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
42 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
43 return 0;
44 }
45
46 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
47 {
48 slot->host->caps =
49 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
50 & SDHCI_TIMEOUT_CLK_MASK) |
51
52 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
53 & SDHCI_CLOCK_BASE_MASK) |
54
55 SDHCI_TIMEOUT_CLK_UNIT |
56 SDHCI_CAN_VDD_330 |
57 SDHCI_CAN_DO_HISPD |
58 SDHCI_CAN_DO_SDMA;
59 return 0;
60 }
61
62 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
63 {
64 /* Apply a delay to allow controller to settle */
65 /* Otherwise it becomes confused if card state changed
66 during suspend */
67 msleep(500);
68 return 0;
69 }
70
71 static const struct sdhci_pci_fixes sdhci_ricoh = {
72 .probe = ricoh_probe,
73 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
74 SDHCI_QUIRK_FORCE_DMA |
75 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
76 };
77
78 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
79 .probe_slot = ricoh_mmc_probe_slot,
80 .resume = ricoh_mmc_resume,
81 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
82 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
83 SDHCI_QUIRK_NO_CARD_NO_RESET |
84 SDHCI_QUIRK_MISSING_CAPS
85 };
86
87 static const struct sdhci_pci_fixes sdhci_ene_712 = {
88 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
89 SDHCI_QUIRK_BROKEN_DMA,
90 };
91
92 static const struct sdhci_pci_fixes sdhci_ene_714 = {
93 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
94 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
95 SDHCI_QUIRK_BROKEN_DMA,
96 };
97
98 static const struct sdhci_pci_fixes sdhci_cafe = {
99 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
100 SDHCI_QUIRK_NO_BUSY_IRQ |
101 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
102 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
103 };
104
105 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
106 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
107 };
108
109 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
110 {
111 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
112 return 0;
113 }
114
115 /*
116 * ADMA operation is disabled for Moorestown platform due to
117 * hardware bugs.
118 */
119 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
120 {
121 /*
122 * slots number is fixed here for MRST as SDIO3/5 are never used and
123 * have hardware bugs.
124 */
125 chip->num_slots = 1;
126 return 0;
127 }
128
129 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
130 {
131 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
132 return 0;
133 }
134
135 #ifdef CONFIG_PM_RUNTIME
136
137 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
138 {
139 struct sdhci_pci_slot *slot = dev_id;
140 struct sdhci_host *host = slot->host;
141
142 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
143 return IRQ_HANDLED;
144 }
145
146 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
147 {
148 int err, irq, gpio = slot->cd_gpio;
149
150 slot->cd_gpio = -EINVAL;
151 slot->cd_irq = -EINVAL;
152
153 if (!gpio_is_valid(gpio))
154 return;
155
156 err = gpio_request(gpio, "sd_cd");
157 if (err < 0)
158 goto out;
159
160 err = gpio_direction_input(gpio);
161 if (err < 0)
162 goto out_free;
163
164 irq = gpio_to_irq(gpio);
165 if (irq < 0)
166 goto out_free;
167
168 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
169 IRQF_TRIGGER_FALLING, "sd_cd", slot);
170 if (err)
171 goto out_free;
172
173 slot->cd_gpio = gpio;
174 slot->cd_irq = irq;
175
176 return;
177
178 out_free:
179 gpio_free(gpio);
180 out:
181 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
182 }
183
184 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
185 {
186 if (slot->cd_irq >= 0)
187 free_irq(slot->cd_irq, slot);
188 if (gpio_is_valid(slot->cd_gpio))
189 gpio_free(slot->cd_gpio);
190 }
191
192 #else
193
194 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
195 {
196 }
197
198 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
199 {
200 }
201
202 #endif
203
204 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
205 {
206 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
207 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
208 MMC_CAP2_HC_ERASE_SZ;
209 return 0;
210 }
211
212 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
213 {
214 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
215 return 0;
216 }
217
218 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
219 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
220 .probe_slot = mrst_hc_probe_slot,
221 };
222
223 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
224 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
225 .probe = mrst_hc_probe,
226 };
227
228 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
229 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
230 .allow_runtime_pm = true,
231 .own_cd_for_runtime_pm = true,
232 };
233
234 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
235 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
236 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
237 .allow_runtime_pm = true,
238 .probe_slot = mfd_sdio_probe_slot,
239 };
240
241 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
242 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
243 .allow_runtime_pm = true,
244 .probe_slot = mfd_emmc_probe_slot,
245 };
246
247 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
248 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
249 .probe_slot = pch_hc_probe_slot,
250 };
251
252 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
253 {
254 u8 reg;
255
256 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
257 reg |= 0x10;
258 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
259 /* For eMMC, minimum is 1us but give it 9us for good measure */
260 udelay(9);
261 reg &= ~0x10;
262 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
263 /* For eMMC, minimum is 200us but give it 300us for good measure */
264 usleep_range(300, 1000);
265 }
266
267 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
268 {
269 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
270 MMC_CAP_HW_RESET;
271 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
272 slot->hw_reset = sdhci_pci_int_hw_reset;
273 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
274 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
275 return 0;
276 }
277
278 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
279 {
280 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
281 return 0;
282 }
283
284 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
285 .allow_runtime_pm = true,
286 .probe_slot = byt_emmc_probe_slot,
287 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
288 };
289
290 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
291 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
292 .allow_runtime_pm = true,
293 .probe_slot = byt_sdio_probe_slot,
294 };
295
296 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
297 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON,
298 .allow_runtime_pm = true,
299 .own_cd_for_runtime_pm = true,
300 };
301
302 /* Define Host controllers for Intel Merrifield platform */
303 #define INTEL_MRFL_EMMC_0 0
304 #define INTEL_MRFL_EMMC_1 1
305
306 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
307 {
308 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
309 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
310 /* SD support is not ready yet */
311 return -ENODEV;
312
313 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
314 MMC_CAP_1_8V_DDR;
315
316 return 0;
317 }
318
319 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
320 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
321 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200,
322 .probe_slot = intel_mrfl_mmc_probe_slot,
323 };
324
325 /* O2Micro extra registers */
326 #define O2_SD_LOCK_WP 0xD3
327 #define O2_SD_MULTI_VCC3V 0xEE
328 #define O2_SD_CLKREQ 0xEC
329 #define O2_SD_CAPS 0xE0
330 #define O2_SD_ADMA1 0xE2
331 #define O2_SD_ADMA2 0xE7
332 #define O2_SD_INF_MOD 0xF1
333
334 static int o2_probe(struct sdhci_pci_chip *chip)
335 {
336 int ret;
337 u8 scratch;
338
339 switch (chip->pdev->device) {
340 case PCI_DEVICE_ID_O2_8220:
341 case PCI_DEVICE_ID_O2_8221:
342 case PCI_DEVICE_ID_O2_8320:
343 case PCI_DEVICE_ID_O2_8321:
344 /* This extra setup is required due to broken ADMA. */
345 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
346 if (ret)
347 return ret;
348 scratch &= 0x7f;
349 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
350
351 /* Set Multi 3 to VCC3V# */
352 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
353
354 /* Disable CLK_REQ# support after media DET */
355 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
356 if (ret)
357 return ret;
358 scratch |= 0x20;
359 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
360
361 /* Choose capabilities, enable SDMA. We have to write 0x01
362 * to the capabilities register first to unlock it.
363 */
364 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
365 if (ret)
366 return ret;
367 scratch |= 0x01;
368 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
369 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
370
371 /* Disable ADMA1/2 */
372 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
373 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
374
375 /* Disable the infinite transfer mode */
376 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
377 if (ret)
378 return ret;
379 scratch |= 0x08;
380 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
381
382 /* Lock WP */
383 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
384 if (ret)
385 return ret;
386 scratch |= 0x80;
387 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
388 }
389
390 return 0;
391 }
392
393 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
394 {
395 u8 scratch;
396 int ret;
397
398 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
399 if (ret)
400 return ret;
401
402 /*
403 * Turn PMOS on [bit 0], set over current detection to 2.4 V
404 * [bit 1:2] and enable over current debouncing [bit 6].
405 */
406 if (on)
407 scratch |= 0x47;
408 else
409 scratch &= ~0x47;
410
411 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
412 if (ret)
413 return ret;
414
415 return 0;
416 }
417
418 static int jmicron_probe(struct sdhci_pci_chip *chip)
419 {
420 int ret;
421 u16 mmcdev = 0;
422
423 if (chip->pdev->revision == 0) {
424 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
425 SDHCI_QUIRK_32BIT_DMA_SIZE |
426 SDHCI_QUIRK_32BIT_ADMA_SIZE |
427 SDHCI_QUIRK_RESET_AFTER_REQUEST |
428 SDHCI_QUIRK_BROKEN_SMALL_PIO;
429 }
430
431 /*
432 * JMicron chips can have two interfaces to the same hardware
433 * in order to work around limitations in Microsoft's driver.
434 * We need to make sure we only bind to one of them.
435 *
436 * This code assumes two things:
437 *
438 * 1. The PCI code adds subfunctions in order.
439 *
440 * 2. The MMC interface has a lower subfunction number
441 * than the SD interface.
442 */
443 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
444 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
445 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
446 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
447
448 if (mmcdev) {
449 struct pci_dev *sd_dev;
450
451 sd_dev = NULL;
452 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
453 mmcdev, sd_dev)) != NULL) {
454 if ((PCI_SLOT(chip->pdev->devfn) ==
455 PCI_SLOT(sd_dev->devfn)) &&
456 (chip->pdev->bus == sd_dev->bus))
457 break;
458 }
459
460 if (sd_dev) {
461 pci_dev_put(sd_dev);
462 dev_info(&chip->pdev->dev, "Refusing to bind to "
463 "secondary interface.\n");
464 return -ENODEV;
465 }
466 }
467
468 /*
469 * JMicron chips need a bit of a nudge to enable the power
470 * output pins.
471 */
472 ret = jmicron_pmos(chip, 1);
473 if (ret) {
474 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
475 return ret;
476 }
477
478 /* quirk for unsable RO-detection on JM388 chips */
479 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
480 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
481 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
482
483 return 0;
484 }
485
486 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
487 {
488 u8 scratch;
489
490 scratch = readb(host->ioaddr + 0xC0);
491
492 if (on)
493 scratch |= 0x01;
494 else
495 scratch &= ~0x01;
496
497 writeb(scratch, host->ioaddr + 0xC0);
498 }
499
500 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
501 {
502 if (slot->chip->pdev->revision == 0) {
503 u16 version;
504
505 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
506 version = (version & SDHCI_VENDOR_VER_MASK) >>
507 SDHCI_VENDOR_VER_SHIFT;
508
509 /*
510 * Older versions of the chip have lots of nasty glitches
511 * in the ADMA engine. It's best just to avoid it
512 * completely.
513 */
514 if (version < 0xAC)
515 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
516 }
517
518 /* JM388 MMC doesn't support 1.8V while SD supports it */
519 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
520 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
521 MMC_VDD_29_30 | MMC_VDD_30_31 |
522 MMC_VDD_165_195; /* allow 1.8V */
523 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
524 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
525 }
526
527 /*
528 * The secondary interface requires a bit set to get the
529 * interrupts.
530 */
531 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
532 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
533 jmicron_enable_mmc(slot->host, 1);
534
535 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
536
537 return 0;
538 }
539
540 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
541 {
542 if (dead)
543 return;
544
545 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
546 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
547 jmicron_enable_mmc(slot->host, 0);
548 }
549
550 static int jmicron_suspend(struct sdhci_pci_chip *chip)
551 {
552 int i;
553
554 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
555 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
556 for (i = 0; i < chip->num_slots; i++)
557 jmicron_enable_mmc(chip->slots[i]->host, 0);
558 }
559
560 return 0;
561 }
562
563 static int jmicron_resume(struct sdhci_pci_chip *chip)
564 {
565 int ret, i;
566
567 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
568 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
569 for (i = 0; i < chip->num_slots; i++)
570 jmicron_enable_mmc(chip->slots[i]->host, 1);
571 }
572
573 ret = jmicron_pmos(chip, 1);
574 if (ret) {
575 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
576 return ret;
577 }
578
579 return 0;
580 }
581
582 static const struct sdhci_pci_fixes sdhci_o2 = {
583 .probe = o2_probe,
584 };
585
586 static const struct sdhci_pci_fixes sdhci_jmicron = {
587 .probe = jmicron_probe,
588
589 .probe_slot = jmicron_probe_slot,
590 .remove_slot = jmicron_remove_slot,
591
592 .suspend = jmicron_suspend,
593 .resume = jmicron_resume,
594 };
595
596 /* SysKonnect CardBus2SDIO extra registers */
597 #define SYSKT_CTRL 0x200
598 #define SYSKT_RDFIFO_STAT 0x204
599 #define SYSKT_WRFIFO_STAT 0x208
600 #define SYSKT_POWER_DATA 0x20c
601 #define SYSKT_POWER_330 0xef
602 #define SYSKT_POWER_300 0xf8
603 #define SYSKT_POWER_184 0xcc
604 #define SYSKT_POWER_CMD 0x20d
605 #define SYSKT_POWER_START (1 << 7)
606 #define SYSKT_POWER_STATUS 0x20e
607 #define SYSKT_POWER_STATUS_OK (1 << 0)
608 #define SYSKT_BOARD_REV 0x210
609 #define SYSKT_CHIP_REV 0x211
610 #define SYSKT_CONF_DATA 0x212
611 #define SYSKT_CONF_DATA_1V8 (1 << 2)
612 #define SYSKT_CONF_DATA_2V5 (1 << 1)
613 #define SYSKT_CONF_DATA_3V3 (1 << 0)
614
615 static int syskt_probe(struct sdhci_pci_chip *chip)
616 {
617 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
618 chip->pdev->class &= ~0x0000FF;
619 chip->pdev->class |= PCI_SDHCI_IFDMA;
620 }
621 return 0;
622 }
623
624 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
625 {
626 int tm, ps;
627
628 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
629 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
630 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
631 "board rev %d.%d, chip rev %d.%d\n",
632 board_rev >> 4, board_rev & 0xf,
633 chip_rev >> 4, chip_rev & 0xf);
634 if (chip_rev >= 0x20)
635 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
636
637 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
638 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
639 udelay(50);
640 tm = 10; /* Wait max 1 ms */
641 do {
642 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
643 if (ps & SYSKT_POWER_STATUS_OK)
644 break;
645 udelay(100);
646 } while (--tm);
647 if (!tm) {
648 dev_err(&slot->chip->pdev->dev,
649 "power regulator never stabilized");
650 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
651 return -ENODEV;
652 }
653
654 return 0;
655 }
656
657 static const struct sdhci_pci_fixes sdhci_syskt = {
658 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
659 .probe = syskt_probe,
660 .probe_slot = syskt_probe_slot,
661 };
662
663 static int via_probe(struct sdhci_pci_chip *chip)
664 {
665 if (chip->pdev->revision == 0x10)
666 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
667
668 return 0;
669 }
670
671 static const struct sdhci_pci_fixes sdhci_via = {
672 .probe = via_probe,
673 };
674
675 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
676 {
677 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
678 return 0;
679 }
680
681 static const struct sdhci_pci_fixes sdhci_rtsx = {
682 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
683 SDHCI_QUIRK2_BROKEN_DDR50,
684 .probe_slot = rtsx_probe_slot,
685 };
686
687 static const struct pci_device_id pci_ids[] = {
688 {
689 .vendor = PCI_VENDOR_ID_RICOH,
690 .device = PCI_DEVICE_ID_RICOH_R5C822,
691 .subvendor = PCI_ANY_ID,
692 .subdevice = PCI_ANY_ID,
693 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
694 },
695
696 {
697 .vendor = PCI_VENDOR_ID_RICOH,
698 .device = 0x843,
699 .subvendor = PCI_ANY_ID,
700 .subdevice = PCI_ANY_ID,
701 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
702 },
703
704 {
705 .vendor = PCI_VENDOR_ID_RICOH,
706 .device = 0xe822,
707 .subvendor = PCI_ANY_ID,
708 .subdevice = PCI_ANY_ID,
709 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
710 },
711
712 {
713 .vendor = PCI_VENDOR_ID_RICOH,
714 .device = 0xe823,
715 .subvendor = PCI_ANY_ID,
716 .subdevice = PCI_ANY_ID,
717 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
718 },
719
720 {
721 .vendor = PCI_VENDOR_ID_ENE,
722 .device = PCI_DEVICE_ID_ENE_CB712_SD,
723 .subvendor = PCI_ANY_ID,
724 .subdevice = PCI_ANY_ID,
725 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
726 },
727
728 {
729 .vendor = PCI_VENDOR_ID_ENE,
730 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
731 .subvendor = PCI_ANY_ID,
732 .subdevice = PCI_ANY_ID,
733 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
734 },
735
736 {
737 .vendor = PCI_VENDOR_ID_ENE,
738 .device = PCI_DEVICE_ID_ENE_CB714_SD,
739 .subvendor = PCI_ANY_ID,
740 .subdevice = PCI_ANY_ID,
741 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
742 },
743
744 {
745 .vendor = PCI_VENDOR_ID_ENE,
746 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
747 .subvendor = PCI_ANY_ID,
748 .subdevice = PCI_ANY_ID,
749 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
750 },
751
752 {
753 .vendor = PCI_VENDOR_ID_MARVELL,
754 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
755 .subvendor = PCI_ANY_ID,
756 .subdevice = PCI_ANY_ID,
757 .driver_data = (kernel_ulong_t)&sdhci_cafe,
758 },
759
760 {
761 .vendor = PCI_VENDOR_ID_JMICRON,
762 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
763 .subvendor = PCI_ANY_ID,
764 .subdevice = PCI_ANY_ID,
765 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
766 },
767
768 {
769 .vendor = PCI_VENDOR_ID_JMICRON,
770 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
771 .subvendor = PCI_ANY_ID,
772 .subdevice = PCI_ANY_ID,
773 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
774 },
775
776 {
777 .vendor = PCI_VENDOR_ID_JMICRON,
778 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
779 .subvendor = PCI_ANY_ID,
780 .subdevice = PCI_ANY_ID,
781 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
782 },
783
784 {
785 .vendor = PCI_VENDOR_ID_JMICRON,
786 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
787 .subvendor = PCI_ANY_ID,
788 .subdevice = PCI_ANY_ID,
789 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
790 },
791
792 {
793 .vendor = PCI_VENDOR_ID_SYSKONNECT,
794 .device = 0x8000,
795 .subvendor = PCI_ANY_ID,
796 .subdevice = PCI_ANY_ID,
797 .driver_data = (kernel_ulong_t)&sdhci_syskt,
798 },
799
800 {
801 .vendor = PCI_VENDOR_ID_VIA,
802 .device = 0x95d0,
803 .subvendor = PCI_ANY_ID,
804 .subdevice = PCI_ANY_ID,
805 .driver_data = (kernel_ulong_t)&sdhci_via,
806 },
807
808 {
809 .vendor = PCI_VENDOR_ID_REALTEK,
810 .device = 0x5250,
811 .subvendor = PCI_ANY_ID,
812 .subdevice = PCI_ANY_ID,
813 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
814 },
815
816 {
817 .vendor = PCI_VENDOR_ID_INTEL,
818 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
819 .subvendor = PCI_ANY_ID,
820 .subdevice = PCI_ANY_ID,
821 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
822 },
823
824 {
825 .vendor = PCI_VENDOR_ID_INTEL,
826 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
827 .subvendor = PCI_ANY_ID,
828 .subdevice = PCI_ANY_ID,
829 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
830 },
831
832 {
833 .vendor = PCI_VENDOR_ID_INTEL,
834 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
835 .subvendor = PCI_ANY_ID,
836 .subdevice = PCI_ANY_ID,
837 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
838 },
839
840 {
841 .vendor = PCI_VENDOR_ID_INTEL,
842 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
843 .subvendor = PCI_ANY_ID,
844 .subdevice = PCI_ANY_ID,
845 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
846 },
847
848 {
849 .vendor = PCI_VENDOR_ID_INTEL,
850 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
851 .subvendor = PCI_ANY_ID,
852 .subdevice = PCI_ANY_ID,
853 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
854 },
855
856 {
857 .vendor = PCI_VENDOR_ID_INTEL,
858 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
859 .subvendor = PCI_ANY_ID,
860 .subdevice = PCI_ANY_ID,
861 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
862 },
863
864 {
865 .vendor = PCI_VENDOR_ID_INTEL,
866 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
867 .subvendor = PCI_ANY_ID,
868 .subdevice = PCI_ANY_ID,
869 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
870 },
871
872 {
873 .vendor = PCI_VENDOR_ID_INTEL,
874 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
875 .subvendor = PCI_ANY_ID,
876 .subdevice = PCI_ANY_ID,
877 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
878 },
879
880 {
881 .vendor = PCI_VENDOR_ID_INTEL,
882 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
883 .subvendor = PCI_ANY_ID,
884 .subdevice = PCI_ANY_ID,
885 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
886 },
887
888 {
889 .vendor = PCI_VENDOR_ID_INTEL,
890 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
891 .subvendor = PCI_ANY_ID,
892 .subdevice = PCI_ANY_ID,
893 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
894 },
895
896 {
897 .vendor = PCI_VENDOR_ID_INTEL,
898 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
899 .subvendor = PCI_ANY_ID,
900 .subdevice = PCI_ANY_ID,
901 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
902 },
903
904 {
905 .vendor = PCI_VENDOR_ID_INTEL,
906 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
907 .subvendor = PCI_ANY_ID,
908 .subdevice = PCI_ANY_ID,
909 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
910 },
911
912 {
913 .vendor = PCI_VENDOR_ID_INTEL,
914 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
915 .subvendor = PCI_ANY_ID,
916 .subdevice = PCI_ANY_ID,
917 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
918 },
919
920 {
921 .vendor = PCI_VENDOR_ID_INTEL,
922 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
923 .subvendor = PCI_ANY_ID,
924 .subdevice = PCI_ANY_ID,
925 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
926 },
927
928 {
929 .vendor = PCI_VENDOR_ID_INTEL,
930 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
931 .subvendor = PCI_ANY_ID,
932 .subdevice = PCI_ANY_ID,
933 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
934 },
935
936 {
937 .vendor = PCI_VENDOR_ID_INTEL,
938 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
939 .subvendor = PCI_ANY_ID,
940 .subdevice = PCI_ANY_ID,
941 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
942 },
943
944 {
945 .vendor = PCI_VENDOR_ID_INTEL,
946 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
947 .subvendor = PCI_ANY_ID,
948 .subdevice = PCI_ANY_ID,
949 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
950 },
951
952 {
953 .vendor = PCI_VENDOR_ID_INTEL,
954 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
955 .subvendor = PCI_ANY_ID,
956 .subdevice = PCI_ANY_ID,
957 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
958 },
959
960 {
961 .vendor = PCI_VENDOR_ID_INTEL,
962 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
963 .subvendor = PCI_ANY_ID,
964 .subdevice = PCI_ANY_ID,
965 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
966 },
967
968 {
969 .vendor = PCI_VENDOR_ID_INTEL,
970 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
971 .subvendor = PCI_ANY_ID,
972 .subdevice = PCI_ANY_ID,
973 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
974 },
975
976 {
977 .vendor = PCI_VENDOR_ID_INTEL,
978 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
979 .subvendor = PCI_ANY_ID,
980 .subdevice = PCI_ANY_ID,
981 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
982 },
983
984 {
985 .vendor = PCI_VENDOR_ID_INTEL,
986 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
987 .subvendor = PCI_ANY_ID,
988 .subdevice = PCI_ANY_ID,
989 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
990 },
991
992 {
993 .vendor = PCI_VENDOR_ID_INTEL,
994 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
995 .subvendor = PCI_ANY_ID,
996 .subdevice = PCI_ANY_ID,
997 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
998 },
999
1000 {
1001 .vendor = PCI_VENDOR_ID_INTEL,
1002 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1003 .subvendor = PCI_ANY_ID,
1004 .subdevice = PCI_ANY_ID,
1005 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1006 },
1007
1008 {
1009 .vendor = PCI_VENDOR_ID_INTEL,
1010 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1011 .subvendor = PCI_ANY_ID,
1012 .subdevice = PCI_ANY_ID,
1013 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1014 },
1015
1016 {
1017 .vendor = PCI_VENDOR_ID_INTEL,
1018 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1019 .subvendor = PCI_ANY_ID,
1020 .subdevice = PCI_ANY_ID,
1021 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1022 },
1023
1024 {
1025 .vendor = PCI_VENDOR_ID_INTEL,
1026 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1027 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID,
1029 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1030 },
1031
1032 {
1033 .vendor = PCI_VENDOR_ID_O2,
1034 .device = PCI_DEVICE_ID_O2_8120,
1035 .subvendor = PCI_ANY_ID,
1036 .subdevice = PCI_ANY_ID,
1037 .driver_data = (kernel_ulong_t)&sdhci_o2,
1038 },
1039
1040 {
1041 .vendor = PCI_VENDOR_ID_O2,
1042 .device = PCI_DEVICE_ID_O2_8220,
1043 .subvendor = PCI_ANY_ID,
1044 .subdevice = PCI_ANY_ID,
1045 .driver_data = (kernel_ulong_t)&sdhci_o2,
1046 },
1047
1048 {
1049 .vendor = PCI_VENDOR_ID_O2,
1050 .device = PCI_DEVICE_ID_O2_8221,
1051 .subvendor = PCI_ANY_ID,
1052 .subdevice = PCI_ANY_ID,
1053 .driver_data = (kernel_ulong_t)&sdhci_o2,
1054 },
1055
1056 {
1057 .vendor = PCI_VENDOR_ID_O2,
1058 .device = PCI_DEVICE_ID_O2_8320,
1059 .subvendor = PCI_ANY_ID,
1060 .subdevice = PCI_ANY_ID,
1061 .driver_data = (kernel_ulong_t)&sdhci_o2,
1062 },
1063
1064 {
1065 .vendor = PCI_VENDOR_ID_O2,
1066 .device = PCI_DEVICE_ID_O2_8321,
1067 .subvendor = PCI_ANY_ID,
1068 .subdevice = PCI_ANY_ID,
1069 .driver_data = (kernel_ulong_t)&sdhci_o2,
1070 },
1071
1072 { /* Generic SD host controller */
1073 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1074 },
1075
1076 { /* end: all zeroes */ },
1077 };
1078
1079 MODULE_DEVICE_TABLE(pci, pci_ids);
1080
1081 /*****************************************************************************\
1082 * *
1083 * SDHCI core callbacks *
1084 * *
1085 \*****************************************************************************/
1086
1087 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1088 {
1089 struct sdhci_pci_slot *slot;
1090 struct pci_dev *pdev;
1091 int ret;
1092
1093 slot = sdhci_priv(host);
1094 pdev = slot->chip->pdev;
1095
1096 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1097 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1098 (host->flags & SDHCI_USE_SDMA)) {
1099 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1100 "doesn't fully claim to support it.\n");
1101 }
1102
1103 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1104 if (ret)
1105 return ret;
1106
1107 pci_set_master(pdev);
1108
1109 return 0;
1110 }
1111
1112 static int sdhci_pci_bus_width(struct sdhci_host *host, int width)
1113 {
1114 u8 ctrl;
1115
1116 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1117
1118 switch (width) {
1119 case MMC_BUS_WIDTH_8:
1120 ctrl |= SDHCI_CTRL_8BITBUS;
1121 ctrl &= ~SDHCI_CTRL_4BITBUS;
1122 break;
1123 case MMC_BUS_WIDTH_4:
1124 ctrl |= SDHCI_CTRL_4BITBUS;
1125 ctrl &= ~SDHCI_CTRL_8BITBUS;
1126 break;
1127 default:
1128 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1129 break;
1130 }
1131
1132 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1133
1134 return 0;
1135 }
1136
1137 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1138 {
1139 struct sdhci_pci_slot *slot = sdhci_priv(host);
1140 int rst_n_gpio = slot->rst_n_gpio;
1141
1142 if (!gpio_is_valid(rst_n_gpio))
1143 return;
1144 gpio_set_value_cansleep(rst_n_gpio, 0);
1145 /* For eMMC, minimum is 1us but give it 10us for good measure */
1146 udelay(10);
1147 gpio_set_value_cansleep(rst_n_gpio, 1);
1148 /* For eMMC, minimum is 200us but give it 300us for good measure */
1149 usleep_range(300, 1000);
1150 }
1151
1152 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1153 {
1154 struct sdhci_pci_slot *slot = sdhci_priv(host);
1155
1156 if (slot->hw_reset)
1157 slot->hw_reset(host);
1158 }
1159
1160 static const struct sdhci_ops sdhci_pci_ops = {
1161 .enable_dma = sdhci_pci_enable_dma,
1162 .platform_bus_width = sdhci_pci_bus_width,
1163 .hw_reset = sdhci_pci_hw_reset,
1164 };
1165
1166 /*****************************************************************************\
1167 * *
1168 * Suspend/resume *
1169 * *
1170 \*****************************************************************************/
1171
1172 #ifdef CONFIG_PM
1173
1174 static int sdhci_pci_suspend(struct device *dev)
1175 {
1176 struct pci_dev *pdev = to_pci_dev(dev);
1177 struct sdhci_pci_chip *chip;
1178 struct sdhci_pci_slot *slot;
1179 mmc_pm_flag_t slot_pm_flags;
1180 mmc_pm_flag_t pm_flags = 0;
1181 int i, ret;
1182
1183 chip = pci_get_drvdata(pdev);
1184 if (!chip)
1185 return 0;
1186
1187 for (i = 0; i < chip->num_slots; i++) {
1188 slot = chip->slots[i];
1189 if (!slot)
1190 continue;
1191
1192 ret = sdhci_suspend_host(slot->host);
1193
1194 if (ret)
1195 goto err_pci_suspend;
1196
1197 slot_pm_flags = slot->host->mmc->pm_flags;
1198 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1199 sdhci_enable_irq_wakeups(slot->host);
1200
1201 pm_flags |= slot_pm_flags;
1202 }
1203
1204 if (chip->fixes && chip->fixes->suspend) {
1205 ret = chip->fixes->suspend(chip);
1206 if (ret)
1207 goto err_pci_suspend;
1208 }
1209
1210 pci_save_state(pdev);
1211 if (pm_flags & MMC_PM_KEEP_POWER) {
1212 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1213 pci_pme_active(pdev, true);
1214 pci_enable_wake(pdev, PCI_D3hot, 1);
1215 }
1216 pci_set_power_state(pdev, PCI_D3hot);
1217 } else {
1218 pci_enable_wake(pdev, PCI_D3hot, 0);
1219 pci_disable_device(pdev);
1220 pci_set_power_state(pdev, PCI_D3hot);
1221 }
1222
1223 return 0;
1224
1225 err_pci_suspend:
1226 while (--i >= 0)
1227 sdhci_resume_host(chip->slots[i]->host);
1228 return ret;
1229 }
1230
1231 static int sdhci_pci_resume(struct device *dev)
1232 {
1233 struct pci_dev *pdev = to_pci_dev(dev);
1234 struct sdhci_pci_chip *chip;
1235 struct sdhci_pci_slot *slot;
1236 int i, ret;
1237
1238 chip = pci_get_drvdata(pdev);
1239 if (!chip)
1240 return 0;
1241
1242 pci_set_power_state(pdev, PCI_D0);
1243 pci_restore_state(pdev);
1244 ret = pci_enable_device(pdev);
1245 if (ret)
1246 return ret;
1247
1248 if (chip->fixes && chip->fixes->resume) {
1249 ret = chip->fixes->resume(chip);
1250 if (ret)
1251 return ret;
1252 }
1253
1254 for (i = 0; i < chip->num_slots; i++) {
1255 slot = chip->slots[i];
1256 if (!slot)
1257 continue;
1258
1259 ret = sdhci_resume_host(slot->host);
1260 if (ret)
1261 return ret;
1262 }
1263
1264 return 0;
1265 }
1266
1267 #else /* CONFIG_PM */
1268
1269 #define sdhci_pci_suspend NULL
1270 #define sdhci_pci_resume NULL
1271
1272 #endif /* CONFIG_PM */
1273
1274 #ifdef CONFIG_PM_RUNTIME
1275
1276 static int sdhci_pci_runtime_suspend(struct device *dev)
1277 {
1278 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1279 struct sdhci_pci_chip *chip;
1280 struct sdhci_pci_slot *slot;
1281 int i, ret;
1282
1283 chip = pci_get_drvdata(pdev);
1284 if (!chip)
1285 return 0;
1286
1287 for (i = 0; i < chip->num_slots; i++) {
1288 slot = chip->slots[i];
1289 if (!slot)
1290 continue;
1291
1292 ret = sdhci_runtime_suspend_host(slot->host);
1293
1294 if (ret)
1295 goto err_pci_runtime_suspend;
1296 }
1297
1298 if (chip->fixes && chip->fixes->suspend) {
1299 ret = chip->fixes->suspend(chip);
1300 if (ret)
1301 goto err_pci_runtime_suspend;
1302 }
1303
1304 return 0;
1305
1306 err_pci_runtime_suspend:
1307 while (--i >= 0)
1308 sdhci_runtime_resume_host(chip->slots[i]->host);
1309 return ret;
1310 }
1311
1312 static int sdhci_pci_runtime_resume(struct device *dev)
1313 {
1314 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1315 struct sdhci_pci_chip *chip;
1316 struct sdhci_pci_slot *slot;
1317 int i, ret;
1318
1319 chip = pci_get_drvdata(pdev);
1320 if (!chip)
1321 return 0;
1322
1323 if (chip->fixes && chip->fixes->resume) {
1324 ret = chip->fixes->resume(chip);
1325 if (ret)
1326 return ret;
1327 }
1328
1329 for (i = 0; i < chip->num_slots; i++) {
1330 slot = chip->slots[i];
1331 if (!slot)
1332 continue;
1333
1334 ret = sdhci_runtime_resume_host(slot->host);
1335 if (ret)
1336 return ret;
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int sdhci_pci_runtime_idle(struct device *dev)
1343 {
1344 return 0;
1345 }
1346
1347 #else
1348
1349 #define sdhci_pci_runtime_suspend NULL
1350 #define sdhci_pci_runtime_resume NULL
1351 #define sdhci_pci_runtime_idle NULL
1352
1353 #endif
1354
1355 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1356 .suspend = sdhci_pci_suspend,
1357 .resume = sdhci_pci_resume,
1358 .runtime_suspend = sdhci_pci_runtime_suspend,
1359 .runtime_resume = sdhci_pci_runtime_resume,
1360 .runtime_idle = sdhci_pci_runtime_idle,
1361 };
1362
1363 /*****************************************************************************\
1364 * *
1365 * Device probing/removal *
1366 * *
1367 \*****************************************************************************/
1368
1369 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1370 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1371 int slotno)
1372 {
1373 struct sdhci_pci_slot *slot;
1374 struct sdhci_host *host;
1375 int ret, bar = first_bar + slotno;
1376
1377 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1378 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1379 return ERR_PTR(-ENODEV);
1380 }
1381
1382 if (pci_resource_len(pdev, bar) < 0x100) {
1383 dev_err(&pdev->dev, "Invalid iomem size. You may "
1384 "experience problems.\n");
1385 }
1386
1387 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1388 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1389 return ERR_PTR(-ENODEV);
1390 }
1391
1392 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1393 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1394 return ERR_PTR(-ENODEV);
1395 }
1396
1397 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1398 if (IS_ERR(host)) {
1399 dev_err(&pdev->dev, "cannot allocate host\n");
1400 return ERR_CAST(host);
1401 }
1402
1403 slot = sdhci_priv(host);
1404
1405 slot->chip = chip;
1406 slot->host = host;
1407 slot->pci_bar = bar;
1408 slot->rst_n_gpio = -EINVAL;
1409 slot->cd_gpio = -EINVAL;
1410
1411 /* Retrieve platform data if there is any */
1412 if (*sdhci_pci_get_data)
1413 slot->data = sdhci_pci_get_data(pdev, slotno);
1414
1415 if (slot->data) {
1416 if (slot->data->setup) {
1417 ret = slot->data->setup(slot->data);
1418 if (ret) {
1419 dev_err(&pdev->dev, "platform setup failed\n");
1420 goto free;
1421 }
1422 }
1423 slot->rst_n_gpio = slot->data->rst_n_gpio;
1424 slot->cd_gpio = slot->data->cd_gpio;
1425 }
1426
1427 host->hw_name = "PCI";
1428 host->ops = &sdhci_pci_ops;
1429 host->quirks = chip->quirks;
1430 host->quirks2 = chip->quirks2;
1431
1432 host->irq = pdev->irq;
1433
1434 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1435 if (ret) {
1436 dev_err(&pdev->dev, "cannot request region\n");
1437 goto cleanup;
1438 }
1439
1440 host->ioaddr = pci_ioremap_bar(pdev, bar);
1441 if (!host->ioaddr) {
1442 dev_err(&pdev->dev, "failed to remap registers\n");
1443 ret = -ENOMEM;
1444 goto release;
1445 }
1446
1447 if (chip->fixes && chip->fixes->probe_slot) {
1448 ret = chip->fixes->probe_slot(slot);
1449 if (ret)
1450 goto unmap;
1451 }
1452
1453 if (gpio_is_valid(slot->rst_n_gpio)) {
1454 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1455 gpio_direction_output(slot->rst_n_gpio, 1);
1456 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1457 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1458 } else {
1459 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1460 slot->rst_n_gpio = -EINVAL;
1461 }
1462 }
1463
1464 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1465 host->mmc->slotno = slotno;
1466 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1467
1468 ret = sdhci_add_host(host);
1469 if (ret)
1470 goto remove;
1471
1472 sdhci_pci_add_own_cd(slot);
1473
1474 /*
1475 * Check if the chip needs a separate GPIO for card detect to wake up
1476 * from runtime suspend. If it is not there, don't allow runtime PM.
1477 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1478 */
1479 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1480 !gpio_is_valid(slot->cd_gpio))
1481 chip->allow_runtime_pm = false;
1482
1483 return slot;
1484
1485 remove:
1486 if (gpio_is_valid(slot->rst_n_gpio))
1487 gpio_free(slot->rst_n_gpio);
1488
1489 if (chip->fixes && chip->fixes->remove_slot)
1490 chip->fixes->remove_slot(slot, 0);
1491
1492 unmap:
1493 iounmap(host->ioaddr);
1494
1495 release:
1496 pci_release_region(pdev, bar);
1497
1498 cleanup:
1499 if (slot->data && slot->data->cleanup)
1500 slot->data->cleanup(slot->data);
1501
1502 free:
1503 sdhci_free_host(host);
1504
1505 return ERR_PTR(ret);
1506 }
1507
1508 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1509 {
1510 int dead;
1511 u32 scratch;
1512
1513 sdhci_pci_remove_own_cd(slot);
1514
1515 dead = 0;
1516 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1517 if (scratch == (u32)-1)
1518 dead = 1;
1519
1520 sdhci_remove_host(slot->host, dead);
1521
1522 if (gpio_is_valid(slot->rst_n_gpio))
1523 gpio_free(slot->rst_n_gpio);
1524
1525 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1526 slot->chip->fixes->remove_slot(slot, dead);
1527
1528 if (slot->data && slot->data->cleanup)
1529 slot->data->cleanup(slot->data);
1530
1531 pci_release_region(slot->chip->pdev, slot->pci_bar);
1532
1533 sdhci_free_host(slot->host);
1534 }
1535
1536 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1537 {
1538 pm_runtime_put_noidle(dev);
1539 pm_runtime_allow(dev);
1540 pm_runtime_set_autosuspend_delay(dev, 50);
1541 pm_runtime_use_autosuspend(dev);
1542 pm_suspend_ignore_children(dev, 1);
1543 }
1544
1545 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1546 {
1547 pm_runtime_forbid(dev);
1548 pm_runtime_get_noresume(dev);
1549 }
1550
1551 static int sdhci_pci_probe(struct pci_dev *pdev,
1552 const struct pci_device_id *ent)
1553 {
1554 struct sdhci_pci_chip *chip;
1555 struct sdhci_pci_slot *slot;
1556
1557 u8 slots, first_bar;
1558 int ret, i;
1559
1560 BUG_ON(pdev == NULL);
1561 BUG_ON(ent == NULL);
1562
1563 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1564 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1565
1566 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1567 if (ret)
1568 return ret;
1569
1570 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1571 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1572 if (slots == 0)
1573 return -ENODEV;
1574
1575 BUG_ON(slots > MAX_SLOTS);
1576
1577 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1578 if (ret)
1579 return ret;
1580
1581 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1582
1583 if (first_bar > 5) {
1584 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1585 return -ENODEV;
1586 }
1587
1588 ret = pci_enable_device(pdev);
1589 if (ret)
1590 return ret;
1591
1592 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1593 if (!chip) {
1594 ret = -ENOMEM;
1595 goto err;
1596 }
1597
1598 chip->pdev = pdev;
1599 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1600 if (chip->fixes) {
1601 chip->quirks = chip->fixes->quirks;
1602 chip->quirks2 = chip->fixes->quirks2;
1603 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1604 }
1605 chip->num_slots = slots;
1606
1607 pci_set_drvdata(pdev, chip);
1608
1609 if (chip->fixes && chip->fixes->probe) {
1610 ret = chip->fixes->probe(chip);
1611 if (ret)
1612 goto free;
1613 }
1614
1615 slots = chip->num_slots; /* Quirk may have changed this */
1616
1617 for (i = 0; i < slots; i++) {
1618 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1619 if (IS_ERR(slot)) {
1620 for (i--; i >= 0; i--)
1621 sdhci_pci_remove_slot(chip->slots[i]);
1622 ret = PTR_ERR(slot);
1623 goto free;
1624 }
1625
1626 chip->slots[i] = slot;
1627 }
1628
1629 if (chip->allow_runtime_pm)
1630 sdhci_pci_runtime_pm_allow(&pdev->dev);
1631
1632 return 0;
1633
1634 free:
1635 pci_set_drvdata(pdev, NULL);
1636 kfree(chip);
1637
1638 err:
1639 pci_disable_device(pdev);
1640 return ret;
1641 }
1642
1643 static void sdhci_pci_remove(struct pci_dev *pdev)
1644 {
1645 int i;
1646 struct sdhci_pci_chip *chip;
1647
1648 chip = pci_get_drvdata(pdev);
1649
1650 if (chip) {
1651 if (chip->allow_runtime_pm)
1652 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1653
1654 for (i = 0; i < chip->num_slots; i++)
1655 sdhci_pci_remove_slot(chip->slots[i]);
1656
1657 pci_set_drvdata(pdev, NULL);
1658 kfree(chip);
1659 }
1660
1661 pci_disable_device(pdev);
1662 }
1663
1664 static struct pci_driver sdhci_driver = {
1665 .name = "sdhci-pci",
1666 .id_table = pci_ids,
1667 .probe = sdhci_pci_probe,
1668 .remove = sdhci_pci_remove,
1669 .driver = {
1670 .pm = &sdhci_pci_pm_ops
1671 },
1672 };
1673
1674 module_pci_driver(sdhci_driver);
1675
1676 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1677 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1678 MODULE_LICENSE("GPL");
Linux with added FPC-III support