8 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
9 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
10 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
11 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
12 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
13 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
14 #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
15 #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
16 #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
17 #define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
18 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
19 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
20 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
21 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
22 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
23 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
24 #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
25 #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
26 #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
32 #define PCI_SDHCI_IFPIO 0x00
33 #define PCI_SDHCI_IFDMA 0x01
34 #define PCI_SDHCI_IFVENDOR 0x02
36 #define PCI_SLOT_INFO 0x40 /* 8 bits */
37 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
38 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
42 struct sdhci_pci_chip
;
43 struct sdhci_pci_slot
;
45 struct sdhci_pci_fixes
{
48 bool allow_runtime_pm
;
49 bool own_cd_for_runtime_pm
;
51 int (*probe
) (struct sdhci_pci_chip
*);
53 int (*probe_slot
) (struct sdhci_pci_slot
*);
54 void (*remove_slot
) (struct sdhci_pci_slot
*, int);
56 int (*suspend
) (struct sdhci_pci_chip
*);
57 int (*resume
) (struct sdhci_pci_chip
*);
60 struct sdhci_pci_slot
{
61 struct sdhci_pci_chip
*chip
;
62 struct sdhci_host
*host
;
63 struct sdhci_pci_data
*data
;
70 void (*hw_reset
)(struct sdhci_host
*host
);
73 struct sdhci_pci_chip
{
78 bool allow_runtime_pm
;
79 const struct sdhci_pci_fixes
*fixes
;
81 int num_slots
; /* Slots on controller */
82 struct sdhci_pci_slot
*slots
[MAX_SLOTS
]; /* Pointers to host slots */
85 #endif /* __SDHCI_PCI_H */