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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / mmc / host / sdhci.c
blob4e697ea67ae2bc6900010c5e929ad93ddedee838
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
32
33 #include "sdhci.h"
34
35 #define DRIVER_NAME "sdhci"
36
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
43 #endif
44
45 #define MAX_TUNING_LOOP 40
46
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
49
50 static void sdhci_finish_data(struct sdhci_host *);
51
52 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_tuning_timer(unsigned long data);
56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57
58 #ifdef CONFIG_PM_RUNTIME
59 static int sdhci_runtime_pm_get(struct sdhci_host *host);
60 static int sdhci_runtime_pm_put(struct sdhci_host *host);
61 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
63 #else
64 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65 {
66 return 0;
67 }
68 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69 {
70 return 0;
71 }
72 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73 {
74 }
75 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76 {
77 }
78 #endif
79
80 static void sdhci_dumpregs(struct sdhci_host *host)
81 {
82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
83 mmc_hostname(host->mmc));
84
85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
113 sdhci_readl(host, SDHCI_CAPABILITIES),
114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
116 sdhci_readw(host, SDHCI_COMMAND),
117 sdhci_readl(host, SDHCI_MAX_CURRENT));
118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
120
121 if (host->flags & SDHCI_USE_ADMA)
122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
125
126 pr_debug(DRIVER_NAME ": ===========================================\n");
127 }
128
129 /*****************************************************************************\
130 * *
131 * Low level functions *
132 * *
133 \*****************************************************************************/
134
135 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
136 {
137 u32 ier;
138
139 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
140 ier &= ~clear;
141 ier |= set;
142 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
143 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
144 }
145
146 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
147 {
148 sdhci_clear_set_irqs(host, 0, irqs);
149 }
150
151 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
152 {
153 sdhci_clear_set_irqs(host, irqs, 0);
154 }
155
156 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
157 {
158 u32 present, irqs;
159
160 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
161 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
162 return;
163
164 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT;
166 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
167
168 if (enable)
169 sdhci_unmask_irqs(host, irqs);
170 else
171 sdhci_mask_irqs(host, irqs);
172 }
173
174 static void sdhci_enable_card_detection(struct sdhci_host *host)
175 {
176 sdhci_set_card_detection(host, true);
177 }
178
179 static void sdhci_disable_card_detection(struct sdhci_host *host)
180 {
181 sdhci_set_card_detection(host, false);
182 }
183
184 static void sdhci_reset(struct sdhci_host *host, u8 mask)
185 {
186 unsigned long timeout;
187 u32 uninitialized_var(ier);
188
189 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
190 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
191 SDHCI_CARD_PRESENT))
192 return;
193 }
194
195 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
196 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
197
198 if (host->ops->platform_reset_enter)
199 host->ops->platform_reset_enter(host, mask);
200
201 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
202
203 if (mask & SDHCI_RESET_ALL) {
204 host->clock = 0;
205 /* Reset-all turns off SD Bus Power */
206 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
207 sdhci_runtime_pm_bus_off(host);
208 }
209
210 /* Wait max 100 ms */
211 timeout = 100;
212
213 /* hw clears the bit when it's done */
214 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
215 if (timeout == 0) {
216 pr_err("%s: Reset 0x%x never completed.\n",
217 mmc_hostname(host->mmc), (int)mask);
218 sdhci_dumpregs(host);
219 return;
220 }
221 timeout--;
222 mdelay(1);
223 }
224
225 if (host->ops->platform_reset_exit)
226 host->ops->platform_reset_exit(host, mask);
227
228 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
229 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
230
231 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
232 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
233 host->ops->enable_dma(host);
234 }
235 }
236
237 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
238
239 static void sdhci_init(struct sdhci_host *host, int soft)
240 {
241 if (soft)
242 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
243 else
244 sdhci_reset(host, SDHCI_RESET_ALL);
245
246 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
247 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
248 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
249 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
250 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
251
252 if (soft) {
253 /* force clock reconfiguration */
254 host->clock = 0;
255 sdhci_set_ios(host->mmc, &host->mmc->ios);
256 }
257 }
258
259 static void sdhci_reinit(struct sdhci_host *host)
260 {
261 sdhci_init(host, 0);
262 /*
263 * Retuning stuffs are affected by different cards inserted and only
264 * applicable to UHS-I cards. So reset these fields to their initial
265 * value when card is removed.
266 */
267 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
268 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
269
270 del_timer_sync(&host->tuning_timer);
271 host->flags &= ~SDHCI_NEEDS_RETUNING;
272 host->mmc->max_blk_count =
273 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
274 }
275 sdhci_enable_card_detection(host);
276 }
277
278 static void sdhci_activate_led(struct sdhci_host *host)
279 {
280 u8 ctrl;
281
282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
283 ctrl |= SDHCI_CTRL_LED;
284 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
285 }
286
287 static void sdhci_deactivate_led(struct sdhci_host *host)
288 {
289 u8 ctrl;
290
291 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
292 ctrl &= ~SDHCI_CTRL_LED;
293 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
294 }
295
296 #ifdef SDHCI_USE_LEDS_CLASS
297 static void sdhci_led_control(struct led_classdev *led,
298 enum led_brightness brightness)
299 {
300 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
301 unsigned long flags;
302
303 spin_lock_irqsave(&host->lock, flags);
304
305 if (host->runtime_suspended)
306 goto out;
307
308 if (brightness == LED_OFF)
309 sdhci_deactivate_led(host);
310 else
311 sdhci_activate_led(host);
312 out:
313 spin_unlock_irqrestore(&host->lock, flags);
314 }
315 #endif
316
317 /*****************************************************************************\
318 * *
319 * Core functions *
320 * *
321 \*****************************************************************************/
322
323 static void sdhci_read_block_pio(struct sdhci_host *host)
324 {
325 unsigned long flags;
326 size_t blksize, len, chunk;
327 u32 uninitialized_var(scratch);
328 u8 *buf;
329
330 DBG("PIO reading\n");
331
332 blksize = host->data->blksz;
333 chunk = 0;
334
335 local_irq_save(flags);
336
337 while (blksize) {
338 if (!sg_miter_next(&host->sg_miter))
339 BUG();
340
341 len = min(host->sg_miter.length, blksize);
342
343 blksize -= len;
344 host->sg_miter.consumed = len;
345
346 buf = host->sg_miter.addr;
347
348 while (len) {
349 if (chunk == 0) {
350 scratch = sdhci_readl(host, SDHCI_BUFFER);
351 chunk = 4;
352 }
353
354 *buf = scratch & 0xFF;
355
356 buf++;
357 scratch >>= 8;
358 chunk--;
359 len--;
360 }
361 }
362
363 sg_miter_stop(&host->sg_miter);
364
365 local_irq_restore(flags);
366 }
367
368 static void sdhci_write_block_pio(struct sdhci_host *host)
369 {
370 unsigned long flags;
371 size_t blksize, len, chunk;
372 u32 scratch;
373 u8 *buf;
374
375 DBG("PIO writing\n");
376
377 blksize = host->data->blksz;
378 chunk = 0;
379 scratch = 0;
380
381 local_irq_save(flags);
382
383 while (blksize) {
384 if (!sg_miter_next(&host->sg_miter))
385 BUG();
386
387 len = min(host->sg_miter.length, blksize);
388
389 blksize -= len;
390 host->sg_miter.consumed = len;
391
392 buf = host->sg_miter.addr;
393
394 while (len) {
395 scratch |= (u32)*buf << (chunk * 8);
396
397 buf++;
398 chunk++;
399 len--;
400
401 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
402 sdhci_writel(host, scratch, SDHCI_BUFFER);
403 chunk = 0;
404 scratch = 0;
405 }
406 }
407 }
408
409 sg_miter_stop(&host->sg_miter);
410
411 local_irq_restore(flags);
412 }
413
414 static void sdhci_transfer_pio(struct sdhci_host *host)
415 {
416 u32 mask;
417
418 BUG_ON(!host->data);
419
420 if (host->blocks == 0)
421 return;
422
423 if (host->data->flags & MMC_DATA_READ)
424 mask = SDHCI_DATA_AVAILABLE;
425 else
426 mask = SDHCI_SPACE_AVAILABLE;
427
428 /*
429 * Some controllers (JMicron JMB38x) mess up the buffer bits
430 * for transfers < 4 bytes. As long as it is just one block,
431 * we can ignore the bits.
432 */
433 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
434 (host->data->blocks == 1))
435 mask = ~0;
436
437 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
438 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
439 udelay(100);
440
441 if (host->data->flags & MMC_DATA_READ)
442 sdhci_read_block_pio(host);
443 else
444 sdhci_write_block_pio(host);
445
446 host->blocks--;
447 if (host->blocks == 0)
448 break;
449 }
450
451 DBG("PIO transfer complete.\n");
452 }
453
454 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455 {
456 local_irq_save(*flags);
457 return kmap_atomic(sg_page(sg)) + sg->offset;
458 }
459
460 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461 {
462 kunmap_atomic(buffer);
463 local_irq_restore(*flags);
464 }
465
466 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
467 {
468 __le32 *dataddr = (__le32 __force *)(desc + 4);
469 __le16 *cmdlen = (__le16 __force *)desc;
470
471 /* SDHCI specification says ADMA descriptors should be 4 byte
472 * aligned, so using 16 or 32bit operations should be safe. */
473
474 cmdlen[0] = cpu_to_le16(cmd);
475 cmdlen[1] = cpu_to_le16(len);
476
477 dataddr[0] = cpu_to_le32(addr);
478 }
479
480 static int sdhci_adma_table_pre(struct sdhci_host *host,
481 struct mmc_data *data)
482 {
483 int direction;
484
485 u8 *desc;
486 u8 *align;
487 dma_addr_t addr;
488 dma_addr_t align_addr;
489 int len, offset;
490
491 struct scatterlist *sg;
492 int i;
493 char *buffer;
494 unsigned long flags;
495
496 /*
497 * The spec does not specify endianness of descriptor table.
498 * We currently guess that it is LE.
499 */
500
501 if (data->flags & MMC_DATA_READ)
502 direction = DMA_FROM_DEVICE;
503 else
504 direction = DMA_TO_DEVICE;
505
506 /*
507 * The ADMA descriptor table is mapped further down as we
508 * need to fill it with data first.
509 */
510
511 host->align_addr = dma_map_single(mmc_dev(host->mmc),
512 host->align_buffer, 128 * 4, direction);
513 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
514 goto fail;
515 BUG_ON(host->align_addr & 0x3);
516
517 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
518 data->sg, data->sg_len, direction);
519 if (host->sg_count == 0)
520 goto unmap_align;
521
522 desc = host->adma_desc;
523 align = host->align_buffer;
524
525 align_addr = host->align_addr;
526
527 for_each_sg(data->sg, sg, host->sg_count, i) {
528 addr = sg_dma_address(sg);
529 len = sg_dma_len(sg);
530
531 /*
532 * The SDHCI specification states that ADMA
533 * addresses must be 32-bit aligned. If they
534 * aren't, then we use a bounce buffer for
535 * the (up to three) bytes that screw up the
536 * alignment.
537 */
538 offset = (4 - (addr & 0x3)) & 0x3;
539 if (offset) {
540 if (data->flags & MMC_DATA_WRITE) {
541 buffer = sdhci_kmap_atomic(sg, &flags);
542 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
543 memcpy(align, buffer, offset);
544 sdhci_kunmap_atomic(buffer, &flags);
545 }
546
547 /* tran, valid */
548 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
549
550 BUG_ON(offset > 65536);
551
552 align += 4;
553 align_addr += 4;
554
555 desc += 8;
556
557 addr += offset;
558 len -= offset;
559 }
560
561 BUG_ON(len > 65536);
562
563 /* tran, valid */
564 sdhci_set_adma_desc(desc, addr, len, 0x21);
565 desc += 8;
566
567 /*
568 * If this triggers then we have a calculation bug
569 * somewhere. :/
570 */
571 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
572 }
573
574 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
575 /*
576 * Mark the last descriptor as the terminating descriptor
577 */
578 if (desc != host->adma_desc) {
579 desc -= 8;
580 desc[0] |= 0x2; /* end */
581 }
582 } else {
583 /*
584 * Add a terminating entry.
585 */
586
587 /* nop, end, valid */
588 sdhci_set_adma_desc(desc, 0, 0, 0x3);
589 }
590
591 /*
592 * Resync align buffer as we might have changed it.
593 */
594 if (data->flags & MMC_DATA_WRITE) {
595 dma_sync_single_for_device(mmc_dev(host->mmc),
596 host->align_addr, 128 * 4, direction);
597 }
598
599 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
600 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
601 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
602 goto unmap_entries;
603 BUG_ON(host->adma_addr & 0x3);
604
605 return 0;
606
607 unmap_entries:
608 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
609 data->sg_len, direction);
610 unmap_align:
611 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
612 128 * 4, direction);
613 fail:
614 return -EINVAL;
615 }
616
617 static void sdhci_adma_table_post(struct sdhci_host *host,
618 struct mmc_data *data)
619 {
620 int direction;
621
622 struct scatterlist *sg;
623 int i, size;
624 u8 *align;
625 char *buffer;
626 unsigned long flags;
627
628 if (data->flags & MMC_DATA_READ)
629 direction = DMA_FROM_DEVICE;
630 else
631 direction = DMA_TO_DEVICE;
632
633 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
634 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
635
636 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
637 128 * 4, direction);
638
639 if (data->flags & MMC_DATA_READ) {
640 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
641 data->sg_len, direction);
642
643 align = host->align_buffer;
644
645 for_each_sg(data->sg, sg, host->sg_count, i) {
646 if (sg_dma_address(sg) & 0x3) {
647 size = 4 - (sg_dma_address(sg) & 0x3);
648
649 buffer = sdhci_kmap_atomic(sg, &flags);
650 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
651 memcpy(buffer, align, size);
652 sdhci_kunmap_atomic(buffer, &flags);
653
654 align += 4;
655 }
656 }
657 }
658
659 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
660 data->sg_len, direction);
661 }
662
663 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
664 {
665 u8 count;
666 struct mmc_data *data = cmd->data;
667 unsigned target_timeout, current_timeout;
668
669 /*
670 * If the host controller provides us with an incorrect timeout
671 * value, just skip the check and use 0xE. The hardware may take
672 * longer to time out, but that's much better than having a too-short
673 * timeout value.
674 */
675 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
676 return 0xE;
677
678 /* Unspecified timeout, assume max */
679 if (!data && !cmd->cmd_timeout_ms)
680 return 0xE;
681
682 /* timeout in us */
683 if (!data)
684 target_timeout = cmd->cmd_timeout_ms * 1000;
685 else {
686 target_timeout = data->timeout_ns / 1000;
687 if (host->clock)
688 target_timeout += data->timeout_clks / host->clock;
689 }
690
691 /*
692 * Figure out needed cycles.
693 * We do this in steps in order to fit inside a 32 bit int.
694 * The first step is the minimum timeout, which will have a
695 * minimum resolution of 6 bits:
696 * (1) 2^13*1000 > 2^22,
697 * (2) host->timeout_clk < 2^16
698 * =>
699 * (1) / (2) > 2^6
700 */
701 count = 0;
702 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
703 while (current_timeout < target_timeout) {
704 count++;
705 current_timeout <<= 1;
706 if (count >= 0xF)
707 break;
708 }
709
710 if (count >= 0xF) {
711 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
712 mmc_hostname(host->mmc), count, cmd->opcode);
713 count = 0xE;
714 }
715
716 return count;
717 }
718
719 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
720 {
721 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
722 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
723
724 if (host->flags & SDHCI_REQ_USE_DMA)
725 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
726 else
727 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
728 }
729
730 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
731 {
732 u8 count;
733 u8 ctrl;
734 struct mmc_data *data = cmd->data;
735 int ret;
736
737 WARN_ON(host->data);
738
739 if (data || (cmd->flags & MMC_RSP_BUSY)) {
740 count = sdhci_calc_timeout(host, cmd);
741 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
742 }
743
744 if (!data)
745 return;
746
747 /* Sanity checks */
748 BUG_ON(data->blksz * data->blocks > 524288);
749 BUG_ON(data->blksz > host->mmc->max_blk_size);
750 BUG_ON(data->blocks > 65535);
751
752 host->data = data;
753 host->data_early = 0;
754 host->data->bytes_xfered = 0;
755
756 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
757 host->flags |= SDHCI_REQ_USE_DMA;
758
759 /*
760 * FIXME: This doesn't account for merging when mapping the
761 * scatterlist.
762 */
763 if (host->flags & SDHCI_REQ_USE_DMA) {
764 int broken, i;
765 struct scatterlist *sg;
766
767 broken = 0;
768 if (host->flags & SDHCI_USE_ADMA) {
769 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
770 broken = 1;
771 } else {
772 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
773 broken = 1;
774 }
775
776 if (unlikely(broken)) {
777 for_each_sg(data->sg, sg, data->sg_len, i) {
778 if (sg->length & 0x3) {
779 DBG("Reverting to PIO because of "
780 "transfer size (%d)\n",
781 sg->length);
782 host->flags &= ~SDHCI_REQ_USE_DMA;
783 break;
784 }
785 }
786 }
787 }
788
789 /*
790 * The assumption here being that alignment is the same after
791 * translation to device address space.
792 */
793 if (host->flags & SDHCI_REQ_USE_DMA) {
794 int broken, i;
795 struct scatterlist *sg;
796
797 broken = 0;
798 if (host->flags & SDHCI_USE_ADMA) {
799 /*
800 * As we use 3 byte chunks to work around
801 * alignment problems, we need to check this
802 * quirk.
803 */
804 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
805 broken = 1;
806 } else {
807 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
808 broken = 1;
809 }
810
811 if (unlikely(broken)) {
812 for_each_sg(data->sg, sg, data->sg_len, i) {
813 if (sg->offset & 0x3) {
814 DBG("Reverting to PIO because of "
815 "bad alignment\n");
816 host->flags &= ~SDHCI_REQ_USE_DMA;
817 break;
818 }
819 }
820 }
821 }
822
823 if (host->flags & SDHCI_REQ_USE_DMA) {
824 if (host->flags & SDHCI_USE_ADMA) {
825 ret = sdhci_adma_table_pre(host, data);
826 if (ret) {
827 /*
828 * This only happens when someone fed
829 * us an invalid request.
830 */
831 WARN_ON(1);
832 host->flags &= ~SDHCI_REQ_USE_DMA;
833 } else {
834 sdhci_writel(host, host->adma_addr,
835 SDHCI_ADMA_ADDRESS);
836 }
837 } else {
838 int sg_cnt;
839
840 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
841 data->sg, data->sg_len,
842 (data->flags & MMC_DATA_READ) ?
843 DMA_FROM_DEVICE :
844 DMA_TO_DEVICE);
845 if (sg_cnt == 0) {
846 /*
847 * This only happens when someone fed
848 * us an invalid request.
849 */
850 WARN_ON(1);
851 host->flags &= ~SDHCI_REQ_USE_DMA;
852 } else {
853 WARN_ON(sg_cnt != 1);
854 sdhci_writel(host, sg_dma_address(data->sg),
855 SDHCI_DMA_ADDRESS);
856 }
857 }
858 }
859
860 /*
861 * Always adjust the DMA selection as some controllers
862 * (e.g. JMicron) can't do PIO properly when the selection
863 * is ADMA.
864 */
865 if (host->version >= SDHCI_SPEC_200) {
866 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
867 ctrl &= ~SDHCI_CTRL_DMA_MASK;
868 if ((host->flags & SDHCI_REQ_USE_DMA) &&
869 (host->flags & SDHCI_USE_ADMA))
870 ctrl |= SDHCI_CTRL_ADMA32;
871 else
872 ctrl |= SDHCI_CTRL_SDMA;
873 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
874 }
875
876 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
877 int flags;
878
879 flags = SG_MITER_ATOMIC;
880 if (host->data->flags & MMC_DATA_READ)
881 flags |= SG_MITER_TO_SG;
882 else
883 flags |= SG_MITER_FROM_SG;
884 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
885 host->blocks = data->blocks;
886 }
887
888 sdhci_set_transfer_irqs(host);
889
890 /* Set the DMA boundary value and block size */
891 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
892 data->blksz), SDHCI_BLOCK_SIZE);
893 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
894 }
895
896 static void sdhci_set_transfer_mode(struct sdhci_host *host,
897 struct mmc_command *cmd)
898 {
899 u16 mode;
900 struct mmc_data *data = cmd->data;
901
902 if (data == NULL)
903 return;
904
905 WARN_ON(!host->data);
906
907 mode = SDHCI_TRNS_BLK_CNT_EN;
908 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
909 mode |= SDHCI_TRNS_MULTI;
910 /*
911 * If we are sending CMD23, CMD12 never gets sent
912 * on successful completion (so no Auto-CMD12).
913 */
914 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
915 mode |= SDHCI_TRNS_AUTO_CMD12;
916 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
917 mode |= SDHCI_TRNS_AUTO_CMD23;
918 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
919 }
920 }
921
922 if (data->flags & MMC_DATA_READ)
923 mode |= SDHCI_TRNS_READ;
924 if (host->flags & SDHCI_REQ_USE_DMA)
925 mode |= SDHCI_TRNS_DMA;
926
927 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
928 }
929
930 static void sdhci_finish_data(struct sdhci_host *host)
931 {
932 struct mmc_data *data;
933
934 BUG_ON(!host->data);
935
936 data = host->data;
937 host->data = NULL;
938
939 if (host->flags & SDHCI_REQ_USE_DMA) {
940 if (host->flags & SDHCI_USE_ADMA)
941 sdhci_adma_table_post(host, data);
942 else {
943 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
944 data->sg_len, (data->flags & MMC_DATA_READ) ?
945 DMA_FROM_DEVICE : DMA_TO_DEVICE);
946 }
947 }
948
949 /*
950 * The specification states that the block count register must
951 * be updated, but it does not specify at what point in the
952 * data flow. That makes the register entirely useless to read
953 * back so we have to assume that nothing made it to the card
954 * in the event of an error.
955 */
956 if (data->error)
957 data->bytes_xfered = 0;
958 else
959 data->bytes_xfered = data->blksz * data->blocks;
960
961 /*
962 * Need to send CMD12 if -
963 * a) open-ended multiblock transfer (no CMD23)
964 * b) error in multiblock transfer
965 */
966 if (data->stop &&
967 (data->error ||
968 !host->mrq->sbc)) {
969
970 /*
971 * The controller needs a reset of internal state machines
972 * upon error conditions.
973 */
974 if (data->error) {
975 sdhci_reset(host, SDHCI_RESET_CMD);
976 sdhci_reset(host, SDHCI_RESET_DATA);
977 }
978
979 sdhci_send_command(host, data->stop);
980 } else
981 tasklet_schedule(&host->finish_tasklet);
982 }
983
984 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
985 {
986 int flags;
987 u32 mask;
988 unsigned long timeout;
989
990 WARN_ON(host->cmd);
991
992 /* Wait max 10 ms */
993 timeout = 10;
994
995 mask = SDHCI_CMD_INHIBIT;
996 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
997 mask |= SDHCI_DATA_INHIBIT;
998
999 /* We shouldn't wait for data inihibit for stop commands, even
1000 though they might use busy signaling */
1001 if (host->mrq->data && (cmd == host->mrq->data->stop))
1002 mask &= ~SDHCI_DATA_INHIBIT;
1003
1004 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1005 if (timeout == 0) {
1006 pr_err("%s: Controller never released "
1007 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1008 sdhci_dumpregs(host);
1009 cmd->error = -EIO;
1010 tasklet_schedule(&host->finish_tasklet);
1011 return;
1012 }
1013 timeout--;
1014 mdelay(1);
1015 }
1016
1017 mod_timer(&host->timer, jiffies + 10 * HZ);
1018
1019 host->cmd = cmd;
1020
1021 sdhci_prepare_data(host, cmd);
1022
1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1024
1025 sdhci_set_transfer_mode(host, cmd);
1026
1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1028 pr_err("%s: Unsupported response type!\n",
1029 mmc_hostname(host->mmc));
1030 cmd->error = -EINVAL;
1031 tasklet_schedule(&host->finish_tasklet);
1032 return;
1033 }
1034
1035 if (!(cmd->flags & MMC_RSP_PRESENT))
1036 flags = SDHCI_CMD_RESP_NONE;
1037 else if (cmd->flags & MMC_RSP_136)
1038 flags = SDHCI_CMD_RESP_LONG;
1039 else if (cmd->flags & MMC_RSP_BUSY)
1040 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041 else
1042 flags = SDHCI_CMD_RESP_SHORT;
1043
1044 if (cmd->flags & MMC_RSP_CRC)
1045 flags |= SDHCI_CMD_CRC;
1046 if (cmd->flags & MMC_RSP_OPCODE)
1047 flags |= SDHCI_CMD_INDEX;
1048
1049 /* CMD19 is special in that the Data Present Select should be set */
1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1052 flags |= SDHCI_CMD_DATA;
1053
1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1055 }
1056
1057 static void sdhci_finish_command(struct sdhci_host *host)
1058 {
1059 int i;
1060
1061 BUG_ON(host->cmd == NULL);
1062
1063 if (host->cmd->flags & MMC_RSP_PRESENT) {
1064 if (host->cmd->flags & MMC_RSP_136) {
1065 /* CRC is stripped so we need to do some shifting. */
1066 for (i = 0;i < 4;i++) {
1067 host->cmd->resp[i] = sdhci_readl(host,
1068 SDHCI_RESPONSE + (3-i)*4) << 8;
1069 if (i != 3)
1070 host->cmd->resp[i] |=
1071 sdhci_readb(host,
1072 SDHCI_RESPONSE + (3-i)*4-1);
1073 }
1074 } else {
1075 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1076 }
1077 }
1078
1079 host->cmd->error = 0;
1080
1081 /* Finished CMD23, now send actual command. */
1082 if (host->cmd == host->mrq->sbc) {
1083 host->cmd = NULL;
1084 sdhci_send_command(host, host->mrq->cmd);
1085 } else {
1086
1087 /* Processed actual command. */
1088 if (host->data && host->data_early)
1089 sdhci_finish_data(host);
1090
1091 if (!host->cmd->data)
1092 tasklet_schedule(&host->finish_tasklet);
1093
1094 host->cmd = NULL;
1095 }
1096 }
1097
1098 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1099 {
1100 u16 ctrl, preset = 0;
1101
1102 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103
1104 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1105 case SDHCI_CTRL_UHS_SDR12:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1107 break;
1108 case SDHCI_CTRL_UHS_SDR25:
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1110 break;
1111 case SDHCI_CTRL_UHS_SDR50:
1112 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1113 break;
1114 case SDHCI_CTRL_UHS_SDR104:
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
1117 case SDHCI_CTRL_UHS_DDR50:
1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119 break;
1120 default:
1121 pr_warn("%s: Invalid UHS-I mode selected\n",
1122 mmc_hostname(host->mmc));
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124 break;
1125 }
1126 return preset;
1127 }
1128
1129 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1130 {
1131 int div = 0; /* Initialized for compiler warning */
1132 int real_div = div, clk_mul = 1;
1133 u16 clk = 0;
1134 unsigned long timeout;
1135
1136 if (clock && clock == host->clock)
1137 return;
1138
1139 host->mmc->actual_clock = 0;
1140
1141 if (host->ops->set_clock) {
1142 host->ops->set_clock(host, clock);
1143 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1144 return;
1145 }
1146
1147 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1148
1149 if (clock == 0)
1150 goto out;
1151
1152 if (host->version >= SDHCI_SPEC_300) {
1153 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1154 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1155 u16 pre_val;
1156
1157 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1158 pre_val = sdhci_get_preset_value(host);
1159 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1160 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1161 if (host->clk_mul &&
1162 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1163 clk = SDHCI_PROG_CLOCK_MODE;
1164 real_div = div + 1;
1165 clk_mul = host->clk_mul;
1166 } else {
1167 real_div = max_t(int, 1, div << 1);
1168 }
1169 goto clock_set;
1170 }
1171
1172 /*
1173 * Check if the Host Controller supports Programmable Clock
1174 * Mode.
1175 */
1176 if (host->clk_mul) {
1177 for (div = 1; div <= 1024; div++) {
1178 if ((host->max_clk * host->clk_mul / div)
1179 <= clock)
1180 break;
1181 }
1182 /*
1183 * Set Programmable Clock Mode in the Clock
1184 * Control register.
1185 */
1186 clk = SDHCI_PROG_CLOCK_MODE;
1187 real_div = div;
1188 clk_mul = host->clk_mul;
1189 div--;
1190 } else {
1191 /* Version 3.00 divisors must be a multiple of 2. */
1192 if (host->max_clk <= clock)
1193 div = 1;
1194 else {
1195 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1196 div += 2) {
1197 if ((host->max_clk / div) <= clock)
1198 break;
1199 }
1200 }
1201 real_div = div;
1202 div >>= 1;
1203 }
1204 } else {
1205 /* Version 2.00 divisors must be a power of 2. */
1206 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
1210 real_div = div;
1211 div >>= 1;
1212 }
1213
1214 clock_set:
1215 if (real_div)
1216 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1217
1218 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1219 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1220 << SDHCI_DIVIDER_HI_SHIFT;
1221 clk |= SDHCI_CLOCK_INT_EN;
1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1223
1224 /* Wait max 20 ms */
1225 timeout = 20;
1226 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1227 & SDHCI_CLOCK_INT_STABLE)) {
1228 if (timeout == 0) {
1229 pr_err("%s: Internal clock never "
1230 "stabilised.\n", mmc_hostname(host->mmc));
1231 sdhci_dumpregs(host);
1232 return;
1233 }
1234 timeout--;
1235 mdelay(1);
1236 }
1237
1238 clk |= SDHCI_CLOCK_CARD_EN;
1239 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1240
1241 out:
1242 host->clock = clock;
1243 }
1244
1245 static inline void sdhci_update_clock(struct sdhci_host *host)
1246 {
1247 unsigned int clock;
1248
1249 clock = host->clock;
1250 host->clock = 0;
1251 sdhci_set_clock(host, clock);
1252 }
1253
1254 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1255 {
1256 u8 pwr = 0;
1257
1258 if (power != (unsigned short)-1) {
1259 switch (1 << power) {
1260 case MMC_VDD_165_195:
1261 pwr = SDHCI_POWER_180;
1262 break;
1263 case MMC_VDD_29_30:
1264 case MMC_VDD_30_31:
1265 pwr = SDHCI_POWER_300;
1266 break;
1267 case MMC_VDD_32_33:
1268 case MMC_VDD_33_34:
1269 pwr = SDHCI_POWER_330;
1270 break;
1271 default:
1272 BUG();
1273 }
1274 }
1275
1276 if (host->pwr == pwr)
1277 return -1;
1278
1279 host->pwr = pwr;
1280
1281 if (pwr == 0) {
1282 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1283 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1284 sdhci_runtime_pm_bus_off(host);
1285 return 0;
1286 }
1287
1288 /*
1289 * Spec says that we should clear the power reg before setting
1290 * a new value. Some controllers don't seem to like this though.
1291 */
1292 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1293 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1294
1295 /*
1296 * At least the Marvell CaFe chip gets confused if we set the voltage
1297 * and set turn on power at the same time, so set the voltage first.
1298 */
1299 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1300 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1301
1302 pwr |= SDHCI_POWER_ON;
1303
1304 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1305
1306 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1307 sdhci_runtime_pm_bus_on(host);
1308
1309 /*
1310 * Some controllers need an extra 10ms delay of 10ms before they
1311 * can apply clock after applying power
1312 */
1313 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1314 mdelay(10);
1315
1316 return power;
1317 }
1318
1319 /*****************************************************************************\
1320 * *
1321 * MMC callbacks *
1322 * *
1323 \*****************************************************************************/
1324
1325 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1326 {
1327 struct sdhci_host *host;
1328 int present;
1329 unsigned long flags;
1330 u32 tuning_opcode;
1331
1332 host = mmc_priv(mmc);
1333
1334 sdhci_runtime_pm_get(host);
1335
1336 present = mmc_gpio_get_cd(host->mmc);
1337
1338 spin_lock_irqsave(&host->lock, flags);
1339
1340 WARN_ON(host->mrq != NULL);
1341
1342 #ifndef SDHCI_USE_LEDS_CLASS
1343 sdhci_activate_led(host);
1344 #endif
1345
1346 /*
1347 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1348 * requests if Auto-CMD12 is enabled.
1349 */
1350 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1351 if (mrq->stop) {
1352 mrq->data->stop = NULL;
1353 mrq->stop = NULL;
1354 }
1355 }
1356
1357 host->mrq = mrq;
1358
1359 /*
1360 * Firstly check card presence from cd-gpio. The return could
1361 * be one of the following possibilities:
1362 * negative: cd-gpio is not available
1363 * zero: cd-gpio is used, and card is removed
1364 * one: cd-gpio is used, and card is present
1365 */
1366 if (present < 0) {
1367 /* If polling, assume that the card is always present. */
1368 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1369 present = 1;
1370 else
1371 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1372 SDHCI_CARD_PRESENT;
1373 }
1374
1375 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1376 host->mrq->cmd->error = -ENOMEDIUM;
1377 tasklet_schedule(&host->finish_tasklet);
1378 } else {
1379 u32 present_state;
1380
1381 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1382 /*
1383 * Check if the re-tuning timer has already expired and there
1384 * is no on-going data transfer. If so, we need to execute
1385 * tuning procedure before sending command.
1386 */
1387 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1388 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1389 if (mmc->card) {
1390 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1391 tuning_opcode =
1392 mmc->card->type == MMC_TYPE_MMC ?
1393 MMC_SEND_TUNING_BLOCK_HS200 :
1394 MMC_SEND_TUNING_BLOCK;
1395 spin_unlock_irqrestore(&host->lock, flags);
1396 sdhci_execute_tuning(mmc, tuning_opcode);
1397 spin_lock_irqsave(&host->lock, flags);
1398
1399 /* Restore original mmc_request structure */
1400 host->mrq = mrq;
1401 }
1402 }
1403
1404 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1405 sdhci_send_command(host, mrq->sbc);
1406 else
1407 sdhci_send_command(host, mrq->cmd);
1408 }
1409
1410 mmiowb();
1411 spin_unlock_irqrestore(&host->lock, flags);
1412 }
1413
1414 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1415 {
1416 unsigned long flags;
1417 int vdd_bit = -1;
1418 u8 ctrl;
1419
1420 spin_lock_irqsave(&host->lock, flags);
1421
1422 if (host->flags & SDHCI_DEVICE_DEAD) {
1423 spin_unlock_irqrestore(&host->lock, flags);
1424 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1425 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1426 return;
1427 }
1428
1429 /*
1430 * Reset the chip on each power off.
1431 * Should clear out any weird states.
1432 */
1433 if (ios->power_mode == MMC_POWER_OFF) {
1434 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1435 sdhci_reinit(host);
1436 }
1437
1438 if (host->version >= SDHCI_SPEC_300 &&
1439 (ios->power_mode == MMC_POWER_UP))
1440 sdhci_enable_preset_value(host, false);
1441
1442 sdhci_set_clock(host, ios->clock);
1443
1444 if (ios->power_mode == MMC_POWER_OFF)
1445 vdd_bit = sdhci_set_power(host, -1);
1446 else
1447 vdd_bit = sdhci_set_power(host, ios->vdd);
1448
1449 if (host->vmmc && vdd_bit != -1) {
1450 spin_unlock_irqrestore(&host->lock, flags);
1451 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1452 spin_lock_irqsave(&host->lock, flags);
1453 }
1454
1455 if (host->ops->platform_send_init_74_clocks)
1456 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1457
1458 /*
1459 * If your platform has 8-bit width support but is not a v3 controller,
1460 * or if it requires special setup code, you should implement that in
1461 * platform_bus_width().
1462 */
1463 if (host->ops->platform_bus_width) {
1464 host->ops->platform_bus_width(host, ios->bus_width);
1465 } else {
1466 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1467 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1468 ctrl &= ~SDHCI_CTRL_4BITBUS;
1469 if (host->version >= SDHCI_SPEC_300)
1470 ctrl |= SDHCI_CTRL_8BITBUS;
1471 } else {
1472 if (host->version >= SDHCI_SPEC_300)
1473 ctrl &= ~SDHCI_CTRL_8BITBUS;
1474 if (ios->bus_width == MMC_BUS_WIDTH_4)
1475 ctrl |= SDHCI_CTRL_4BITBUS;
1476 else
1477 ctrl &= ~SDHCI_CTRL_4BITBUS;
1478 }
1479 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1480 }
1481
1482 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1483
1484 if ((ios->timing == MMC_TIMING_SD_HS ||
1485 ios->timing == MMC_TIMING_MMC_HS)
1486 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1487 ctrl |= SDHCI_CTRL_HISPD;
1488 else
1489 ctrl &= ~SDHCI_CTRL_HISPD;
1490
1491 if (host->version >= SDHCI_SPEC_300) {
1492 u16 clk, ctrl_2;
1493
1494 /* In case of UHS-I modes, set High Speed Enable */
1495 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1496 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1497 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1498 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1499 (ios->timing == MMC_TIMING_UHS_SDR25))
1500 ctrl |= SDHCI_CTRL_HISPD;
1501
1502 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1503 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1504 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1505 /*
1506 * We only need to set Driver Strength if the
1507 * preset value enable is not set.
1508 */
1509 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1510 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1512 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1513 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1514
1515 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1516 } else {
1517 /*
1518 * According to SDHC Spec v3.00, if the Preset Value
1519 * Enable in the Host Control 2 register is set, we
1520 * need to reset SD Clock Enable before changing High
1521 * Speed Enable to avoid generating clock gliches.
1522 */
1523
1524 /* Reset SD Clock Enable */
1525 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1526 clk &= ~SDHCI_CLOCK_CARD_EN;
1527 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1528
1529 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1530
1531 /* Re-enable SD Clock */
1532 sdhci_update_clock(host);
1533 }
1534
1535
1536 /* Reset SD Clock Enable */
1537 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1538 clk &= ~SDHCI_CLOCK_CARD_EN;
1539 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1540
1541 if (host->ops->set_uhs_signaling)
1542 host->ops->set_uhs_signaling(host, ios->timing);
1543 else {
1544 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1545 /* Select Bus Speed Mode for host */
1546 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1547 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1548 (ios->timing == MMC_TIMING_UHS_SDR104))
1549 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1550 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1551 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1552 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1553 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1554 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1555 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1556 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1557 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1558 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1559 }
1560
1561 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1562 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1563 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1564 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1565 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1566 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1567 u16 preset;
1568
1569 sdhci_enable_preset_value(host, true);
1570 preset = sdhci_get_preset_value(host);
1571 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1572 >> SDHCI_PRESET_DRV_SHIFT;
1573 }
1574
1575 /* Re-enable SD Clock */
1576 sdhci_update_clock(host);
1577 } else
1578 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1579
1580 /*
1581 * Some (ENE) controllers go apeshit on some ios operation,
1582 * signalling timeout and CRC errors even on CMD0. Resetting
1583 * it on each ios seems to solve the problem.
1584 */
1585 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1586 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1587
1588 mmiowb();
1589 spin_unlock_irqrestore(&host->lock, flags);
1590 }
1591
1592 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1593 {
1594 struct sdhci_host *host = mmc_priv(mmc);
1595
1596 sdhci_runtime_pm_get(host);
1597 sdhci_do_set_ios(host, ios);
1598 sdhci_runtime_pm_put(host);
1599 }
1600
1601 static int sdhci_do_get_cd(struct sdhci_host *host)
1602 {
1603 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1604
1605 if (host->flags & SDHCI_DEVICE_DEAD)
1606 return 0;
1607
1608 /* If polling/nonremovable, assume that the card is always present. */
1609 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1610 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1611 return 1;
1612
1613 /* Try slot gpio detect */
1614 if (!IS_ERR_VALUE(gpio_cd))
1615 return !!gpio_cd;
1616
1617 /* Host native card detect */
1618 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1619 }
1620
1621 static int sdhci_get_cd(struct mmc_host *mmc)
1622 {
1623 struct sdhci_host *host = mmc_priv(mmc);
1624 int ret;
1625
1626 sdhci_runtime_pm_get(host);
1627 ret = sdhci_do_get_cd(host);
1628 sdhci_runtime_pm_put(host);
1629 return ret;
1630 }
1631
1632 static int sdhci_check_ro(struct sdhci_host *host)
1633 {
1634 unsigned long flags;
1635 int is_readonly;
1636
1637 spin_lock_irqsave(&host->lock, flags);
1638
1639 if (host->flags & SDHCI_DEVICE_DEAD)
1640 is_readonly = 0;
1641 else if (host->ops->get_ro)
1642 is_readonly = host->ops->get_ro(host);
1643 else
1644 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1645 & SDHCI_WRITE_PROTECT);
1646
1647 spin_unlock_irqrestore(&host->lock, flags);
1648
1649 /* This quirk needs to be replaced by a callback-function later */
1650 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1651 !is_readonly : is_readonly;
1652 }
1653
1654 #define SAMPLE_COUNT 5
1655
1656 static int sdhci_do_get_ro(struct sdhci_host *host)
1657 {
1658 int i, ro_count;
1659
1660 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1661 return sdhci_check_ro(host);
1662
1663 ro_count = 0;
1664 for (i = 0; i < SAMPLE_COUNT; i++) {
1665 if (sdhci_check_ro(host)) {
1666 if (++ro_count > SAMPLE_COUNT / 2)
1667 return 1;
1668 }
1669 msleep(30);
1670 }
1671 return 0;
1672 }
1673
1674 static void sdhci_hw_reset(struct mmc_host *mmc)
1675 {
1676 struct sdhci_host *host = mmc_priv(mmc);
1677
1678 if (host->ops && host->ops->hw_reset)
1679 host->ops->hw_reset(host);
1680 }
1681
1682 static int sdhci_get_ro(struct mmc_host *mmc)
1683 {
1684 struct sdhci_host *host = mmc_priv(mmc);
1685 int ret;
1686
1687 sdhci_runtime_pm_get(host);
1688 ret = sdhci_do_get_ro(host);
1689 sdhci_runtime_pm_put(host);
1690 return ret;
1691 }
1692
1693 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1694 {
1695 if (host->flags & SDHCI_DEVICE_DEAD)
1696 goto out;
1697
1698 if (enable)
1699 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1700 else
1701 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1702
1703 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1704 if (host->runtime_suspended)
1705 goto out;
1706
1707 if (enable)
1708 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1709 else
1710 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1711 out:
1712 mmiowb();
1713 }
1714
1715 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1716 {
1717 struct sdhci_host *host = mmc_priv(mmc);
1718 unsigned long flags;
1719
1720 spin_lock_irqsave(&host->lock, flags);
1721 sdhci_enable_sdio_irq_nolock(host, enable);
1722 spin_unlock_irqrestore(&host->lock, flags);
1723 }
1724
1725 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1726 struct mmc_ios *ios)
1727 {
1728 u16 ctrl;
1729 int ret;
1730
1731 /*
1732 * Signal Voltage Switching is only applicable for Host Controllers
1733 * v3.00 and above.
1734 */
1735 if (host->version < SDHCI_SPEC_300)
1736 return 0;
1737
1738 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1739
1740 switch (ios->signal_voltage) {
1741 case MMC_SIGNAL_VOLTAGE_330:
1742 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1743 ctrl &= ~SDHCI_CTRL_VDD_180;
1744 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1745
1746 if (host->vqmmc) {
1747 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1748 if (ret) {
1749 pr_warning("%s: Switching to 3.3V signalling voltage "
1750 " failed\n", mmc_hostname(host->mmc));
1751 return -EIO;
1752 }
1753 }
1754 /* Wait for 5ms */
1755 usleep_range(5000, 5500);
1756
1757 /* 3.3V regulator output should be stable within 5 ms */
1758 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1759 if (!(ctrl & SDHCI_CTRL_VDD_180))
1760 return 0;
1761
1762 pr_warning("%s: 3.3V regulator output did not became stable\n",
1763 mmc_hostname(host->mmc));
1764
1765 return -EAGAIN;
1766 case MMC_SIGNAL_VOLTAGE_180:
1767 if (host->vqmmc) {
1768 ret = regulator_set_voltage(host->vqmmc,
1769 1700000, 1950000);
1770 if (ret) {
1771 pr_warning("%s: Switching to 1.8V signalling voltage "
1772 " failed\n", mmc_hostname(host->mmc));
1773 return -EIO;
1774 }
1775 }
1776
1777 /*
1778 * Enable 1.8V Signal Enable in the Host Control2
1779 * register
1780 */
1781 ctrl |= SDHCI_CTRL_VDD_180;
1782 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1783
1784 /* Wait for 5ms */
1785 usleep_range(5000, 5500);
1786
1787 /* 1.8V regulator output should be stable within 5 ms */
1788 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1789 if (ctrl & SDHCI_CTRL_VDD_180)
1790 return 0;
1791
1792 pr_warning("%s: 1.8V regulator output did not became stable\n",
1793 mmc_hostname(host->mmc));
1794
1795 return -EAGAIN;
1796 case MMC_SIGNAL_VOLTAGE_120:
1797 if (host->vqmmc) {
1798 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1799 if (ret) {
1800 pr_warning("%s: Switching to 1.2V signalling voltage "
1801 " failed\n", mmc_hostname(host->mmc));
1802 return -EIO;
1803 }
1804 }
1805 return 0;
1806 default:
1807 /* No signal voltage switch required */
1808 return 0;
1809 }
1810 }
1811
1812 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1813 struct mmc_ios *ios)
1814 {
1815 struct sdhci_host *host = mmc_priv(mmc);
1816 int err;
1817
1818 if (host->version < SDHCI_SPEC_300)
1819 return 0;
1820 sdhci_runtime_pm_get(host);
1821 err = sdhci_do_start_signal_voltage_switch(host, ios);
1822 sdhci_runtime_pm_put(host);
1823 return err;
1824 }
1825
1826 static int sdhci_card_busy(struct mmc_host *mmc)
1827 {
1828 struct sdhci_host *host = mmc_priv(mmc);
1829 u32 present_state;
1830
1831 sdhci_runtime_pm_get(host);
1832 /* Check whether DAT[3:0] is 0000 */
1833 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1834 sdhci_runtime_pm_put(host);
1835
1836 return !(present_state & SDHCI_DATA_LVL_MASK);
1837 }
1838
1839 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1840 {
1841 struct sdhci_host *host;
1842 u16 ctrl;
1843 u32 ier;
1844 int tuning_loop_counter = MAX_TUNING_LOOP;
1845 unsigned long timeout;
1846 int err = 0;
1847 bool requires_tuning_nonuhs = false;
1848
1849 host = mmc_priv(mmc);
1850
1851 sdhci_runtime_pm_get(host);
1852 disable_irq(host->irq);
1853 spin_lock(&host->lock);
1854
1855 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1856
1857 /*
1858 * The Host Controller needs tuning only in case of SDR104 mode
1859 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1860 * Capabilities register.
1861 * If the Host Controller supports the HS200 mode then the
1862 * tuning function has to be executed.
1863 */
1864 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1865 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1866 host->flags & SDHCI_SDR104_NEEDS_TUNING))
1867 requires_tuning_nonuhs = true;
1868
1869 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1870 requires_tuning_nonuhs)
1871 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1872 else {
1873 spin_unlock(&host->lock);
1874 enable_irq(host->irq);
1875 sdhci_runtime_pm_put(host);
1876 return 0;
1877 }
1878
1879 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1880
1881 /*
1882 * As per the Host Controller spec v3.00, tuning command
1883 * generates Buffer Read Ready interrupt, so enable that.
1884 *
1885 * Note: The spec clearly says that when tuning sequence
1886 * is being performed, the controller does not generate
1887 * interrupts other than Buffer Read Ready interrupt. But
1888 * to make sure we don't hit a controller bug, we _only_
1889 * enable Buffer Read Ready interrupt here.
1890 */
1891 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1892 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1893
1894 /*
1895 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1896 * of loops reaches 40 times or a timeout of 150ms occurs.
1897 */
1898 timeout = 150;
1899 do {
1900 struct mmc_command cmd = {0};
1901 struct mmc_request mrq = {NULL};
1902
1903 if (!tuning_loop_counter && !timeout)
1904 break;
1905
1906 cmd.opcode = opcode;
1907 cmd.arg = 0;
1908 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1909 cmd.retries = 0;
1910 cmd.data = NULL;
1911 cmd.error = 0;
1912
1913 mrq.cmd = &cmd;
1914 host->mrq = &mrq;
1915
1916 /*
1917 * In response to CMD19, the card sends 64 bytes of tuning
1918 * block to the Host Controller. So we set the block size
1919 * to 64 here.
1920 */
1921 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1922 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1923 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1924 SDHCI_BLOCK_SIZE);
1925 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1926 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1927 SDHCI_BLOCK_SIZE);
1928 } else {
1929 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1930 SDHCI_BLOCK_SIZE);
1931 }
1932
1933 /*
1934 * The tuning block is sent by the card to the host controller.
1935 * So we set the TRNS_READ bit in the Transfer Mode register.
1936 * This also takes care of setting DMA Enable and Multi Block
1937 * Select in the same register to 0.
1938 */
1939 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1940
1941 sdhci_send_command(host, &cmd);
1942
1943 host->cmd = NULL;
1944 host->mrq = NULL;
1945
1946 spin_unlock(&host->lock);
1947 enable_irq(host->irq);
1948
1949 /* Wait for Buffer Read Ready interrupt */
1950 wait_event_interruptible_timeout(host->buf_ready_int,
1951 (host->tuning_done == 1),
1952 msecs_to_jiffies(50));
1953 disable_irq(host->irq);
1954 spin_lock(&host->lock);
1955
1956 if (!host->tuning_done) {
1957 pr_info(DRIVER_NAME ": Timeout waiting for "
1958 "Buffer Read Ready interrupt during tuning "
1959 "procedure, falling back to fixed sampling "
1960 "clock\n");
1961 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1962 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1963 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1964 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1965
1966 err = -EIO;
1967 goto out;
1968 }
1969
1970 host->tuning_done = 0;
1971
1972 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1973 tuning_loop_counter--;
1974 timeout--;
1975 mdelay(1);
1976 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1977
1978 /*
1979 * The Host Driver has exhausted the maximum number of loops allowed,
1980 * so use fixed sampling frequency.
1981 */
1982 if (!tuning_loop_counter || !timeout) {
1983 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1984 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1985 } else {
1986 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1987 pr_info(DRIVER_NAME ": Tuning procedure"
1988 " failed, falling back to fixed sampling"
1989 " clock\n");
1990 err = -EIO;
1991 }
1992 }
1993
1994 out:
1995 /*
1996 * If this is the very first time we are here, we start the retuning
1997 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1998 * flag won't be set, we check this condition before actually starting
1999 * the timer.
2000 */
2001 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2002 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2003 host->flags |= SDHCI_USING_RETUNING_TIMER;
2004 mod_timer(&host->tuning_timer, jiffies +
2005 host->tuning_count * HZ);
2006 /* Tuning mode 1 limits the maximum data length to 4MB */
2007 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2008 } else {
2009 host->flags &= ~SDHCI_NEEDS_RETUNING;
2010 /* Reload the new initial value for timer */
2011 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2012 mod_timer(&host->tuning_timer, jiffies +
2013 host->tuning_count * HZ);
2014 }
2015
2016 /*
2017 * In case tuning fails, host controllers which support re-tuning can
2018 * try tuning again at a later time, when the re-tuning timer expires.
2019 * So for these controllers, we return 0. Since there might be other
2020 * controllers who do not have this capability, we return error for
2021 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2022 * a retuning timer to do the retuning for the card.
2023 */
2024 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2025 err = 0;
2026
2027 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2028 spin_unlock(&host->lock);
2029 enable_irq(host->irq);
2030 sdhci_runtime_pm_put(host);
2031
2032 return err;
2033 }
2034
2035
2036 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2037 {
2038 u16 ctrl;
2039
2040 /* Host Controller v3.00 defines preset value registers */
2041 if (host->version < SDHCI_SPEC_300)
2042 return;
2043
2044 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2045
2046 /*
2047 * We only enable or disable Preset Value if they are not already
2048 * enabled or disabled respectively. Otherwise, we bail out.
2049 */
2050 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2051 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2052 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2053 host->flags |= SDHCI_PV_ENABLED;
2054 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2055 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2056 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2057 host->flags &= ~SDHCI_PV_ENABLED;
2058 }
2059 }
2060
2061 static void sdhci_card_event(struct mmc_host *mmc)
2062 {
2063 struct sdhci_host *host = mmc_priv(mmc);
2064 unsigned long flags;
2065 int present;
2066
2067 /* First check if client has provided their own card event */
2068 if (host->ops->card_event)
2069 host->ops->card_event(host);
2070
2071 present = sdhci_do_get_cd(host);
2072
2073 spin_lock_irqsave(&host->lock, flags);
2074
2075 /* Check host->mrq first in case we are runtime suspended */
2076 if (host->mrq && !present) {
2077 pr_err("%s: Card removed during transfer!\n",
2078 mmc_hostname(host->mmc));
2079 pr_err("%s: Resetting controller.\n",
2080 mmc_hostname(host->mmc));
2081
2082 sdhci_reset(host, SDHCI_RESET_CMD);
2083 sdhci_reset(host, SDHCI_RESET_DATA);
2084
2085 host->mrq->cmd->error = -ENOMEDIUM;
2086 tasklet_schedule(&host->finish_tasklet);
2087 }
2088
2089 spin_unlock_irqrestore(&host->lock, flags);
2090 }
2091
2092 static const struct mmc_host_ops sdhci_ops = {
2093 .request = sdhci_request,
2094 .set_ios = sdhci_set_ios,
2095 .get_cd = sdhci_get_cd,
2096 .get_ro = sdhci_get_ro,
2097 .hw_reset = sdhci_hw_reset,
2098 .enable_sdio_irq = sdhci_enable_sdio_irq,
2099 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2100 .execute_tuning = sdhci_execute_tuning,
2101 .card_event = sdhci_card_event,
2102 .card_busy = sdhci_card_busy,
2103 };
2104
2105 /*****************************************************************************\
2106 * *
2107 * Tasklets *
2108 * *
2109 \*****************************************************************************/
2110
2111 static void sdhci_tasklet_card(unsigned long param)
2112 {
2113 struct sdhci_host *host = (struct sdhci_host*)param;
2114
2115 sdhci_card_event(host->mmc);
2116
2117 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2118 }
2119
2120 static void sdhci_tasklet_finish(unsigned long param)
2121 {
2122 struct sdhci_host *host;
2123 unsigned long flags;
2124 struct mmc_request *mrq;
2125
2126 host = (struct sdhci_host*)param;
2127
2128 spin_lock_irqsave(&host->lock, flags);
2129
2130 /*
2131 * If this tasklet gets rescheduled while running, it will
2132 * be run again afterwards but without any active request.
2133 */
2134 if (!host->mrq) {
2135 spin_unlock_irqrestore(&host->lock, flags);
2136 return;
2137 }
2138
2139 del_timer(&host->timer);
2140
2141 mrq = host->mrq;
2142
2143 /*
2144 * The controller needs a reset of internal state machines
2145 * upon error conditions.
2146 */
2147 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2148 ((mrq->cmd && mrq->cmd->error) ||
2149 (mrq->data && (mrq->data->error ||
2150 (mrq->data->stop && mrq->data->stop->error))) ||
2151 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2152
2153 /* Some controllers need this kick or reset won't work here */
2154 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2155 /* This is to force an update */
2156 sdhci_update_clock(host);
2157
2158 /* Spec says we should do both at the same time, but Ricoh
2159 controllers do not like that. */
2160 sdhci_reset(host, SDHCI_RESET_CMD);
2161 sdhci_reset(host, SDHCI_RESET_DATA);
2162 }
2163
2164 host->mrq = NULL;
2165 host->cmd = NULL;
2166 host->data = NULL;
2167
2168 #ifndef SDHCI_USE_LEDS_CLASS
2169 sdhci_deactivate_led(host);
2170 #endif
2171
2172 mmiowb();
2173 spin_unlock_irqrestore(&host->lock, flags);
2174
2175 mmc_request_done(host->mmc, mrq);
2176 sdhci_runtime_pm_put(host);
2177 }
2178
2179 static void sdhci_timeout_timer(unsigned long data)
2180 {
2181 struct sdhci_host *host;
2182 unsigned long flags;
2183
2184 host = (struct sdhci_host*)data;
2185
2186 spin_lock_irqsave(&host->lock, flags);
2187
2188 if (host->mrq) {
2189 pr_err("%s: Timeout waiting for hardware "
2190 "interrupt.\n", mmc_hostname(host->mmc));
2191 sdhci_dumpregs(host);
2192
2193 if (host->data) {
2194 host->data->error = -ETIMEDOUT;
2195 sdhci_finish_data(host);
2196 } else {
2197 if (host->cmd)
2198 host->cmd->error = -ETIMEDOUT;
2199 else
2200 host->mrq->cmd->error = -ETIMEDOUT;
2201
2202 tasklet_schedule(&host->finish_tasklet);
2203 }
2204 }
2205
2206 mmiowb();
2207 spin_unlock_irqrestore(&host->lock, flags);
2208 }
2209
2210 static void sdhci_tuning_timer(unsigned long data)
2211 {
2212 struct sdhci_host *host;
2213 unsigned long flags;
2214
2215 host = (struct sdhci_host *)data;
2216
2217 spin_lock_irqsave(&host->lock, flags);
2218
2219 host->flags |= SDHCI_NEEDS_RETUNING;
2220
2221 spin_unlock_irqrestore(&host->lock, flags);
2222 }
2223
2224 /*****************************************************************************\
2225 * *
2226 * Interrupt handling *
2227 * *
2228 \*****************************************************************************/
2229
2230 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2231 {
2232 BUG_ON(intmask == 0);
2233
2234 if (!host->cmd) {
2235 pr_err("%s: Got command interrupt 0x%08x even "
2236 "though no command operation was in progress.\n",
2237 mmc_hostname(host->mmc), (unsigned)intmask);
2238 sdhci_dumpregs(host);
2239 return;
2240 }
2241
2242 if (intmask & SDHCI_INT_TIMEOUT)
2243 host->cmd->error = -ETIMEDOUT;
2244 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2245 SDHCI_INT_INDEX))
2246 host->cmd->error = -EILSEQ;
2247
2248 if (host->cmd->error) {
2249 tasklet_schedule(&host->finish_tasklet);
2250 return;
2251 }
2252
2253 /*
2254 * The host can send and interrupt when the busy state has
2255 * ended, allowing us to wait without wasting CPU cycles.
2256 * Unfortunately this is overloaded on the "data complete"
2257 * interrupt, so we need to take some care when handling
2258 * it.
2259 *
2260 * Note: The 1.0 specification is a bit ambiguous about this
2261 * feature so there might be some problems with older
2262 * controllers.
2263 */
2264 if (host->cmd->flags & MMC_RSP_BUSY) {
2265 if (host->cmd->data)
2266 DBG("Cannot wait for busy signal when also "
2267 "doing a data transfer");
2268 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2269 return;
2270
2271 /* The controller does not support the end-of-busy IRQ,
2272 * fall through and take the SDHCI_INT_RESPONSE */
2273 }
2274
2275 if (intmask & SDHCI_INT_RESPONSE)
2276 sdhci_finish_command(host);
2277 }
2278
2279 #ifdef CONFIG_MMC_DEBUG
2280 static void sdhci_show_adma_error(struct sdhci_host *host)
2281 {
2282 const char *name = mmc_hostname(host->mmc);
2283 u8 *desc = host->adma_desc;
2284 __le32 *dma;
2285 __le16 *len;
2286 u8 attr;
2287
2288 sdhci_dumpregs(host);
2289
2290 while (true) {
2291 dma = (__le32 *)(desc + 4);
2292 len = (__le16 *)(desc + 2);
2293 attr = *desc;
2294
2295 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2296 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2297
2298 desc += 8;
2299
2300 if (attr & 2)
2301 break;
2302 }
2303 }
2304 #else
2305 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2306 #endif
2307
2308 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2309 {
2310 u32 command;
2311 BUG_ON(intmask == 0);
2312
2313 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2314 if (intmask & SDHCI_INT_DATA_AVAIL) {
2315 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2316 if (command == MMC_SEND_TUNING_BLOCK ||
2317 command == MMC_SEND_TUNING_BLOCK_HS200) {
2318 host->tuning_done = 1;
2319 wake_up(&host->buf_ready_int);
2320 return;
2321 }
2322 }
2323
2324 if (!host->data) {
2325 /*
2326 * The "data complete" interrupt is also used to
2327 * indicate that a busy state has ended. See comment
2328 * above in sdhci_cmd_irq().
2329 */
2330 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2331 if (intmask & SDHCI_INT_DATA_END) {
2332 sdhci_finish_command(host);
2333 return;
2334 }
2335 }
2336
2337 pr_err("%s: Got data interrupt 0x%08x even "
2338 "though no data operation was in progress.\n",
2339 mmc_hostname(host->mmc), (unsigned)intmask);
2340 sdhci_dumpregs(host);
2341
2342 return;
2343 }
2344
2345 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2346 host->data->error = -ETIMEDOUT;
2347 else if (intmask & SDHCI_INT_DATA_END_BIT)
2348 host->data->error = -EILSEQ;
2349 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2350 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2351 != MMC_BUS_TEST_R)
2352 host->data->error = -EILSEQ;
2353 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2354 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2355 sdhci_show_adma_error(host);
2356 host->data->error = -EIO;
2357 if (host->ops->adma_workaround)
2358 host->ops->adma_workaround(host, intmask);
2359 }
2360
2361 if (host->data->error)
2362 sdhci_finish_data(host);
2363 else {
2364 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2365 sdhci_transfer_pio(host);
2366
2367 /*
2368 * We currently don't do anything fancy with DMA
2369 * boundaries, but as we can't disable the feature
2370 * we need to at least restart the transfer.
2371 *
2372 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2373 * should return a valid address to continue from, but as
2374 * some controllers are faulty, don't trust them.
2375 */
2376 if (intmask & SDHCI_INT_DMA_END) {
2377 u32 dmastart, dmanow;
2378 dmastart = sg_dma_address(host->data->sg);
2379 dmanow = dmastart + host->data->bytes_xfered;
2380 /*
2381 * Force update to the next DMA block boundary.
2382 */
2383 dmanow = (dmanow &
2384 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2385 SDHCI_DEFAULT_BOUNDARY_SIZE;
2386 host->data->bytes_xfered = dmanow - dmastart;
2387 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2388 " next 0x%08x\n",
2389 mmc_hostname(host->mmc), dmastart,
2390 host->data->bytes_xfered, dmanow);
2391 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2392 }
2393
2394 if (intmask & SDHCI_INT_DATA_END) {
2395 if (host->cmd) {
2396 /*
2397 * Data managed to finish before the
2398 * command completed. Make sure we do
2399 * things in the proper order.
2400 */
2401 host->data_early = 1;
2402 } else {
2403 sdhci_finish_data(host);
2404 }
2405 }
2406 }
2407 }
2408
2409 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2410 {
2411 irqreturn_t result;
2412 struct sdhci_host *host = dev_id;
2413 u32 intmask, unexpected = 0;
2414 int cardint = 0, max_loops = 16;
2415
2416 spin_lock(&host->lock);
2417
2418 if (host->runtime_suspended) {
2419 spin_unlock(&host->lock);
2420 return IRQ_NONE;
2421 }
2422
2423 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2424
2425 if (!intmask || intmask == 0xffffffff) {
2426 result = IRQ_NONE;
2427 goto out;
2428 }
2429
2430 again:
2431 DBG("*** %s got interrupt: 0x%08x\n",
2432 mmc_hostname(host->mmc), intmask);
2433
2434 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2435 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2436 SDHCI_CARD_PRESENT;
2437
2438 /*
2439 * There is a observation on i.mx esdhc. INSERT bit will be
2440 * immediately set again when it gets cleared, if a card is
2441 * inserted. We have to mask the irq to prevent interrupt
2442 * storm which will freeze the system. And the REMOVE gets
2443 * the same situation.
2444 *
2445 * More testing are needed here to ensure it works for other
2446 * platforms though.
2447 */
2448 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2449 SDHCI_INT_CARD_REMOVE);
2450 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2451 SDHCI_INT_CARD_INSERT);
2452
2453 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2454 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2455 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2456 tasklet_schedule(&host->card_tasklet);
2457 }
2458
2459 if (intmask & SDHCI_INT_CMD_MASK) {
2460 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2461 SDHCI_INT_STATUS);
2462 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2463 }
2464
2465 if (intmask & SDHCI_INT_DATA_MASK) {
2466 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2467 SDHCI_INT_STATUS);
2468 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2469 }
2470
2471 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2472
2473 intmask &= ~SDHCI_INT_ERROR;
2474
2475 if (intmask & SDHCI_INT_BUS_POWER) {
2476 pr_err("%s: Card is consuming too much power!\n",
2477 mmc_hostname(host->mmc));
2478 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2479 }
2480
2481 intmask &= ~SDHCI_INT_BUS_POWER;
2482
2483 if (intmask & SDHCI_INT_CARD_INT)
2484 cardint = 1;
2485
2486 intmask &= ~SDHCI_INT_CARD_INT;
2487
2488 if (intmask) {
2489 unexpected |= intmask;
2490 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2491 }
2492
2493 result = IRQ_HANDLED;
2494
2495 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2496 if (intmask && --max_loops)
2497 goto again;
2498 out:
2499 spin_unlock(&host->lock);
2500
2501 if (unexpected) {
2502 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2503 mmc_hostname(host->mmc), unexpected);
2504 sdhci_dumpregs(host);
2505 }
2506 /*
2507 * We have to delay this as it calls back into the driver.
2508 */
2509 if (cardint && host->mmc->sdio_irqs)
2510 mmc_signal_sdio_irq(host->mmc);
2511
2512 return result;
2513 }
2514
2515 /*****************************************************************************\
2516 * *
2517 * Suspend/resume *
2518 * *
2519 \*****************************************************************************/
2520
2521 #ifdef CONFIG_PM
2522 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2523 {
2524 u8 val;
2525 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2526 | SDHCI_WAKE_ON_INT;
2527
2528 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2529 val |= mask ;
2530 /* Avoid fake wake up */
2531 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2532 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2533 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2534 }
2535 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2536
2537 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2538 {
2539 u8 val;
2540 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2541 | SDHCI_WAKE_ON_INT;
2542
2543 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2544 val &= ~mask;
2545 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2546 }
2547 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2548
2549 int sdhci_suspend_host(struct sdhci_host *host)
2550 {
2551 int ret;
2552
2553 if (host->ops->platform_suspend)
2554 host->ops->platform_suspend(host);
2555
2556 sdhci_disable_card_detection(host);
2557
2558 /* Disable tuning since we are suspending */
2559 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2560 del_timer_sync(&host->tuning_timer);
2561 host->flags &= ~SDHCI_NEEDS_RETUNING;
2562 }
2563
2564 ret = mmc_suspend_host(host->mmc);
2565 if (ret) {
2566 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2567 host->flags |= SDHCI_NEEDS_RETUNING;
2568 mod_timer(&host->tuning_timer, jiffies +
2569 host->tuning_count * HZ);
2570 }
2571
2572 sdhci_enable_card_detection(host);
2573
2574 return ret;
2575 }
2576
2577 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2578 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2579 free_irq(host->irq, host);
2580 } else {
2581 sdhci_enable_irq_wakeups(host);
2582 enable_irq_wake(host->irq);
2583 }
2584 return ret;
2585 }
2586
2587 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2588
2589 int sdhci_resume_host(struct sdhci_host *host)
2590 {
2591 int ret;
2592
2593 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2594 if (host->ops->enable_dma)
2595 host->ops->enable_dma(host);
2596 }
2597
2598 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2599 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2600 mmc_hostname(host->mmc), host);
2601 if (ret)
2602 return ret;
2603 } else {
2604 sdhci_disable_irq_wakeups(host);
2605 disable_irq_wake(host->irq);
2606 }
2607
2608 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2609 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2610 /* Card keeps power but host controller does not */
2611 sdhci_init(host, 0);
2612 host->pwr = 0;
2613 host->clock = 0;
2614 sdhci_do_set_ios(host, &host->mmc->ios);
2615 } else {
2616 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2617 mmiowb();
2618 }
2619
2620 ret = mmc_resume_host(host->mmc);
2621 sdhci_enable_card_detection(host);
2622
2623 if (host->ops->platform_resume)
2624 host->ops->platform_resume(host);
2625
2626 /* Set the re-tuning expiration flag */
2627 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2628 host->flags |= SDHCI_NEEDS_RETUNING;
2629
2630 return ret;
2631 }
2632
2633 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2634 #endif /* CONFIG_PM */
2635
2636 #ifdef CONFIG_PM_RUNTIME
2637
2638 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2639 {
2640 return pm_runtime_get_sync(host->mmc->parent);
2641 }
2642
2643 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2644 {
2645 pm_runtime_mark_last_busy(host->mmc->parent);
2646 return pm_runtime_put_autosuspend(host->mmc->parent);
2647 }
2648
2649 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2650 {
2651 if (host->bus_on)
2652 return;
2653 host->bus_on = true;
2654 pm_runtime_get_noresume(host->mmc->parent);
2655 }
2656
2657 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2658 {
2659 if (!host->bus_on)
2660 return;
2661 host->bus_on = false;
2662 pm_runtime_put_noidle(host->mmc->parent);
2663 }
2664
2665 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2666 {
2667 unsigned long flags;
2668 int ret = 0;
2669
2670 /* Disable tuning since we are suspending */
2671 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2672 del_timer_sync(&host->tuning_timer);
2673 host->flags &= ~SDHCI_NEEDS_RETUNING;
2674 }
2675
2676 spin_lock_irqsave(&host->lock, flags);
2677 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2678 spin_unlock_irqrestore(&host->lock, flags);
2679
2680 synchronize_irq(host->irq);
2681
2682 spin_lock_irqsave(&host->lock, flags);
2683 host->runtime_suspended = true;
2684 spin_unlock_irqrestore(&host->lock, flags);
2685
2686 return ret;
2687 }
2688 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2689
2690 int sdhci_runtime_resume_host(struct sdhci_host *host)
2691 {
2692 unsigned long flags;
2693 int ret = 0, host_flags = host->flags;
2694
2695 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2696 if (host->ops->enable_dma)
2697 host->ops->enable_dma(host);
2698 }
2699
2700 sdhci_init(host, 0);
2701
2702 /* Force clock and power re-program */
2703 host->pwr = 0;
2704 host->clock = 0;
2705 sdhci_do_set_ios(host, &host->mmc->ios);
2706
2707 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2708 if ((host_flags & SDHCI_PV_ENABLED) &&
2709 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2710 spin_lock_irqsave(&host->lock, flags);
2711 sdhci_enable_preset_value(host, true);
2712 spin_unlock_irqrestore(&host->lock, flags);
2713 }
2714
2715 /* Set the re-tuning expiration flag */
2716 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2717 host->flags |= SDHCI_NEEDS_RETUNING;
2718
2719 spin_lock_irqsave(&host->lock, flags);
2720
2721 host->runtime_suspended = false;
2722
2723 /* Enable SDIO IRQ */
2724 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2725 sdhci_enable_sdio_irq_nolock(host, true);
2726
2727 /* Enable Card Detection */
2728 sdhci_enable_card_detection(host);
2729
2730 spin_unlock_irqrestore(&host->lock, flags);
2731
2732 return ret;
2733 }
2734 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2735
2736 #endif
2737
2738 /*****************************************************************************\
2739 * *
2740 * Device allocation/registration *
2741 * *
2742 \*****************************************************************************/
2743
2744 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2745 size_t priv_size)
2746 {
2747 struct mmc_host *mmc;
2748 struct sdhci_host *host;
2749
2750 WARN_ON(dev == NULL);
2751
2752 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2753 if (!mmc)
2754 return ERR_PTR(-ENOMEM);
2755
2756 host = mmc_priv(mmc);
2757 host->mmc = mmc;
2758
2759 return host;
2760 }
2761
2762 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2763
2764 int sdhci_add_host(struct sdhci_host *host)
2765 {
2766 struct mmc_host *mmc;
2767 u32 caps[2] = {0, 0};
2768 u32 max_current_caps;
2769 unsigned int ocr_avail;
2770 int ret;
2771
2772 WARN_ON(host == NULL);
2773 if (host == NULL)
2774 return -EINVAL;
2775
2776 mmc = host->mmc;
2777
2778 if (debug_quirks)
2779 host->quirks = debug_quirks;
2780 if (debug_quirks2)
2781 host->quirks2 = debug_quirks2;
2782
2783 sdhci_reset(host, SDHCI_RESET_ALL);
2784
2785 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2786 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2787 >> SDHCI_SPEC_VER_SHIFT;
2788 if (host->version > SDHCI_SPEC_300) {
2789 pr_err("%s: Unknown controller version (%d). "
2790 "You may experience problems.\n", mmc_hostname(mmc),
2791 host->version);
2792 }
2793
2794 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2795 sdhci_readl(host, SDHCI_CAPABILITIES);
2796
2797 if (host->version >= SDHCI_SPEC_300)
2798 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2799 host->caps1 :
2800 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2801
2802 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2803 host->flags |= SDHCI_USE_SDMA;
2804 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2805 DBG("Controller doesn't have SDMA capability\n");
2806 else
2807 host->flags |= SDHCI_USE_SDMA;
2808
2809 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2810 (host->flags & SDHCI_USE_SDMA)) {
2811 DBG("Disabling DMA as it is marked broken\n");
2812 host->flags &= ~SDHCI_USE_SDMA;
2813 }
2814
2815 if ((host->version >= SDHCI_SPEC_200) &&
2816 (caps[0] & SDHCI_CAN_DO_ADMA2))
2817 host->flags |= SDHCI_USE_ADMA;
2818
2819 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2820 (host->flags & SDHCI_USE_ADMA)) {
2821 DBG("Disabling ADMA as it is marked broken\n");
2822 host->flags &= ~SDHCI_USE_ADMA;
2823 }
2824
2825 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2826 if (host->ops->enable_dma) {
2827 if (host->ops->enable_dma(host)) {
2828 pr_warning("%s: No suitable DMA "
2829 "available. Falling back to PIO.\n",
2830 mmc_hostname(mmc));
2831 host->flags &=
2832 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2833 }
2834 }
2835 }
2836
2837 if (host->flags & SDHCI_USE_ADMA) {
2838 /*
2839 * We need to allocate descriptors for all sg entries
2840 * (128) and potentially one alignment transfer for
2841 * each of those entries.
2842 */
2843 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2844 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2845 if (!host->adma_desc || !host->align_buffer) {
2846 kfree(host->adma_desc);
2847 kfree(host->align_buffer);
2848 pr_warning("%s: Unable to allocate ADMA "
2849 "buffers. Falling back to standard DMA.\n",
2850 mmc_hostname(mmc));
2851 host->flags &= ~SDHCI_USE_ADMA;
2852 }
2853 }
2854
2855 /*
2856 * If we use DMA, then it's up to the caller to set the DMA
2857 * mask, but PIO does not need the hw shim so we set a new
2858 * mask here in that case.
2859 */
2860 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2861 host->dma_mask = DMA_BIT_MASK(64);
2862 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2863 }
2864
2865 if (host->version >= SDHCI_SPEC_300)
2866 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2867 >> SDHCI_CLOCK_BASE_SHIFT;
2868 else
2869 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2870 >> SDHCI_CLOCK_BASE_SHIFT;
2871
2872 host->max_clk *= 1000000;
2873 if (host->max_clk == 0 || host->quirks &
2874 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2875 if (!host->ops->get_max_clock) {
2876 pr_err("%s: Hardware doesn't specify base clock "
2877 "frequency.\n", mmc_hostname(mmc));
2878 return -ENODEV;
2879 }
2880 host->max_clk = host->ops->get_max_clock(host);
2881 }
2882
2883 /*
2884 * In case of Host Controller v3.00, find out whether clock
2885 * multiplier is supported.
2886 */
2887 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2888 SDHCI_CLOCK_MUL_SHIFT;
2889
2890 /*
2891 * In case the value in Clock Multiplier is 0, then programmable
2892 * clock mode is not supported, otherwise the actual clock
2893 * multiplier is one more than the value of Clock Multiplier
2894 * in the Capabilities Register.
2895 */
2896 if (host->clk_mul)
2897 host->clk_mul += 1;
2898
2899 /*
2900 * Set host parameters.
2901 */
2902 mmc->ops = &sdhci_ops;
2903 mmc->f_max = host->max_clk;
2904 if (host->ops->get_min_clock)
2905 mmc->f_min = host->ops->get_min_clock(host);
2906 else if (host->version >= SDHCI_SPEC_300) {
2907 if (host->clk_mul) {
2908 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2909 mmc->f_max = host->max_clk * host->clk_mul;
2910 } else
2911 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2912 } else
2913 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2914
2915 host->timeout_clk =
2916 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2917 if (host->timeout_clk == 0) {
2918 if (host->ops->get_timeout_clock) {
2919 host->timeout_clk = host->ops->get_timeout_clock(host);
2920 } else if (!(host->quirks &
2921 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2922 pr_err("%s: Hardware doesn't specify timeout clock "
2923 "frequency.\n", mmc_hostname(mmc));
2924 return -ENODEV;
2925 }
2926 }
2927 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2928 host->timeout_clk *= 1000;
2929
2930 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2931 host->timeout_clk = mmc->f_max / 1000;
2932
2933 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2934
2935 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2936
2937 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2938 host->flags |= SDHCI_AUTO_CMD12;
2939
2940 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2941 if ((host->version >= SDHCI_SPEC_300) &&
2942 ((host->flags & SDHCI_USE_ADMA) ||
2943 !(host->flags & SDHCI_USE_SDMA))) {
2944 host->flags |= SDHCI_AUTO_CMD23;
2945 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2946 } else {
2947 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2948 }
2949
2950 /*
2951 * A controller may support 8-bit width, but the board itself
2952 * might not have the pins brought out. Boards that support
2953 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2954 * their platform code before calling sdhci_add_host(), and we
2955 * won't assume 8-bit width for hosts without that CAP.
2956 */
2957 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2958 mmc->caps |= MMC_CAP_4_BIT_DATA;
2959
2960 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2961 mmc->caps &= ~MMC_CAP_CMD23;
2962
2963 if (caps[0] & SDHCI_CAN_DO_HISPD)
2964 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2965
2966 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2967 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2968 mmc->caps |= MMC_CAP_NEEDS_POLL;
2969
2970 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2971 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
2972 if (IS_ERR_OR_NULL(host->vqmmc)) {
2973 if (PTR_ERR(host->vqmmc) < 0) {
2974 pr_info("%s: no vqmmc regulator found\n",
2975 mmc_hostname(mmc));
2976 host->vqmmc = NULL;
2977 }
2978 } else {
2979 ret = regulator_enable(host->vqmmc);
2980 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2981 1950000))
2982 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2983 SDHCI_SUPPORT_SDR50 |
2984 SDHCI_SUPPORT_DDR50);
2985 if (ret) {
2986 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2987 mmc_hostname(mmc), ret);
2988 host->vqmmc = NULL;
2989 }
2990 }
2991
2992 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2993 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2994 SDHCI_SUPPORT_DDR50);
2995
2996 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2997 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2998 SDHCI_SUPPORT_DDR50))
2999 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3000
3001 /* SDR104 supports also implies SDR50 support */
3002 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3003 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3004 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3005 * field can be promoted to support HS200.
3006 */
3007 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3008 mmc->caps2 |= MMC_CAP2_HS200;
3009 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3010 mmc->caps |= MMC_CAP_UHS_SDR50;
3011
3012 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3013 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3014 mmc->caps |= MMC_CAP_UHS_DDR50;
3015
3016 /* Does the host need tuning for SDR50? */
3017 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3018 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3019
3020 /* Does the host need tuning for SDR104 / HS200? */
3021 if (mmc->caps2 & MMC_CAP2_HS200)
3022 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3023
3024 /* Driver Type(s) (A, C, D) supported by the host */
3025 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3026 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3027 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3028 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3029 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3030 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3031
3032 /* Initial value for re-tuning timer count */
3033 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3034 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3035
3036 /*
3037 * In case Re-tuning Timer is not disabled, the actual value of
3038 * re-tuning timer will be 2 ^ (n - 1).
3039 */
3040 if (host->tuning_count)
3041 host->tuning_count = 1 << (host->tuning_count - 1);
3042
3043 /* Re-tuning mode supported by the Host Controller */
3044 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3045 SDHCI_RETUNING_MODE_SHIFT;
3046
3047 ocr_avail = 0;
3048
3049 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
3050 if (IS_ERR_OR_NULL(host->vmmc)) {
3051 if (PTR_ERR(host->vmmc) < 0) {
3052 pr_info("%s: no vmmc regulator found\n",
3053 mmc_hostname(mmc));
3054 host->vmmc = NULL;
3055 }
3056 }
3057
3058 #ifdef CONFIG_REGULATOR
3059 /*
3060 * Voltage range check makes sense only if regulator reports
3061 * any voltage value.
3062 */
3063 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3064 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3065 3600000);
3066 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3067 caps[0] &= ~SDHCI_CAN_VDD_330;
3068 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3069 caps[0] &= ~SDHCI_CAN_VDD_300;
3070 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3071 1950000);
3072 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3073 caps[0] &= ~SDHCI_CAN_VDD_180;
3074 }
3075 #endif /* CONFIG_REGULATOR */
3076
3077 /*
3078 * According to SD Host Controller spec v3.00, if the Host System
3079 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3080 * the value is meaningful only if Voltage Support in the Capabilities
3081 * register is set. The actual current value is 4 times the register
3082 * value.
3083 */
3084 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3085 if (!max_current_caps && host->vmmc) {
3086 u32 curr = regulator_get_current_limit(host->vmmc);
3087 if (curr > 0) {
3088
3089 /* convert to SDHCI_MAX_CURRENT format */
3090 curr = curr/1000; /* convert to mA */
3091 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3092
3093 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3094 max_current_caps =
3095 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3096 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3097 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3098 }
3099 }
3100
3101 if (caps[0] & SDHCI_CAN_VDD_330) {
3102 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3103
3104 mmc->max_current_330 = ((max_current_caps &
3105 SDHCI_MAX_CURRENT_330_MASK) >>
3106 SDHCI_MAX_CURRENT_330_SHIFT) *
3107 SDHCI_MAX_CURRENT_MULTIPLIER;
3108 }
3109 if (caps[0] & SDHCI_CAN_VDD_300) {
3110 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3111
3112 mmc->max_current_300 = ((max_current_caps &
3113 SDHCI_MAX_CURRENT_300_MASK) >>
3114 SDHCI_MAX_CURRENT_300_SHIFT) *
3115 SDHCI_MAX_CURRENT_MULTIPLIER;
3116 }
3117 if (caps[0] & SDHCI_CAN_VDD_180) {
3118 ocr_avail |= MMC_VDD_165_195;
3119
3120 mmc->max_current_180 = ((max_current_caps &
3121 SDHCI_MAX_CURRENT_180_MASK) >>
3122 SDHCI_MAX_CURRENT_180_SHIFT) *
3123 SDHCI_MAX_CURRENT_MULTIPLIER;
3124 }
3125
3126 if (host->ocr_mask)
3127 ocr_avail = host->ocr_mask;
3128
3129 mmc->ocr_avail = ocr_avail;
3130 mmc->ocr_avail_sdio = ocr_avail;
3131 if (host->ocr_avail_sdio)
3132 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3133 mmc->ocr_avail_sd = ocr_avail;
3134 if (host->ocr_avail_sd)
3135 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3136 else /* normal SD controllers don't support 1.8V */
3137 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3138 mmc->ocr_avail_mmc = ocr_avail;
3139 if (host->ocr_avail_mmc)
3140 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3141
3142 if (mmc->ocr_avail == 0) {
3143 pr_err("%s: Hardware doesn't report any "
3144 "support voltages.\n", mmc_hostname(mmc));
3145 return -ENODEV;
3146 }
3147
3148 spin_lock_init(&host->lock);
3149
3150 /*
3151 * Maximum number of segments. Depends on if the hardware
3152 * can do scatter/gather or not.
3153 */
3154 if (host->flags & SDHCI_USE_ADMA)
3155 mmc->max_segs = 128;
3156 else if (host->flags & SDHCI_USE_SDMA)
3157 mmc->max_segs = 1;
3158 else /* PIO */
3159 mmc->max_segs = 128;
3160
3161 /*
3162 * Maximum number of sectors in one transfer. Limited by DMA boundary
3163 * size (512KiB).
3164 */
3165 mmc->max_req_size = 524288;
3166
3167 /*
3168 * Maximum segment size. Could be one segment with the maximum number
3169 * of bytes. When doing hardware scatter/gather, each entry cannot
3170 * be larger than 64 KiB though.
3171 */
3172 if (host->flags & SDHCI_USE_ADMA) {
3173 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3174 mmc->max_seg_size = 65535;
3175 else
3176 mmc->max_seg_size = 65536;
3177 } else {
3178 mmc->max_seg_size = mmc->max_req_size;
3179 }
3180
3181 /*
3182 * Maximum block size. This varies from controller to controller and
3183 * is specified in the capabilities register.
3184 */
3185 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3186 mmc->max_blk_size = 2;
3187 } else {
3188 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3189 SDHCI_MAX_BLOCK_SHIFT;
3190 if (mmc->max_blk_size >= 3) {
3191 pr_warning("%s: Invalid maximum block size, "
3192 "assuming 512 bytes\n", mmc_hostname(mmc));
3193 mmc->max_blk_size = 0;
3194 }
3195 }
3196
3197 mmc->max_blk_size = 512 << mmc->max_blk_size;
3198
3199 /*
3200 * Maximum block count.
3201 */
3202 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3203
3204 /*
3205 * Init tasklets.
3206 */
3207 tasklet_init(&host->card_tasklet,
3208 sdhci_tasklet_card, (unsigned long)host);
3209 tasklet_init(&host->finish_tasklet,
3210 sdhci_tasklet_finish, (unsigned long)host);
3211
3212 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3213
3214 if (host->version >= SDHCI_SPEC_300) {
3215 init_waitqueue_head(&host->buf_ready_int);
3216
3217 /* Initialize re-tuning timer */
3218 init_timer(&host->tuning_timer);
3219 host->tuning_timer.data = (unsigned long)host;
3220 host->tuning_timer.function = sdhci_tuning_timer;
3221 }
3222
3223 sdhci_init(host, 0);
3224
3225 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3226 mmc_hostname(mmc), host);
3227 if (ret) {
3228 pr_err("%s: Failed to request IRQ %d: %d\n",
3229 mmc_hostname(mmc), host->irq, ret);
3230 goto untasklet;
3231 }
3232
3233 #ifdef CONFIG_MMC_DEBUG
3234 sdhci_dumpregs(host);
3235 #endif
3236
3237 #ifdef SDHCI_USE_LEDS_CLASS
3238 snprintf(host->led_name, sizeof(host->led_name),
3239 "%s::", mmc_hostname(mmc));
3240 host->led.name = host->led_name;
3241 host->led.brightness = LED_OFF;
3242 host->led.default_trigger = mmc_hostname(mmc);
3243 host->led.brightness_set = sdhci_led_control;
3244
3245 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3246 if (ret) {
3247 pr_err("%s: Failed to register LED device: %d\n",
3248 mmc_hostname(mmc), ret);
3249 goto reset;
3250 }
3251 #endif
3252
3253 mmiowb();
3254
3255 mmc_add_host(mmc);
3256
3257 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3258 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3259 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3260 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3261
3262 sdhci_enable_card_detection(host);
3263
3264 return 0;
3265
3266 #ifdef SDHCI_USE_LEDS_CLASS
3267 reset:
3268 sdhci_reset(host, SDHCI_RESET_ALL);
3269 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3270 free_irq(host->irq, host);
3271 #endif
3272 untasklet:
3273 tasklet_kill(&host->card_tasklet);
3274 tasklet_kill(&host->finish_tasklet);
3275
3276 return ret;
3277 }
3278
3279 EXPORT_SYMBOL_GPL(sdhci_add_host);
3280
3281 void sdhci_remove_host(struct sdhci_host *host, int dead)
3282 {
3283 unsigned long flags;
3284
3285 if (dead) {
3286 spin_lock_irqsave(&host->lock, flags);
3287
3288 host->flags |= SDHCI_DEVICE_DEAD;
3289
3290 if (host->mrq) {
3291 pr_err("%s: Controller removed during "
3292 " transfer!\n", mmc_hostname(host->mmc));
3293
3294 host->mrq->cmd->error = -ENOMEDIUM;
3295 tasklet_schedule(&host->finish_tasklet);
3296 }
3297
3298 spin_unlock_irqrestore(&host->lock, flags);
3299 }
3300
3301 sdhci_disable_card_detection(host);
3302
3303 mmc_remove_host(host->mmc);
3304
3305 #ifdef SDHCI_USE_LEDS_CLASS
3306 led_classdev_unregister(&host->led);
3307 #endif
3308
3309 if (!dead)
3310 sdhci_reset(host, SDHCI_RESET_ALL);
3311
3312 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3313 free_irq(host->irq, host);
3314
3315 del_timer_sync(&host->timer);
3316
3317 tasklet_kill(&host->card_tasklet);
3318 tasklet_kill(&host->finish_tasklet);
3319
3320 if (host->vmmc) {
3321 regulator_disable(host->vmmc);
3322 regulator_put(host->vmmc);
3323 }
3324
3325 if (host->vqmmc) {
3326 regulator_disable(host->vqmmc);
3327 regulator_put(host->vqmmc);
3328 }
3329
3330 kfree(host->adma_desc);
3331 kfree(host->align_buffer);
3332
3333 host->adma_desc = NULL;
3334 host->align_buffer = NULL;
3335 }
3336
3337 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3338
3339 void sdhci_free_host(struct sdhci_host *host)
3340 {
3341 mmc_free_host(host->mmc);
3342 }
3343
3344 EXPORT_SYMBOL_GPL(sdhci_free_host);
3345
3346 /*****************************************************************************\
3347 * *
3348 * Driver init/exit *
3349 * *
3350 \*****************************************************************************/
3351
3352 static int __init sdhci_drv_init(void)
3353 {
3354 pr_info(DRIVER_NAME
3355 ": Secure Digital Host Controller Interface driver\n");
3356 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3357
3358 return 0;
3359 }
3360
3361 static void __exit sdhci_drv_exit(void)
3362 {
3363 }
3364
3365 module_init(sdhci_drv_init);
3366 module_exit(sdhci_drv_exit);
3367
3368 module_param(debug_quirks, uint, 0444);
3369 module_param(debug_quirks2, uint, 0444);
3370
3371 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3372 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3373 MODULE_LICENSE("GPL");
3374
3375 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3376 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux with added FPC-III support