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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / mtd / nand / cafe_nand.c
blobc34985a55101b0606f76ed580f1e13ac562913e2
1 /*
2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3 *
4 * The data sheet for this device can be found at:
5 * http://wiki.laptop.org/go/Datasheets
6 *
7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
11 #define DEBUG
12
13 #include <linux/device.h>
14 #undef DEBUG
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/rslib.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <asm/io.h>
26
27 #define CAFE_NAND_CTRL1 0x00
28 #define CAFE_NAND_CTRL2 0x04
29 #define CAFE_NAND_CTRL3 0x08
30 #define CAFE_NAND_STATUS 0x0c
31 #define CAFE_NAND_IRQ 0x10
32 #define CAFE_NAND_IRQ_MASK 0x14
33 #define CAFE_NAND_DATA_LEN 0x18
34 #define CAFE_NAND_ADDR1 0x1c
35 #define CAFE_NAND_ADDR2 0x20
36 #define CAFE_NAND_TIMING1 0x24
37 #define CAFE_NAND_TIMING2 0x28
38 #define CAFE_NAND_TIMING3 0x2c
39 #define CAFE_NAND_NONMEM 0x30
40 #define CAFE_NAND_ECC_RESULT 0x3C
41 #define CAFE_NAND_DMA_CTRL 0x40
42 #define CAFE_NAND_DMA_ADDR0 0x44
43 #define CAFE_NAND_DMA_ADDR1 0x48
44 #define CAFE_NAND_ECC_SYN01 0x50
45 #define CAFE_NAND_ECC_SYN23 0x54
46 #define CAFE_NAND_ECC_SYN45 0x58
47 #define CAFE_NAND_ECC_SYN67 0x5c
48 #define CAFE_NAND_READ_DATA 0x1000
49 #define CAFE_NAND_WRITE_DATA 0x2000
50
51 #define CAFE_GLOBAL_CTRL 0x3004
52 #define CAFE_GLOBAL_IRQ 0x3008
53 #define CAFE_GLOBAL_IRQ_MASK 0x300c
54 #define CAFE_NAND_RESET 0x3034
55
56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
57 #define CTRL1_CHIPSELECT (1<<19)
58
59 struct cafe_priv {
60 struct nand_chip nand;
61 struct pci_dev *pdev;
62 void __iomem *mmio;
63 struct rs_control *rs;
64 uint32_t ctl1;
65 uint32_t ctl2;
66 int datalen;
67 int nr_data;
68 int data_pos;
69 int page_addr;
70 dma_addr_t dmaaddr;
71 unsigned char *dmabuf;
72 };
73
74 static int usedma = 1;
75 module_param(usedma, int, 0644);
76
77 static int skipbbt = 0;
78 module_param(skipbbt, int, 0644);
79
80 static int debug = 0;
81 module_param(debug, int, 0644);
82
83 static int regdebug = 0;
84 module_param(regdebug, int, 0644);
85
86 static int checkecc = 1;
87 module_param(checkecc, int, 0644);
88
89 static unsigned int numtimings;
90 static int timing[3];
91 module_param_array(timing, int, &numtimings, 0644);
92
93 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
94
95 /* Hrm. Why isn't this already conditional on something in the struct device? */
96 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
97
98 /* Make it easier to switch to PIO if we need to */
99 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
100 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
101
102 static int cafe_device_ready(struct mtd_info *mtd)
103 {
104 struct cafe_priv *cafe = mtd->priv;
105 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
106 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
107
108 cafe_writel(cafe, irqs, NAND_IRQ);
109
110 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
111 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
112 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
113
114 return result;
115 }
116
117
118 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
119 {
120 struct cafe_priv *cafe = mtd->priv;
121
122 if (usedma)
123 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
124 else
125 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
126
127 cafe->datalen += len;
128
129 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
130 len, cafe->datalen);
131 }
132
133 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
134 {
135 struct cafe_priv *cafe = mtd->priv;
136
137 if (usedma)
138 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
139 else
140 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
141
142 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
143 len, cafe->datalen);
144 cafe->datalen += len;
145 }
146
147 static uint8_t cafe_read_byte(struct mtd_info *mtd)
148 {
149 struct cafe_priv *cafe = mtd->priv;
150 uint8_t d;
151
152 cafe_read_buf(mtd, &d, 1);
153 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
154
155 return d;
156 }
157
158 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
159 int column, int page_addr)
160 {
161 struct cafe_priv *cafe = mtd->priv;
162 int adrbytes = 0;
163 uint32_t ctl1;
164 uint32_t doneint = 0x80000000;
165
166 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
167 command, column, page_addr);
168
169 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
170 /* Second half of a command we already calculated */
171 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
172 ctl1 = cafe->ctl1;
173 cafe->ctl2 &= ~(1<<30);
174 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
175 cafe->ctl1, cafe->nr_data);
176 goto do_command;
177 }
178 /* Reset ECC engine */
179 cafe_writel(cafe, 0, NAND_CTRL2);
180
181 /* Emulate NAND_CMD_READOOB on large-page chips */
182 if (mtd->writesize > 512 &&
183 command == NAND_CMD_READOOB) {
184 column += mtd->writesize;
185 command = NAND_CMD_READ0;
186 }
187
188 /* FIXME: Do we need to send read command before sending data
189 for small-page chips, to position the buffer correctly? */
190
191 if (column != -1) {
192 cafe_writel(cafe, column, NAND_ADDR1);
193 adrbytes = 2;
194 if (page_addr != -1)
195 goto write_adr2;
196 } else if (page_addr != -1) {
197 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
198 page_addr >>= 16;
199 write_adr2:
200 cafe_writel(cafe, page_addr, NAND_ADDR2);
201 adrbytes += 2;
202 if (mtd->size > mtd->writesize << 16)
203 adrbytes++;
204 }
205
206 cafe->data_pos = cafe->datalen = 0;
207
208 /* Set command valid bit, mask in the chip select bit */
209 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
210
211 /* Set RD or WR bits as appropriate */
212 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
213 ctl1 |= (1<<26); /* rd */
214 /* Always 5 bytes, for now */
215 cafe->datalen = 4;
216 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
217 adrbytes = 1;
218 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
219 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
220 ctl1 |= 1<<26; /* rd */
221 /* For now, assume just read to end of page */
222 cafe->datalen = mtd->writesize + mtd->oobsize - column;
223 } else if (command == NAND_CMD_SEQIN)
224 ctl1 |= 1<<25; /* wr */
225
226 /* Set number of address bytes */
227 if (adrbytes)
228 ctl1 |= ((adrbytes-1)|8) << 27;
229
230 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
231 /* Ignore the first command of a pair; the hardware
232 deals with them both at once, later */
233 cafe->ctl1 = ctl1;
234 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
235 cafe->ctl1, cafe->datalen);
236 return;
237 }
238 /* RNDOUT and READ0 commands need a following byte */
239 if (command == NAND_CMD_RNDOUT)
240 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
241 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
242 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
243
244 do_command:
245 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
246 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
247
248 /* NB: The datasheet lies -- we really should be subtracting 1 here */
249 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
250 cafe_writel(cafe, 0x90000000, NAND_IRQ);
251 if (usedma && (ctl1 & (3<<25))) {
252 uint32_t dmactl = 0xc0000000 + cafe->datalen;
253 /* If WR or RD bits set, set up DMA */
254 if (ctl1 & (1<<26)) {
255 /* It's a read */
256 dmactl |= (1<<29);
257 /* ... so it's done when the DMA is done, not just
258 the command. */
259 doneint = 0x10000000;
260 }
261 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
262 }
263 cafe->datalen = 0;
264
265 if (unlikely(regdebug)) {
266 int i;
267 printk("About to write command %08x to register 0\n", ctl1);
268 for (i=4; i< 0x5c; i+=4)
269 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
270 }
271
272 cafe_writel(cafe, ctl1, NAND_CTRL1);
273 /* Apply this short delay always to ensure that we do wait tWB in
274 * any case on any machine. */
275 ndelay(100);
276
277 if (1) {
278 int c;
279 uint32_t irqs;
280
281 for (c = 500000; c != 0; c--) {
282 irqs = cafe_readl(cafe, NAND_IRQ);
283 if (irqs & doneint)
284 break;
285 udelay(1);
286 if (!(c % 100000))
287 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
288 cpu_relax();
289 }
290 cafe_writel(cafe, doneint, NAND_IRQ);
291 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
292 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
293 }
294
295 WARN_ON(cafe->ctl2 & (1<<30));
296
297 switch (command) {
298
299 case NAND_CMD_CACHEDPROG:
300 case NAND_CMD_PAGEPROG:
301 case NAND_CMD_ERASE1:
302 case NAND_CMD_ERASE2:
303 case NAND_CMD_SEQIN:
304 case NAND_CMD_RNDIN:
305 case NAND_CMD_STATUS:
306 case NAND_CMD_RNDOUT:
307 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
308 return;
309 }
310 nand_wait_ready(mtd);
311 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
312 }
313
314 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
315 {
316 struct cafe_priv *cafe = mtd->priv;
317
318 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
319
320 /* Mask the appropriate bit into the stored value of ctl1
321 which will be used by cafe_nand_cmdfunc() */
322 if (chipnr)
323 cafe->ctl1 |= CTRL1_CHIPSELECT;
324 else
325 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
326 }
327
328 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
329 {
330 struct mtd_info *mtd = id;
331 struct cafe_priv *cafe = mtd->priv;
332 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
333 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
334 if (!irqs)
335 return IRQ_NONE;
336
337 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
338 return IRQ_HANDLED;
339 }
340
341 static void cafe_nand_bug(struct mtd_info *mtd)
342 {
343 BUG();
344 }
345
346 static int cafe_nand_write_oob(struct mtd_info *mtd,
347 struct nand_chip *chip, int page)
348 {
349 int status = 0;
350
351 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
352 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
353 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
354 status = chip->waitfunc(mtd, chip);
355
356 return status & NAND_STATUS_FAIL ? -EIO : 0;
357 }
358
359 /* Don't use -- use nand_read_oob_std for now */
360 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
361 int page)
362 {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
364 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
365 return 0;
366 }
367 /**
368 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
369 * @mtd: mtd info structure
370 * @chip: nand chip info structure
371 * @buf: buffer to store read data
372 * @oob_required: caller expects OOB data read to chip->oob_poi
373 *
374 * The hw generator calculates the error syndrome automatically. Therefore
375 * we need a special oob layout and handling.
376 */
377 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
378 uint8_t *buf, int oob_required, int page)
379 {
380 struct cafe_priv *cafe = mtd->priv;
381 unsigned int max_bitflips = 0;
382
383 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
384 cafe_readl(cafe, NAND_ECC_RESULT),
385 cafe_readl(cafe, NAND_ECC_SYN01));
386
387 chip->read_buf(mtd, buf, mtd->writesize);
388 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
389
390 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
391 unsigned short syn[8], pat[4];
392 int pos[4];
393 u8 *oob = chip->oob_poi;
394 int i, n;
395
396 for (i=0; i<8; i+=2) {
397 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
398 syn[i] = cafe->rs->index_of[tmp & 0xfff];
399 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
400 }
401
402 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
403 pat);
404
405 for (i = 0; i < n; i++) {
406 int p = pos[i];
407
408 /* The 12-bit symbols are mapped to bytes here */
409
410 if (p > 1374) {
411 /* out of range */
412 n = -1374;
413 } else if (p == 0) {
414 /* high four bits do not correspond to data */
415 if (pat[i] > 0xff)
416 n = -2048;
417 else
418 buf[0] ^= pat[i];
419 } else if (p == 1365) {
420 buf[2047] ^= pat[i] >> 4;
421 oob[0] ^= pat[i] << 4;
422 } else if (p > 1365) {
423 if ((p & 1) == 1) {
424 oob[3*p/2 - 2048] ^= pat[i] >> 4;
425 oob[3*p/2 - 2047] ^= pat[i] << 4;
426 } else {
427 oob[3*p/2 - 2049] ^= pat[i] >> 8;
428 oob[3*p/2 - 2048] ^= pat[i];
429 }
430 } else if ((p & 1) == 1) {
431 buf[3*p/2] ^= pat[i] >> 4;
432 buf[3*p/2 + 1] ^= pat[i] << 4;
433 } else {
434 buf[3*p/2 - 1] ^= pat[i] >> 8;
435 buf[3*p/2] ^= pat[i];
436 }
437 }
438
439 if (n < 0) {
440 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
441 cafe_readl(cafe, NAND_ADDR2) * 2048);
442 for (i = 0; i < 0x5c; i += 4)
443 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
444 mtd->ecc_stats.failed++;
445 } else {
446 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
447 mtd->ecc_stats.corrected += n;
448 max_bitflips = max_t(unsigned int, max_bitflips, n);
449 }
450 }
451
452 return max_bitflips;
453 }
454
455 static struct nand_ecclayout cafe_oobinfo_2048 = {
456 .eccbytes = 14,
457 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
458 .oobfree = {{14, 50}}
459 };
460
461 /* Ick. The BBT code really ought to be able to work this bit out
462 for itself from the above, at least for the 2KiB case */
463 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
464 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
465
466 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
467 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
468
469
470 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
471 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
472 | NAND_BBT_2BIT | NAND_BBT_VERSION,
473 .offs = 14,
474 .len = 4,
475 .veroffs = 18,
476 .maxblocks = 4,
477 .pattern = cafe_bbt_pattern_2048
478 };
479
480 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
481 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
482 | NAND_BBT_2BIT | NAND_BBT_VERSION,
483 .offs = 14,
484 .len = 4,
485 .veroffs = 18,
486 .maxblocks = 4,
487 .pattern = cafe_mirror_pattern_2048
488 };
489
490 static struct nand_ecclayout cafe_oobinfo_512 = {
491 .eccbytes = 14,
492 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
493 .oobfree = {{14, 2}}
494 };
495
496 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
497 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
498 | NAND_BBT_2BIT | NAND_BBT_VERSION,
499 .offs = 14,
500 .len = 1,
501 .veroffs = 15,
502 .maxblocks = 4,
503 .pattern = cafe_bbt_pattern_512
504 };
505
506 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
507 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
508 | NAND_BBT_2BIT | NAND_BBT_VERSION,
509 .offs = 14,
510 .len = 1,
511 .veroffs = 15,
512 .maxblocks = 4,
513 .pattern = cafe_mirror_pattern_512
514 };
515
516
517 static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
518 struct nand_chip *chip,
519 const uint8_t *buf, int oob_required)
520 {
521 struct cafe_priv *cafe = mtd->priv;
522
523 chip->write_buf(mtd, buf, mtd->writesize);
524 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
525
526 /* Set up ECC autogeneration */
527 cafe->ctl2 |= (1<<30);
528
529 return 0;
530 }
531
532 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
533 uint32_t offset, int data_len, const uint8_t *buf,
534 int oob_required, int page, int cached, int raw)
535 {
536 int status;
537
538 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
539
540 if (unlikely(raw))
541 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
542 else
543 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
544
545 if (status < 0)
546 return status;
547
548 /*
549 * Cached progamming disabled for now, Not sure if its worth the
550 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
551 */
552 cached = 0;
553
554 if (!cached || !(chip->options & NAND_CACHEPRG)) {
555
556 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
557 status = chip->waitfunc(mtd, chip);
558 /*
559 * See if operation failed and additional status checks are
560 * available
561 */
562 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
563 status = chip->errstat(mtd, chip, FL_WRITING, status,
564 page);
565
566 if (status & NAND_STATUS_FAIL)
567 return -EIO;
568 } else {
569 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
570 status = chip->waitfunc(mtd, chip);
571 }
572
573 return 0;
574 }
575
576 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
577 {
578 return 0;
579 }
580
581 /* F_2[X]/(X**6+X+1) */
582 static unsigned short gf64_mul(u8 a, u8 b)
583 {
584 u8 c;
585 unsigned int i;
586
587 c = 0;
588 for (i = 0; i < 6; i++) {
589 if (a & 1)
590 c ^= b;
591 a >>= 1;
592 b <<= 1;
593 if ((b & 0x40) != 0)
594 b ^= 0x43;
595 }
596
597 return c;
598 }
599
600 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
601 static u16 gf4096_mul(u16 a, u16 b)
602 {
603 u8 ah, al, bh, bl, ch, cl;
604
605 ah = a >> 6;
606 al = a & 0x3f;
607 bh = b >> 6;
608 bl = b & 0x3f;
609
610 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
611 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
612
613 return (ch << 6) ^ cl;
614 }
615
616 static int cafe_mul(int x)
617 {
618 if (x == 0)
619 return 1;
620 return gf4096_mul(x, 0xe01);
621 }
622
623 static int cafe_nand_probe(struct pci_dev *pdev,
624 const struct pci_device_id *ent)
625 {
626 struct mtd_info *mtd;
627 struct cafe_priv *cafe;
628 uint32_t ctrl;
629 int err = 0;
630
631 /* Very old versions shared the same PCI ident for all three
632 functions on the chip. Verify the class too... */
633 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
634 return -ENODEV;
635
636 err = pci_enable_device(pdev);
637 if (err)
638 return err;
639
640 pci_set_master(pdev);
641
642 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
643 if (!mtd) {
644 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
645 return -ENOMEM;
646 }
647 cafe = (void *)(&mtd[1]);
648
649 mtd->dev.parent = &pdev->dev;
650 mtd->priv = cafe;
651 mtd->owner = THIS_MODULE;
652
653 cafe->pdev = pdev;
654 cafe->mmio = pci_iomap(pdev, 0, 0);
655 if (!cafe->mmio) {
656 dev_warn(&pdev->dev, "failed to iomap\n");
657 err = -ENOMEM;
658 goto out_free_mtd;
659 }
660 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
661 &cafe->dmaaddr, GFP_KERNEL);
662 if (!cafe->dmabuf) {
663 err = -ENOMEM;
664 goto out_ior;
665 }
666 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
667
668 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
669 if (!cafe->rs) {
670 err = -ENOMEM;
671 goto out_ior;
672 }
673
674 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
675 cafe->nand.dev_ready = cafe_device_ready;
676 cafe->nand.read_byte = cafe_read_byte;
677 cafe->nand.read_buf = cafe_read_buf;
678 cafe->nand.write_buf = cafe_write_buf;
679 cafe->nand.select_chip = cafe_select_chip;
680
681 cafe->nand.chip_delay = 0;
682
683 /* Enable the following for a flash based bad block table */
684 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
685 cafe->nand.options = NAND_OWN_BUFFERS;
686
687 if (skipbbt) {
688 cafe->nand.options |= NAND_SKIP_BBTSCAN;
689 cafe->nand.block_bad = cafe_nand_block_bad;
690 }
691
692 if (numtimings && numtimings != 3) {
693 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
694 }
695
696 if (numtimings == 3) {
697 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
698 timing[0], timing[1], timing[2]);
699 } else {
700 timing[0] = cafe_readl(cafe, NAND_TIMING1);
701 timing[1] = cafe_readl(cafe, NAND_TIMING2);
702 timing[2] = cafe_readl(cafe, NAND_TIMING3);
703
704 if (timing[0] | timing[1] | timing[2]) {
705 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
706 timing[0], timing[1], timing[2]);
707 } else {
708 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
709 timing[0] = timing[1] = timing[2] = 0xffffffff;
710 }
711 }
712
713 /* Start off by resetting the NAND controller completely */
714 cafe_writel(cafe, 1, NAND_RESET);
715 cafe_writel(cafe, 0, NAND_RESET);
716
717 cafe_writel(cafe, timing[0], NAND_TIMING1);
718 cafe_writel(cafe, timing[1], NAND_TIMING2);
719 cafe_writel(cafe, timing[2], NAND_TIMING3);
720
721 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
722 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
723 "CAFE NAND", mtd);
724 if (err) {
725 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
726 goto out_free_dma;
727 }
728
729 /* Disable master reset, enable NAND clock */
730 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
731 ctrl &= 0xffffeff0;
732 ctrl |= 0x00007000;
733 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
734 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
735 cafe_writel(cafe, 0, NAND_DMA_CTRL);
736
737 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
738 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
739
740 /* Set up DMA address */
741 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
742 if (sizeof(cafe->dmaaddr) > 4)
743 /* Shift in two parts to shut the compiler up */
744 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
745 else
746 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
747
748 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
749 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
750
751 /* Enable NAND IRQ in global IRQ mask register */
752 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
753 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
754 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
755
756 /* Scan to find existence of the device */
757 if (nand_scan_ident(mtd, 2, NULL)) {
758 err = -ENXIO;
759 goto out_irq;
760 }
761
762 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
763 if (mtd->writesize == 2048)
764 cafe->ctl2 |= 1<<29; /* 2KiB page size */
765
766 /* Set up ECC according to the type of chip we found */
767 if (mtd->writesize == 2048) {
768 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
769 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
770 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
771 } else if (mtd->writesize == 512) {
772 cafe->nand.ecc.layout = &cafe_oobinfo_512;
773 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
774 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
775 } else {
776 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
777 mtd->writesize);
778 goto out_irq;
779 }
780 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
781 cafe->nand.ecc.size = mtd->writesize;
782 cafe->nand.ecc.bytes = 14;
783 cafe->nand.ecc.strength = 4;
784 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
785 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
786 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
787 cafe->nand.write_page = cafe_nand_write_page;
788 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
789 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
790 cafe->nand.ecc.read_page = cafe_nand_read_page;
791 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
792
793 err = nand_scan_tail(mtd);
794 if (err)
795 goto out_irq;
796
797 pci_set_drvdata(pdev, mtd);
798
799 mtd->name = "cafe_nand";
800 mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
801
802 goto out;
803
804 out_irq:
805 /* Disable NAND IRQ in global IRQ mask register */
806 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
807 free_irq(pdev->irq, mtd);
808 out_free_dma:
809 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
810 out_ior:
811 pci_iounmap(pdev, cafe->mmio);
812 out_free_mtd:
813 kfree(mtd);
814 out:
815 return err;
816 }
817
818 static void cafe_nand_remove(struct pci_dev *pdev)
819 {
820 struct mtd_info *mtd = pci_get_drvdata(pdev);
821 struct cafe_priv *cafe = mtd->priv;
822
823 /* Disable NAND IRQ in global IRQ mask register */
824 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
825 free_irq(pdev->irq, mtd);
826 nand_release(mtd);
827 free_rs(cafe->rs);
828 pci_iounmap(pdev, cafe->mmio);
829 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
830 kfree(mtd);
831 }
832
833 static const struct pci_device_id cafe_nand_tbl[] = {
834 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
835 PCI_ANY_ID, PCI_ANY_ID },
836 { }
837 };
838
839 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
840
841 static int cafe_nand_resume(struct pci_dev *pdev)
842 {
843 uint32_t ctrl;
844 struct mtd_info *mtd = pci_get_drvdata(pdev);
845 struct cafe_priv *cafe = mtd->priv;
846
847 /* Start off by resetting the NAND controller completely */
848 cafe_writel(cafe, 1, NAND_RESET);
849 cafe_writel(cafe, 0, NAND_RESET);
850 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
851
852 /* Restore timing configuration */
853 cafe_writel(cafe, timing[0], NAND_TIMING1);
854 cafe_writel(cafe, timing[1], NAND_TIMING2);
855 cafe_writel(cafe, timing[2], NAND_TIMING3);
856
857 /* Disable master reset, enable NAND clock */
858 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
859 ctrl &= 0xffffeff0;
860 ctrl |= 0x00007000;
861 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
862 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
863 cafe_writel(cafe, 0, NAND_DMA_CTRL);
864 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
865 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
866
867 /* Set up DMA address */
868 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
869 if (sizeof(cafe->dmaaddr) > 4)
870 /* Shift in two parts to shut the compiler up */
871 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
872 else
873 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
874
875 /* Enable NAND IRQ in global IRQ mask register */
876 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
877 return 0;
878 }
879
880 static struct pci_driver cafe_nand_pci_driver = {
881 .name = "CAFÉ NAND",
882 .id_table = cafe_nand_tbl,
883 .probe = cafe_nand_probe,
884 .remove = cafe_nand_remove,
885 .resume = cafe_nand_resume,
886 };
887
888 module_pci_driver(cafe_nand_pci_driver);
889
890 MODULE_LICENSE("GPL");
891 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
892 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
Linux with added FPC-III support