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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / mtd / nand / mxc_nand.c
blobe5c0e593ed1e9802a520af06a8e72291cca32684
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of_device.h>
36 #include <linux/of_mtd.h>
37
38 #include <asm/mach/flash.h>
39 #include <linux/platform_data/mtd-mxc_nand.h>
40
41 #define DRIVER_NAME "mxc_nand"
42
43 /* Addresses for NFC registers */
44 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
45 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
46 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
47 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
48 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
49 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
50 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
51 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
52 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
53 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
54 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
55 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
56 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
57 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
58 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
59 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
60 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
61 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
62 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
63 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
64 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
65 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
66
67 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
68 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
69 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
70 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
71 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
72 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
73 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
74 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
75 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
76 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
77
78 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
79
80 /*
81 * Operation modes for the NFC. Valid for v1, v2 and v3
82 * type controllers.
83 */
84 #define NFC_CMD (1 << 0)
85 #define NFC_ADDR (1 << 1)
86 #define NFC_INPUT (1 << 2)
87 #define NFC_OUTPUT (1 << 3)
88 #define NFC_ID (1 << 4)
89 #define NFC_STATUS (1 << 5)
90
91 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
92 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
93
94 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
95 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
96 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
97
98 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
99
100 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
101
102 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
103 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
104 #define NFC_V3_WRPROT_LOCK (1 << 1)
105 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
106 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
107
108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
109
110 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
111 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
112 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
113 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
114 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
115 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
116 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
118 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
119 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
121 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
122 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
123 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
124
125 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
126 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
127 #define NFC_V3_CONFIG3_FW8 (1 << 3)
128 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
130 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
131 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
132
133 #define NFC_V3_IPC (host->regs_ip + 0x2C)
134 #define NFC_V3_IPC_CREQ (1 << 0)
135 #define NFC_V3_IPC_INT (1 << 31)
136
137 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
138
139 struct mxc_nand_host;
140
141 struct mxc_nand_devtype_data {
142 void (*preset)(struct mtd_info *);
143 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
144 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_page)(struct mtd_info *, unsigned int);
146 void (*send_read_id)(struct mxc_nand_host *);
147 uint16_t (*get_dev_status)(struct mxc_nand_host *);
148 int (*check_int)(struct mxc_nand_host *);
149 void (*irq_control)(struct mxc_nand_host *, int);
150 u32 (*get_ecc_status)(struct mxc_nand_host *);
151 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
152 void (*select_chip)(struct mtd_info *mtd, int chip);
153 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
154 u_char *read_ecc, u_char *calc_ecc);
155
156 /*
157 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
158 * (CONFIG1:INT_MSK is set). To handle this the driver uses
159 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
160 */
161 int irqpending_quirk;
162 int needs_ip;
163
164 size_t regs_offset;
165 size_t spare0_offset;
166 size_t axi_offset;
167
168 int spare_len;
169 int eccbytes;
170 int eccsize;
171 int ppb_shift;
172 };
173
174 struct mxc_nand_host {
175 struct mtd_info mtd;
176 struct nand_chip nand;
177 struct device *dev;
178
179 void __iomem *spare0;
180 void __iomem *main_area0;
181
182 void __iomem *base;
183 void __iomem *regs;
184 void __iomem *regs_axi;
185 void __iomem *regs_ip;
186 int status_request;
187 struct clk *clk;
188 int clk_act;
189 int irq;
190 int eccsize;
191 int active_cs;
192
193 struct completion op_completion;
194
195 uint8_t *data_buf;
196 unsigned int buf_start;
197
198 const struct mxc_nand_devtype_data *devtype_data;
199 struct mxc_nand_platform_data pdata;
200 };
201
202 /* OOB placement block for use with hardware ecc generation */
203 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
204 .eccbytes = 5,
205 .eccpos = {6, 7, 8, 9, 10},
206 .oobfree = {{0, 5}, {12, 4}, }
207 };
208
209 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
210 .eccbytes = 20,
211 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
212 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
213 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
214 };
215
216 /* OOB description for 512 byte pages with 16 byte OOB */
217 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
218 .eccbytes = 1 * 9,
219 .eccpos = {
220 7, 8, 9, 10, 11, 12, 13, 14, 15
221 },
222 .oobfree = {
223 {.offset = 0, .length = 5}
224 }
225 };
226
227 /* OOB description for 2048 byte pages with 64 byte OOB */
228 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
229 .eccbytes = 4 * 9,
230 .eccpos = {
231 7, 8, 9, 10, 11, 12, 13, 14, 15,
232 23, 24, 25, 26, 27, 28, 29, 30, 31,
233 39, 40, 41, 42, 43, 44, 45, 46, 47,
234 55, 56, 57, 58, 59, 60, 61, 62, 63
235 },
236 .oobfree = {
237 {.offset = 2, .length = 4},
238 {.offset = 16, .length = 7},
239 {.offset = 32, .length = 7},
240 {.offset = 48, .length = 7}
241 }
242 };
243
244 /* OOB description for 4096 byte pages with 128 byte OOB */
245 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
246 .eccbytes = 8 * 9,
247 .eccpos = {
248 7, 8, 9, 10, 11, 12, 13, 14, 15,
249 23, 24, 25, 26, 27, 28, 29, 30, 31,
250 39, 40, 41, 42, 43, 44, 45, 46, 47,
251 55, 56, 57, 58, 59, 60, 61, 62, 63,
252 71, 72, 73, 74, 75, 76, 77, 78, 79,
253 87, 88, 89, 90, 91, 92, 93, 94, 95,
254 103, 104, 105, 106, 107, 108, 109, 110, 111,
255 119, 120, 121, 122, 123, 124, 125, 126, 127,
256 },
257 .oobfree = {
258 {.offset = 2, .length = 4},
259 {.offset = 16, .length = 7},
260 {.offset = 32, .length = 7},
261 {.offset = 48, .length = 7},
262 {.offset = 64, .length = 7},
263 {.offset = 80, .length = 7},
264 {.offset = 96, .length = 7},
265 {.offset = 112, .length = 7},
266 }
267 };
268
269 static const char * const part_probes[] = {
270 "cmdlinepart", "RedBoot", "ofpart", NULL };
271
272 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
273 {
274 int i;
275 u32 *t = trg;
276 const __iomem u32 *s = src;
277
278 for (i = 0; i < (size >> 2); i++)
279 *t++ = __raw_readl(s++);
280 }
281
282 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
283 {
284 int i;
285 u32 __iomem *t = trg;
286 const u32 *s = src;
287
288 for (i = 0; i < (size >> 2); i++)
289 __raw_writel(*s++, t++);
290 }
291
292 static int check_int_v3(struct mxc_nand_host *host)
293 {
294 uint32_t tmp;
295
296 tmp = readl(NFC_V3_IPC);
297 if (!(tmp & NFC_V3_IPC_INT))
298 return 0;
299
300 tmp &= ~NFC_V3_IPC_INT;
301 writel(tmp, NFC_V3_IPC);
302
303 return 1;
304 }
305
306 static int check_int_v1_v2(struct mxc_nand_host *host)
307 {
308 uint32_t tmp;
309
310 tmp = readw(NFC_V1_V2_CONFIG2);
311 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
312 return 0;
313
314 if (!host->devtype_data->irqpending_quirk)
315 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
316
317 return 1;
318 }
319
320 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
321 {
322 uint16_t tmp;
323
324 tmp = readw(NFC_V1_V2_CONFIG1);
325
326 if (activate)
327 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
328 else
329 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
330
331 writew(tmp, NFC_V1_V2_CONFIG1);
332 }
333
334 static void irq_control_v3(struct mxc_nand_host *host, int activate)
335 {
336 uint32_t tmp;
337
338 tmp = readl(NFC_V3_CONFIG2);
339
340 if (activate)
341 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
342 else
343 tmp |= NFC_V3_CONFIG2_INT_MSK;
344
345 writel(tmp, NFC_V3_CONFIG2);
346 }
347
348 static void irq_control(struct mxc_nand_host *host, int activate)
349 {
350 if (host->devtype_data->irqpending_quirk) {
351 if (activate)
352 enable_irq(host->irq);
353 else
354 disable_irq_nosync(host->irq);
355 } else {
356 host->devtype_data->irq_control(host, activate);
357 }
358 }
359
360 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
361 {
362 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
363 }
364
365 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
366 {
367 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
368 }
369
370 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
371 {
372 return readl(NFC_V3_ECC_STATUS_RESULT);
373 }
374
375 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
376 {
377 struct mxc_nand_host *host = dev_id;
378
379 if (!host->devtype_data->check_int(host))
380 return IRQ_NONE;
381
382 irq_control(host, 0);
383
384 complete(&host->op_completion);
385
386 return IRQ_HANDLED;
387 }
388
389 /* This function polls the NANDFC to wait for the basic operation to
390 * complete by checking the INT bit of config2 register.
391 */
392 static void wait_op_done(struct mxc_nand_host *host, int useirq)
393 {
394 int max_retries = 8000;
395
396 if (useirq) {
397 if (!host->devtype_data->check_int(host)) {
398 INIT_COMPLETION(host->op_completion);
399 irq_control(host, 1);
400 wait_for_completion(&host->op_completion);
401 }
402 } else {
403 while (max_retries-- > 0) {
404 if (host->devtype_data->check_int(host))
405 break;
406
407 udelay(1);
408 }
409 if (max_retries < 0)
410 pr_debug("%s: INT not set\n", __func__);
411 }
412 }
413
414 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
415 {
416 /* fill command */
417 writel(cmd, NFC_V3_FLASH_CMD);
418
419 /* send out command */
420 writel(NFC_CMD, NFC_V3_LAUNCH);
421
422 /* Wait for operation to complete */
423 wait_op_done(host, useirq);
424 }
425
426 /* This function issues the specified command to the NAND device and
427 * waits for completion. */
428 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
429 {
430 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
431
432 writew(cmd, NFC_V1_V2_FLASH_CMD);
433 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
434
435 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
436 int max_retries = 100;
437 /* Reset completion is indicated by NFC_CONFIG2 */
438 /* being set to 0 */
439 while (max_retries-- > 0) {
440 if (readw(NFC_V1_V2_CONFIG2) == 0) {
441 break;
442 }
443 udelay(1);
444 }
445 if (max_retries < 0)
446 pr_debug("%s: RESET failed\n", __func__);
447 } else {
448 /* Wait for operation to complete */
449 wait_op_done(host, useirq);
450 }
451 }
452
453 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
454 {
455 /* fill address */
456 writel(addr, NFC_V3_FLASH_ADDR0);
457
458 /* send out address */
459 writel(NFC_ADDR, NFC_V3_LAUNCH);
460
461 wait_op_done(host, 0);
462 }
463
464 /* This function sends an address (or partial address) to the
465 * NAND device. The address is used to select the source/destination for
466 * a NAND command. */
467 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
468 {
469 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
470
471 writew(addr, NFC_V1_V2_FLASH_ADDR);
472 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
473
474 /* Wait for operation to complete */
475 wait_op_done(host, islast);
476 }
477
478 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
479 {
480 struct nand_chip *nand_chip = mtd->priv;
481 struct mxc_nand_host *host = nand_chip->priv;
482 uint32_t tmp;
483
484 tmp = readl(NFC_V3_CONFIG1);
485 tmp &= ~(7 << 4);
486 writel(tmp, NFC_V3_CONFIG1);
487
488 /* transfer data from NFC ram to nand */
489 writel(ops, NFC_V3_LAUNCH);
490
491 wait_op_done(host, false);
492 }
493
494 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
495 {
496 struct nand_chip *nand_chip = mtd->priv;
497 struct mxc_nand_host *host = nand_chip->priv;
498
499 /* NANDFC buffer 0 is used for page read/write */
500 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
501
502 writew(ops, NFC_V1_V2_CONFIG2);
503
504 /* Wait for operation to complete */
505 wait_op_done(host, true);
506 }
507
508 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
509 {
510 struct nand_chip *nand_chip = mtd->priv;
511 struct mxc_nand_host *host = nand_chip->priv;
512 int bufs, i;
513
514 if (mtd->writesize > 512)
515 bufs = 4;
516 else
517 bufs = 1;
518
519 for (i = 0; i < bufs; i++) {
520
521 /* NANDFC buffer 0 is used for page read/write */
522 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
523
524 writew(ops, NFC_V1_V2_CONFIG2);
525
526 /* Wait for operation to complete */
527 wait_op_done(host, true);
528 }
529 }
530
531 static void send_read_id_v3(struct mxc_nand_host *host)
532 {
533 struct nand_chip *this = &host->nand;
534
535 /* Read ID into main buffer */
536 writel(NFC_ID, NFC_V3_LAUNCH);
537
538 wait_op_done(host, true);
539
540 memcpy32_fromio(host->data_buf, host->main_area0, 16);
541
542 if (this->options & NAND_BUSWIDTH_16) {
543 /* compress the ID info */
544 host->data_buf[1] = host->data_buf[2];
545 host->data_buf[2] = host->data_buf[4];
546 host->data_buf[3] = host->data_buf[6];
547 host->data_buf[4] = host->data_buf[8];
548 host->data_buf[5] = host->data_buf[10];
549 }
550 }
551
552 /* Request the NANDFC to perform a read of the NAND device ID. */
553 static void send_read_id_v1_v2(struct mxc_nand_host *host)
554 {
555 struct nand_chip *this = &host->nand;
556
557 /* NANDFC buffer 0 is used for device ID output */
558 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
559
560 writew(NFC_ID, NFC_V1_V2_CONFIG2);
561
562 /* Wait for operation to complete */
563 wait_op_done(host, true);
564
565 memcpy32_fromio(host->data_buf, host->main_area0, 16);
566
567 if (this->options & NAND_BUSWIDTH_16) {
568 /* compress the ID info */
569 host->data_buf[1] = host->data_buf[2];
570 host->data_buf[2] = host->data_buf[4];
571 host->data_buf[3] = host->data_buf[6];
572 host->data_buf[4] = host->data_buf[8];
573 host->data_buf[5] = host->data_buf[10];
574 }
575 }
576
577 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
578 {
579 writew(NFC_STATUS, NFC_V3_LAUNCH);
580 wait_op_done(host, true);
581
582 return readl(NFC_V3_CONFIG1) >> 16;
583 }
584
585 /* This function requests the NANDFC to perform a read of the
586 * NAND device status and returns the current status. */
587 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
588 {
589 void __iomem *main_buf = host->main_area0;
590 uint32_t store;
591 uint16_t ret;
592
593 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
594
595 /*
596 * The device status is stored in main_area0. To
597 * prevent corruption of the buffer save the value
598 * and restore it afterwards.
599 */
600 store = readl(main_buf);
601
602 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
603 wait_op_done(host, true);
604
605 ret = readw(main_buf);
606
607 writel(store, main_buf);
608
609 return ret;
610 }
611
612 /* This functions is used by upper layer to checks if device is ready */
613 static int mxc_nand_dev_ready(struct mtd_info *mtd)
614 {
615 /*
616 * NFC handles R/B internally. Therefore, this function
617 * always returns status as ready.
618 */
619 return 1;
620 }
621
622 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
623 {
624 /*
625 * If HW ECC is enabled, we turn it on during init. There is
626 * no need to enable again here.
627 */
628 }
629
630 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
631 u_char *read_ecc, u_char *calc_ecc)
632 {
633 struct nand_chip *nand_chip = mtd->priv;
634 struct mxc_nand_host *host = nand_chip->priv;
635
636 /*
637 * 1-Bit errors are automatically corrected in HW. No need for
638 * additional correction. 2-Bit errors cannot be corrected by
639 * HW ECC, so we need to return failure
640 */
641 uint16_t ecc_status = get_ecc_status_v1(host);
642
643 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
644 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
645 return -1;
646 }
647
648 return 0;
649 }
650
651 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
652 u_char *read_ecc, u_char *calc_ecc)
653 {
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
656 u32 ecc_stat, err;
657 int no_subpages = 1;
658 int ret = 0;
659 u8 ecc_bit_mask, err_limit;
660
661 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
662 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
663
664 no_subpages = mtd->writesize >> 9;
665
666 ecc_stat = host->devtype_data->get_ecc_status(host);
667
668 do {
669 err = ecc_stat & ecc_bit_mask;
670 if (err > err_limit) {
671 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
672 return -1;
673 } else {
674 ret += err;
675 }
676 ecc_stat >>= 4;
677 } while (--no_subpages);
678
679 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
680
681 return ret;
682 }
683
684 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
685 u_char *ecc_code)
686 {
687 return 0;
688 }
689
690 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
691 {
692 struct nand_chip *nand_chip = mtd->priv;
693 struct mxc_nand_host *host = nand_chip->priv;
694 uint8_t ret;
695
696 /* Check for status request */
697 if (host->status_request)
698 return host->devtype_data->get_dev_status(host) & 0xFF;
699
700 ret = *(uint8_t *)(host->data_buf + host->buf_start);
701 host->buf_start++;
702
703 return ret;
704 }
705
706 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
707 {
708 struct nand_chip *nand_chip = mtd->priv;
709 struct mxc_nand_host *host = nand_chip->priv;
710 uint16_t ret;
711
712 ret = *(uint16_t *)(host->data_buf + host->buf_start);
713 host->buf_start += 2;
714
715 return ret;
716 }
717
718 /* Write data of length len to buffer buf. The data to be
719 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
720 * Operation by the NFC, the data is written to NAND Flash */
721 static void mxc_nand_write_buf(struct mtd_info *mtd,
722 const u_char *buf, int len)
723 {
724 struct nand_chip *nand_chip = mtd->priv;
725 struct mxc_nand_host *host = nand_chip->priv;
726 u16 col = host->buf_start;
727 int n = mtd->oobsize + mtd->writesize - col;
728
729 n = min(n, len);
730
731 memcpy(host->data_buf + col, buf, n);
732
733 host->buf_start += n;
734 }
735
736 /* Read the data buffer from the NAND Flash. To read the data from NAND
737 * Flash first the data output cycle is initiated by the NFC, which copies
738 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
739 */
740 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
741 {
742 struct nand_chip *nand_chip = mtd->priv;
743 struct mxc_nand_host *host = nand_chip->priv;
744 u16 col = host->buf_start;
745 int n = mtd->oobsize + mtd->writesize - col;
746
747 n = min(n, len);
748
749 memcpy(buf, host->data_buf + col, n);
750
751 host->buf_start += n;
752 }
753
754 /* This function is used by upper layer for select and
755 * deselect of the NAND chip */
756 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
757 {
758 struct nand_chip *nand_chip = mtd->priv;
759 struct mxc_nand_host *host = nand_chip->priv;
760
761 if (chip == -1) {
762 /* Disable the NFC clock */
763 if (host->clk_act) {
764 clk_disable_unprepare(host->clk);
765 host->clk_act = 0;
766 }
767 return;
768 }
769
770 if (!host->clk_act) {
771 /* Enable the NFC clock */
772 clk_prepare_enable(host->clk);
773 host->clk_act = 1;
774 }
775 }
776
777 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
778 {
779 struct nand_chip *nand_chip = mtd->priv;
780 struct mxc_nand_host *host = nand_chip->priv;
781
782 if (chip == -1) {
783 /* Disable the NFC clock */
784 if (host->clk_act) {
785 clk_disable_unprepare(host->clk);
786 host->clk_act = 0;
787 }
788 return;
789 }
790
791 if (!host->clk_act) {
792 /* Enable the NFC clock */
793 clk_prepare_enable(host->clk);
794 host->clk_act = 1;
795 }
796
797 host->active_cs = chip;
798 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
799 }
800
801 /*
802 * Function to transfer data to/from spare area.
803 */
804 static void copy_spare(struct mtd_info *mtd, bool bfrom)
805 {
806 struct nand_chip *this = mtd->priv;
807 struct mxc_nand_host *host = this->priv;
808 u16 i, j;
809 u16 n = mtd->writesize >> 9;
810 u8 *d = host->data_buf + mtd->writesize;
811 u8 __iomem *s = host->spare0;
812 u16 t = host->devtype_data->spare_len;
813
814 j = (mtd->oobsize / n >> 1) << 1;
815
816 if (bfrom) {
817 for (i = 0; i < n - 1; i++)
818 memcpy32_fromio(d + i * j, s + i * t, j);
819
820 /* the last section */
821 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
822 } else {
823 for (i = 0; i < n - 1; i++)
824 memcpy32_toio(&s[i * t], &d[i * j], j);
825
826 /* the last section */
827 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
828 }
829 }
830
831 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
832 {
833 struct nand_chip *nand_chip = mtd->priv;
834 struct mxc_nand_host *host = nand_chip->priv;
835
836 /* Write out column address, if necessary */
837 if (column != -1) {
838 /*
839 * MXC NANDFC can only perform full page+spare or
840 * spare-only read/write. When the upper layers
841 * perform a read/write buf operation, the saved column
842 * address is used to index into the full page.
843 */
844 host->devtype_data->send_addr(host, 0, page_addr == -1);
845 if (mtd->writesize > 512)
846 /* another col addr cycle for 2k page */
847 host->devtype_data->send_addr(host, 0, false);
848 }
849
850 /* Write out page address, if necessary */
851 if (page_addr != -1) {
852 /* paddr_0 - p_addr_7 */
853 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
854
855 if (mtd->writesize > 512) {
856 if (mtd->size >= 0x10000000) {
857 /* paddr_8 - paddr_15 */
858 host->devtype_data->send_addr(host,
859 (page_addr >> 8) & 0xff,
860 false);
861 host->devtype_data->send_addr(host,
862 (page_addr >> 16) & 0xff,
863 true);
864 } else
865 /* paddr_8 - paddr_15 */
866 host->devtype_data->send_addr(host,
867 (page_addr >> 8) & 0xff, true);
868 } else {
869 /* One more address cycle for higher density devices */
870 if (mtd->size >= 0x4000000) {
871 /* paddr_8 - paddr_15 */
872 host->devtype_data->send_addr(host,
873 (page_addr >> 8) & 0xff,
874 false);
875 host->devtype_data->send_addr(host,
876 (page_addr >> 16) & 0xff,
877 true);
878 } else
879 /* paddr_8 - paddr_15 */
880 host->devtype_data->send_addr(host,
881 (page_addr >> 8) & 0xff, true);
882 }
883 }
884 }
885
886 /*
887 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
888 * on how much oob the nand chip has. For 8bit ecc we need at least
889 * 26 bytes of oob data per 512 byte block.
890 */
891 static int get_eccsize(struct mtd_info *mtd)
892 {
893 int oobbytes_per_512 = 0;
894
895 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
896
897 if (oobbytes_per_512 < 26)
898 return 4;
899 else
900 return 8;
901 }
902
903 static void preset_v1(struct mtd_info *mtd)
904 {
905 struct nand_chip *nand_chip = mtd->priv;
906 struct mxc_nand_host *host = nand_chip->priv;
907 uint16_t config1 = 0;
908
909 if (nand_chip->ecc.mode == NAND_ECC_HW)
910 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
911
912 if (!host->devtype_data->irqpending_quirk)
913 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
914
915 host->eccsize = 1;
916
917 writew(config1, NFC_V1_V2_CONFIG1);
918 /* preset operation */
919
920 /* Unlock the internal RAM Buffer */
921 writew(0x2, NFC_V1_V2_CONFIG);
922
923 /* Blocks to be unlocked */
924 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
925 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
926
927 /* Unlock Block Command for given address range */
928 writew(0x4, NFC_V1_V2_WRPROT);
929 }
930
931 static void preset_v2(struct mtd_info *mtd)
932 {
933 struct nand_chip *nand_chip = mtd->priv;
934 struct mxc_nand_host *host = nand_chip->priv;
935 uint16_t config1 = 0;
936
937 if (nand_chip->ecc.mode == NAND_ECC_HW)
938 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
939
940 config1 |= NFC_V2_CONFIG1_FP_INT;
941
942 if (!host->devtype_data->irqpending_quirk)
943 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
944
945 if (mtd->writesize) {
946 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
947
948 host->eccsize = get_eccsize(mtd);
949 if (host->eccsize == 4)
950 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
951
952 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
953 } else {
954 host->eccsize = 1;
955 }
956
957 writew(config1, NFC_V1_V2_CONFIG1);
958 /* preset operation */
959
960 /* Unlock the internal RAM Buffer */
961 writew(0x2, NFC_V1_V2_CONFIG);
962
963 /* Blocks to be unlocked */
964 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
965 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
966 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
967 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
968 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
969 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
970 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
971 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
972
973 /* Unlock Block Command for given address range */
974 writew(0x4, NFC_V1_V2_WRPROT);
975 }
976
977 static void preset_v3(struct mtd_info *mtd)
978 {
979 struct nand_chip *chip = mtd->priv;
980 struct mxc_nand_host *host = chip->priv;
981 uint32_t config2, config3;
982 int i, addr_phases;
983
984 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
985 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
986
987 /* Unlock the internal RAM Buffer */
988 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
989 NFC_V3_WRPROT);
990
991 /* Blocks to be unlocked */
992 for (i = 0; i < NAND_MAX_CHIPS; i++)
993 writel(0x0 | (0xffff << 16),
994 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
995
996 writel(0, NFC_V3_IPC);
997
998 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
999 NFC_V3_CONFIG2_2CMD_PHASES |
1000 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1001 NFC_V3_CONFIG2_ST_CMD(0x70) |
1002 NFC_V3_CONFIG2_INT_MSK |
1003 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1004
1005 if (chip->ecc.mode == NAND_ECC_HW)
1006 config2 |= NFC_V3_CONFIG2_ECC_EN;
1007
1008 addr_phases = fls(chip->pagemask) >> 3;
1009
1010 if (mtd->writesize == 2048) {
1011 config2 |= NFC_V3_CONFIG2_PS_2048;
1012 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1013 } else if (mtd->writesize == 4096) {
1014 config2 |= NFC_V3_CONFIG2_PS_4096;
1015 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1016 } else {
1017 config2 |= NFC_V3_CONFIG2_PS_512;
1018 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1019 }
1020
1021 if (mtd->writesize) {
1022 config2 |= NFC_V3_CONFIG2_PPB(
1023 ffs(mtd->erasesize / mtd->writesize) - 6,
1024 host->devtype_data->ppb_shift);
1025 host->eccsize = get_eccsize(mtd);
1026 if (host->eccsize == 8)
1027 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1028 }
1029
1030 writel(config2, NFC_V3_CONFIG2);
1031
1032 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1033 NFC_V3_CONFIG3_NO_SDMA |
1034 NFC_V3_CONFIG3_RBB_MODE |
1035 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1036 NFC_V3_CONFIG3_ADD_OP(0);
1037
1038 if (!(chip->options & NAND_BUSWIDTH_16))
1039 config3 |= NFC_V3_CONFIG3_FW8;
1040
1041 writel(config3, NFC_V3_CONFIG3);
1042
1043 writel(0, NFC_V3_DELAY_LINE);
1044 }
1045
1046 /* Used by the upper layer to write command to NAND Flash for
1047 * different operations to be carried out on NAND Flash */
1048 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1049 int column, int page_addr)
1050 {
1051 struct nand_chip *nand_chip = mtd->priv;
1052 struct mxc_nand_host *host = nand_chip->priv;
1053
1054 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1055 command, column, page_addr);
1056
1057 /* Reset command state information */
1058 host->status_request = false;
1059
1060 /* Command pre-processing step */
1061 switch (command) {
1062 case NAND_CMD_RESET:
1063 host->devtype_data->preset(mtd);
1064 host->devtype_data->send_cmd(host, command, false);
1065 break;
1066
1067 case NAND_CMD_STATUS:
1068 host->buf_start = 0;
1069 host->status_request = true;
1070
1071 host->devtype_data->send_cmd(host, command, true);
1072 mxc_do_addr_cycle(mtd, column, page_addr);
1073 break;
1074
1075 case NAND_CMD_READ0:
1076 case NAND_CMD_READOOB:
1077 if (command == NAND_CMD_READ0)
1078 host->buf_start = column;
1079 else
1080 host->buf_start = column + mtd->writesize;
1081
1082 command = NAND_CMD_READ0; /* only READ0 is valid */
1083
1084 host->devtype_data->send_cmd(host, command, false);
1085 mxc_do_addr_cycle(mtd, column, page_addr);
1086
1087 if (mtd->writesize > 512)
1088 host->devtype_data->send_cmd(host,
1089 NAND_CMD_READSTART, true);
1090
1091 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1092
1093 memcpy32_fromio(host->data_buf, host->main_area0,
1094 mtd->writesize);
1095 copy_spare(mtd, true);
1096 break;
1097
1098 case NAND_CMD_SEQIN:
1099 if (column >= mtd->writesize)
1100 /* call ourself to read a page */
1101 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1102
1103 host->buf_start = column;
1104
1105 host->devtype_data->send_cmd(host, command, false);
1106 mxc_do_addr_cycle(mtd, column, page_addr);
1107 break;
1108
1109 case NAND_CMD_PAGEPROG:
1110 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1111 copy_spare(mtd, false);
1112 host->devtype_data->send_page(mtd, NFC_INPUT);
1113 host->devtype_data->send_cmd(host, command, true);
1114 mxc_do_addr_cycle(mtd, column, page_addr);
1115 break;
1116
1117 case NAND_CMD_READID:
1118 host->devtype_data->send_cmd(host, command, true);
1119 mxc_do_addr_cycle(mtd, column, page_addr);
1120 host->devtype_data->send_read_id(host);
1121 host->buf_start = column;
1122 break;
1123
1124 case NAND_CMD_ERASE1:
1125 case NAND_CMD_ERASE2:
1126 host->devtype_data->send_cmd(host, command, false);
1127 mxc_do_addr_cycle(mtd, column, page_addr);
1128
1129 break;
1130 }
1131 }
1132
1133 /*
1134 * The generic flash bbt decriptors overlap with our ecc
1135 * hardware, so define some i.MX specific ones.
1136 */
1137 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1138 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1139
1140 static struct nand_bbt_descr bbt_main_descr = {
1141 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1142 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1143 .offs = 0,
1144 .len = 4,
1145 .veroffs = 4,
1146 .maxblocks = 4,
1147 .pattern = bbt_pattern,
1148 };
1149
1150 static struct nand_bbt_descr bbt_mirror_descr = {
1151 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1152 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1153 .offs = 0,
1154 .len = 4,
1155 .veroffs = 4,
1156 .maxblocks = 4,
1157 .pattern = mirror_pattern,
1158 };
1159
1160 /* v1 + irqpending_quirk: i.MX21 */
1161 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1162 .preset = preset_v1,
1163 .send_cmd = send_cmd_v1_v2,
1164 .send_addr = send_addr_v1_v2,
1165 .send_page = send_page_v1,
1166 .send_read_id = send_read_id_v1_v2,
1167 .get_dev_status = get_dev_status_v1_v2,
1168 .check_int = check_int_v1_v2,
1169 .irq_control = irq_control_v1_v2,
1170 .get_ecc_status = get_ecc_status_v1,
1171 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1172 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1173 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1174 .select_chip = mxc_nand_select_chip_v1_v3,
1175 .correct_data = mxc_nand_correct_data_v1,
1176 .irqpending_quirk = 1,
1177 .needs_ip = 0,
1178 .regs_offset = 0xe00,
1179 .spare0_offset = 0x800,
1180 .spare_len = 16,
1181 .eccbytes = 3,
1182 .eccsize = 1,
1183 };
1184
1185 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1186 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1187 .preset = preset_v1,
1188 .send_cmd = send_cmd_v1_v2,
1189 .send_addr = send_addr_v1_v2,
1190 .send_page = send_page_v1,
1191 .send_read_id = send_read_id_v1_v2,
1192 .get_dev_status = get_dev_status_v1_v2,
1193 .check_int = check_int_v1_v2,
1194 .irq_control = irq_control_v1_v2,
1195 .get_ecc_status = get_ecc_status_v1,
1196 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1197 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1198 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1199 .select_chip = mxc_nand_select_chip_v1_v3,
1200 .correct_data = mxc_nand_correct_data_v1,
1201 .irqpending_quirk = 0,
1202 .needs_ip = 0,
1203 .regs_offset = 0xe00,
1204 .spare0_offset = 0x800,
1205 .axi_offset = 0,
1206 .spare_len = 16,
1207 .eccbytes = 3,
1208 .eccsize = 1,
1209 };
1210
1211 /* v21: i.MX25, i.MX35 */
1212 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1213 .preset = preset_v2,
1214 .send_cmd = send_cmd_v1_v2,
1215 .send_addr = send_addr_v1_v2,
1216 .send_page = send_page_v2,
1217 .send_read_id = send_read_id_v1_v2,
1218 .get_dev_status = get_dev_status_v1_v2,
1219 .check_int = check_int_v1_v2,
1220 .irq_control = irq_control_v1_v2,
1221 .get_ecc_status = get_ecc_status_v2,
1222 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1223 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1224 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1225 .select_chip = mxc_nand_select_chip_v2,
1226 .correct_data = mxc_nand_correct_data_v2_v3,
1227 .irqpending_quirk = 0,
1228 .needs_ip = 0,
1229 .regs_offset = 0x1e00,
1230 .spare0_offset = 0x1000,
1231 .axi_offset = 0,
1232 .spare_len = 64,
1233 .eccbytes = 9,
1234 .eccsize = 0,
1235 };
1236
1237 /* v3.2a: i.MX51 */
1238 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1239 .preset = preset_v3,
1240 .send_cmd = send_cmd_v3,
1241 .send_addr = send_addr_v3,
1242 .send_page = send_page_v3,
1243 .send_read_id = send_read_id_v3,
1244 .get_dev_status = get_dev_status_v3,
1245 .check_int = check_int_v3,
1246 .irq_control = irq_control_v3,
1247 .get_ecc_status = get_ecc_status_v3,
1248 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1249 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1250 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1251 .select_chip = mxc_nand_select_chip_v1_v3,
1252 .correct_data = mxc_nand_correct_data_v2_v3,
1253 .irqpending_quirk = 0,
1254 .needs_ip = 1,
1255 .regs_offset = 0,
1256 .spare0_offset = 0x1000,
1257 .axi_offset = 0x1e00,
1258 .spare_len = 64,
1259 .eccbytes = 0,
1260 .eccsize = 0,
1261 .ppb_shift = 7,
1262 };
1263
1264 /* v3.2b: i.MX53 */
1265 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1266 .preset = preset_v3,
1267 .send_cmd = send_cmd_v3,
1268 .send_addr = send_addr_v3,
1269 .send_page = send_page_v3,
1270 .send_read_id = send_read_id_v3,
1271 .get_dev_status = get_dev_status_v3,
1272 .check_int = check_int_v3,
1273 .irq_control = irq_control_v3,
1274 .get_ecc_status = get_ecc_status_v3,
1275 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1276 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1277 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1278 .select_chip = mxc_nand_select_chip_v1_v3,
1279 .correct_data = mxc_nand_correct_data_v2_v3,
1280 .irqpending_quirk = 0,
1281 .needs_ip = 1,
1282 .regs_offset = 0,
1283 .spare0_offset = 0x1000,
1284 .axi_offset = 0x1e00,
1285 .spare_len = 64,
1286 .eccbytes = 0,
1287 .eccsize = 0,
1288 .ppb_shift = 8,
1289 };
1290
1291 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1292 {
1293 return host->devtype_data == &imx21_nand_devtype_data;
1294 }
1295
1296 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1297 {
1298 return host->devtype_data == &imx27_nand_devtype_data;
1299 }
1300
1301 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1302 {
1303 return host->devtype_data == &imx25_nand_devtype_data;
1304 }
1305
1306 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1307 {
1308 return host->devtype_data == &imx51_nand_devtype_data;
1309 }
1310
1311 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1312 {
1313 return host->devtype_data == &imx53_nand_devtype_data;
1314 }
1315
1316 static struct platform_device_id mxcnd_devtype[] = {
1317 {
1318 .name = "imx21-nand",
1319 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1320 }, {
1321 .name = "imx27-nand",
1322 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1323 }, {
1324 .name = "imx25-nand",
1325 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1326 }, {
1327 .name = "imx51-nand",
1328 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1329 }, {
1330 .name = "imx53-nand",
1331 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1332 }, {
1333 /* sentinel */
1334 }
1335 };
1336 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1337
1338 #ifdef CONFIG_OF_MTD
1339 static const struct of_device_id mxcnd_dt_ids[] = {
1340 {
1341 .compatible = "fsl,imx21-nand",
1342 .data = &imx21_nand_devtype_data,
1343 }, {
1344 .compatible = "fsl,imx27-nand",
1345 .data = &imx27_nand_devtype_data,
1346 }, {
1347 .compatible = "fsl,imx25-nand",
1348 .data = &imx25_nand_devtype_data,
1349 }, {
1350 .compatible = "fsl,imx51-nand",
1351 .data = &imx51_nand_devtype_data,
1352 }, {
1353 .compatible = "fsl,imx53-nand",
1354 .data = &imx53_nand_devtype_data,
1355 },
1356 { /* sentinel */ }
1357 };
1358
1359 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1360 {
1361 struct device_node *np = host->dev->of_node;
1362 struct mxc_nand_platform_data *pdata = &host->pdata;
1363 const struct of_device_id *of_id =
1364 of_match_device(mxcnd_dt_ids, host->dev);
1365 int buswidth;
1366
1367 if (!np)
1368 return 1;
1369
1370 if (of_get_nand_ecc_mode(np) >= 0)
1371 pdata->hw_ecc = 1;
1372
1373 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1374
1375 buswidth = of_get_nand_bus_width(np);
1376 if (buswidth < 0)
1377 return buswidth;
1378
1379 pdata->width = buswidth / 8;
1380
1381 host->devtype_data = of_id->data;
1382
1383 return 0;
1384 }
1385 #else
1386 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1387 {
1388 return 1;
1389 }
1390 #endif
1391
1392 static int mxcnd_probe(struct platform_device *pdev)
1393 {
1394 struct nand_chip *this;
1395 struct mtd_info *mtd;
1396 struct mxc_nand_host *host;
1397 struct resource *res;
1398 int err = 0;
1399
1400 /* Allocate memory for MTD device structure and private data */
1401 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) +
1402 NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL);
1403 if (!host)
1404 return -ENOMEM;
1405
1406 host->data_buf = (uint8_t *)(host + 1);
1407
1408 host->dev = &pdev->dev;
1409 /* structures must be linked */
1410 this = &host->nand;
1411 mtd = &host->mtd;
1412 mtd->priv = this;
1413 mtd->owner = THIS_MODULE;
1414 mtd->dev.parent = &pdev->dev;
1415 mtd->name = DRIVER_NAME;
1416
1417 /* 50 us command delay time */
1418 this->chip_delay = 5;
1419
1420 this->priv = host;
1421 this->dev_ready = mxc_nand_dev_ready;
1422 this->cmdfunc = mxc_nand_command;
1423 this->read_byte = mxc_nand_read_byte;
1424 this->read_word = mxc_nand_read_word;
1425 this->write_buf = mxc_nand_write_buf;
1426 this->read_buf = mxc_nand_read_buf;
1427
1428 host->clk = devm_clk_get(&pdev->dev, NULL);
1429 if (IS_ERR(host->clk))
1430 return PTR_ERR(host->clk);
1431
1432 err = mxcnd_probe_dt(host);
1433 if (err > 0) {
1434 struct mxc_nand_platform_data *pdata =
1435 dev_get_platdata(&pdev->dev);
1436 if (pdata) {
1437 host->pdata = *pdata;
1438 host->devtype_data = (struct mxc_nand_devtype_data *)
1439 pdev->id_entry->driver_data;
1440 } else {
1441 err = -ENODEV;
1442 }
1443 }
1444 if (err < 0)
1445 return err;
1446
1447 if (host->devtype_data->needs_ip) {
1448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1449 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1450 if (IS_ERR(host->regs_ip))
1451 return PTR_ERR(host->regs_ip);
1452
1453 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1454 } else {
1455 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1456 }
1457
1458 host->base = devm_ioremap_resource(&pdev->dev, res);
1459 if (IS_ERR(host->base))
1460 return PTR_ERR(host->base);
1461
1462 host->main_area0 = host->base;
1463
1464 if (host->devtype_data->regs_offset)
1465 host->regs = host->base + host->devtype_data->regs_offset;
1466 host->spare0 = host->base + host->devtype_data->spare0_offset;
1467 if (host->devtype_data->axi_offset)
1468 host->regs_axi = host->base + host->devtype_data->axi_offset;
1469
1470 this->ecc.bytes = host->devtype_data->eccbytes;
1471 host->eccsize = host->devtype_data->eccsize;
1472
1473 this->select_chip = host->devtype_data->select_chip;
1474 this->ecc.size = 512;
1475 this->ecc.layout = host->devtype_data->ecclayout_512;
1476
1477 if (host->pdata.hw_ecc) {
1478 this->ecc.calculate = mxc_nand_calculate_ecc;
1479 this->ecc.hwctl = mxc_nand_enable_hwecc;
1480 this->ecc.correct = host->devtype_data->correct_data;
1481 this->ecc.mode = NAND_ECC_HW;
1482 } else {
1483 this->ecc.mode = NAND_ECC_SOFT;
1484 }
1485
1486 /* NAND bus width determines access functions used by upper layer */
1487 if (host->pdata.width == 2)
1488 this->options |= NAND_BUSWIDTH_16;
1489
1490 if (host->pdata.flash_bbt) {
1491 this->bbt_td = &bbt_main_descr;
1492 this->bbt_md = &bbt_mirror_descr;
1493 /* update flash based bbt */
1494 this->bbt_options |= NAND_BBT_USE_FLASH;
1495 }
1496
1497 init_completion(&host->op_completion);
1498
1499 host->irq = platform_get_irq(pdev, 0);
1500
1501 /*
1502 * Use host->devtype_data->irq_control() here instead of irq_control()
1503 * because we must not disable_irq_nosync without having requested the
1504 * irq.
1505 */
1506 host->devtype_data->irq_control(host, 0);
1507
1508 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1509 IRQF_DISABLED, DRIVER_NAME, host);
1510 if (err)
1511 return err;
1512
1513 clk_prepare_enable(host->clk);
1514 host->clk_act = 1;
1515
1516 /*
1517 * Now that we "own" the interrupt make sure the interrupt mask bit is
1518 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1519 * on this machine.
1520 */
1521 if (host->devtype_data->irqpending_quirk) {
1522 disable_irq_nosync(host->irq);
1523 host->devtype_data->irq_control(host, 1);
1524 }
1525
1526 /* first scan to find the device and get the page size */
1527 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1528 err = -ENXIO;
1529 goto escan;
1530 }
1531
1532 /* Call preset again, with correct writesize this time */
1533 host->devtype_data->preset(mtd);
1534
1535 if (mtd->writesize == 2048)
1536 this->ecc.layout = host->devtype_data->ecclayout_2k;
1537 else if (mtd->writesize == 4096)
1538 this->ecc.layout = host->devtype_data->ecclayout_4k;
1539
1540 if (this->ecc.mode == NAND_ECC_HW) {
1541 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1542 this->ecc.strength = 1;
1543 else
1544 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1545 }
1546
1547 /* second phase scan */
1548 if (nand_scan_tail(mtd)) {
1549 err = -ENXIO;
1550 goto escan;
1551 }
1552
1553 /* Register the partitions */
1554 mtd_device_parse_register(mtd, part_probes,
1555 &(struct mtd_part_parser_data){
1556 .of_node = pdev->dev.of_node,
1557 },
1558 host->pdata.parts,
1559 host->pdata.nr_parts);
1560
1561 platform_set_drvdata(pdev, host);
1562
1563 return 0;
1564
1565 escan:
1566 if (host->clk_act)
1567 clk_disable_unprepare(host->clk);
1568
1569 return err;
1570 }
1571
1572 static int mxcnd_remove(struct platform_device *pdev)
1573 {
1574 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1575
1576 nand_release(&host->mtd);
1577
1578 return 0;
1579 }
1580
1581 static struct platform_driver mxcnd_driver = {
1582 .driver = {
1583 .name = DRIVER_NAME,
1584 .owner = THIS_MODULE,
1585 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1586 },
1587 .id_table = mxcnd_devtype,
1588 .probe = mxcnd_probe,
1589 .remove = mxcnd_remove,
1590 };
1591 module_platform_driver(mxcnd_driver);
1592
1593 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1594 MODULE_DESCRIPTION("MXC NAND MTD driver");
1595 MODULE_LICENSE("GPL");
Linux with added FPC-III support