2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
12 * Your platform definition file should specify something like:
14 * static struct at91_can_data ek_can_data = {
15 * transceiver_switch = sam9263ek_transceiver_switch,
18 * at91_add_device_can(&ek_can_data);
22 #include <linux/clk.h>
23 #include <linux/errno.h>
24 #include <linux/if_arp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
31 #include <linux/platform_device.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
35 #include <linux/string.h>
36 #include <linux/types.h>
37 #include <linux/platform_data/atmel.h>
39 #include <linux/can/dev.h>
40 #include <linux/can/error.h>
41 #include <linux/can/led.h>
43 #define AT91_MB_MASK(i) ((1 << (i)) - 1)
45 /* Common registers */
60 /* Mailbox registers (0 <= i <= 15) */
61 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
62 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
63 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
64 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
65 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
66 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
67 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
68 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
71 #define AT91_MR_CANEN BIT(0)
72 #define AT91_MR_LPM BIT(1)
73 #define AT91_MR_ABM BIT(2)
74 #define AT91_MR_OVL BIT(3)
75 #define AT91_MR_TEOF BIT(4)
76 #define AT91_MR_TTM BIT(5)
77 #define AT91_MR_TIMFRZ BIT(6)
78 #define AT91_MR_DRPT BIT(7)
80 #define AT91_SR_RBSY BIT(29)
82 #define AT91_MMR_PRIO_SHIFT (16)
84 #define AT91_MID_MIDE BIT(29)
86 #define AT91_MSR_MRTR BIT(20)
87 #define AT91_MSR_MABT BIT(22)
88 #define AT91_MSR_MRDY BIT(23)
89 #define AT91_MSR_MMI BIT(24)
91 #define AT91_MCR_MRTR BIT(20)
92 #define AT91_MCR_MTCR BIT(23)
96 AT91_MB_MODE_DISABLED
= 0,
98 AT91_MB_MODE_RX_OVRWR
= 2,
100 AT91_MB_MODE_CONSUMER
= 4,
101 AT91_MB_MODE_PRODUCER
= 5,
104 /* Interrupt mask bits */
105 #define AT91_IRQ_ERRA (1 << 16)
106 #define AT91_IRQ_WARN (1 << 17)
107 #define AT91_IRQ_ERRP (1 << 18)
108 #define AT91_IRQ_BOFF (1 << 19)
109 #define AT91_IRQ_SLEEP (1 << 20)
110 #define AT91_IRQ_WAKEUP (1 << 21)
111 #define AT91_IRQ_TOVF (1 << 22)
112 #define AT91_IRQ_TSTP (1 << 23)
113 #define AT91_IRQ_CERR (1 << 24)
114 #define AT91_IRQ_SERR (1 << 25)
115 #define AT91_IRQ_AERR (1 << 26)
116 #define AT91_IRQ_FERR (1 << 27)
117 #define AT91_IRQ_BERR (1 << 28)
119 #define AT91_IRQ_ERR_ALL (0x1fff0000)
120 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
121 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
122 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
123 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
125 #define AT91_IRQ_ALL (0x1fffffff)
128 AT91_DEVTYPE_SAM9263
,
132 struct at91_devtype_data
{
133 unsigned int rx_first
;
134 unsigned int rx_split
;
135 unsigned int rx_last
;
136 unsigned int tx_shift
;
137 enum at91_devtype type
;
141 struct can_priv can
; /* must be the first member! */
142 struct net_device
*dev
;
143 struct napi_struct napi
;
145 void __iomem
*reg_base
;
148 unsigned int tx_next
;
149 unsigned int tx_echo
;
150 unsigned int rx_next
;
151 struct at91_devtype_data devtype_data
;
154 struct at91_can_data
*pdata
;
159 static const struct at91_devtype_data at91_at91sam9263_data
= {
164 .type
= AT91_DEVTYPE_SAM9263
,
167 static const struct at91_devtype_data at91_at91sam9x5_data
= {
172 .type
= AT91_DEVTYPE_SAM9X5
,
175 static const struct can_bittiming_const at91_bittiming_const
= {
176 .name
= KBUILD_MODNAME
,
187 #define AT91_IS(_model) \
188 static inline int at91_is_sam##_model(const struct at91_priv *priv) \
190 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
196 static inline unsigned int get_mb_rx_first(const struct at91_priv
*priv
)
198 return priv
->devtype_data
.rx_first
;
201 static inline unsigned int get_mb_rx_last(const struct at91_priv
*priv
)
203 return priv
->devtype_data
.rx_last
;
206 static inline unsigned int get_mb_rx_split(const struct at91_priv
*priv
)
208 return priv
->devtype_data
.rx_split
;
211 static inline unsigned int get_mb_rx_num(const struct at91_priv
*priv
)
213 return get_mb_rx_last(priv
) - get_mb_rx_first(priv
) + 1;
216 static inline unsigned int get_mb_rx_low_last(const struct at91_priv
*priv
)
218 return get_mb_rx_split(priv
) - 1;
221 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv
*priv
)
223 return AT91_MB_MASK(get_mb_rx_split(priv
)) &
224 ~AT91_MB_MASK(get_mb_rx_first(priv
));
227 static inline unsigned int get_mb_tx_shift(const struct at91_priv
*priv
)
229 return priv
->devtype_data
.tx_shift
;
232 static inline unsigned int get_mb_tx_num(const struct at91_priv
*priv
)
234 return 1 << get_mb_tx_shift(priv
);
237 static inline unsigned int get_mb_tx_first(const struct at91_priv
*priv
)
239 return get_mb_rx_last(priv
) + 1;
242 static inline unsigned int get_mb_tx_last(const struct at91_priv
*priv
)
244 return get_mb_tx_first(priv
) + get_mb_tx_num(priv
) - 1;
247 static inline unsigned int get_next_prio_shift(const struct at91_priv
*priv
)
249 return get_mb_tx_shift(priv
);
252 static inline unsigned int get_next_prio_mask(const struct at91_priv
*priv
)
254 return 0xf << get_mb_tx_shift(priv
);
257 static inline unsigned int get_next_mb_mask(const struct at91_priv
*priv
)
259 return AT91_MB_MASK(get_mb_tx_shift(priv
));
262 static inline unsigned int get_next_mask(const struct at91_priv
*priv
)
264 return get_next_mb_mask(priv
) | get_next_prio_mask(priv
);
267 static inline unsigned int get_irq_mb_rx(const struct at91_priv
*priv
)
269 return AT91_MB_MASK(get_mb_rx_last(priv
) + 1) &
270 ~AT91_MB_MASK(get_mb_rx_first(priv
));
273 static inline unsigned int get_irq_mb_tx(const struct at91_priv
*priv
)
275 return AT91_MB_MASK(get_mb_tx_last(priv
) + 1) &
276 ~AT91_MB_MASK(get_mb_tx_first(priv
));
279 static inline unsigned int get_tx_next_mb(const struct at91_priv
*priv
)
281 return (priv
->tx_next
& get_next_mb_mask(priv
)) + get_mb_tx_first(priv
);
284 static inline unsigned int get_tx_next_prio(const struct at91_priv
*priv
)
286 return (priv
->tx_next
>> get_next_prio_shift(priv
)) & 0xf;
289 static inline unsigned int get_tx_echo_mb(const struct at91_priv
*priv
)
291 return (priv
->tx_echo
& get_next_mb_mask(priv
)) + get_mb_tx_first(priv
);
294 static inline u32
at91_read(const struct at91_priv
*priv
, enum at91_reg reg
)
296 return __raw_readl(priv
->reg_base
+ reg
);
299 static inline void at91_write(const struct at91_priv
*priv
, enum at91_reg reg
,
302 __raw_writel(value
, priv
->reg_base
+ reg
);
305 static inline void set_mb_mode_prio(const struct at91_priv
*priv
,
306 unsigned int mb
, enum at91_mb_mode mode
, int prio
)
308 at91_write(priv
, AT91_MMR(mb
), (mode
<< 24) | (prio
<< 16));
311 static inline void set_mb_mode(const struct at91_priv
*priv
, unsigned int mb
,
312 enum at91_mb_mode mode
)
314 set_mb_mode_prio(priv
, mb
, mode
, 0);
317 static inline u32
at91_can_id_to_reg_mid(canid_t can_id
)
321 if (can_id
& CAN_EFF_FLAG
)
322 reg_mid
= (can_id
& CAN_EFF_MASK
) | AT91_MID_MIDE
;
324 reg_mid
= (can_id
& CAN_SFF_MASK
) << 18;
330 * Swtich transceiver on or off
332 static void at91_transceiver_switch(const struct at91_priv
*priv
, int on
)
334 if (priv
->pdata
&& priv
->pdata
->transceiver_switch
)
335 priv
->pdata
->transceiver_switch(on
);
338 static void at91_setup_mailboxes(struct net_device
*dev
)
340 struct at91_priv
*priv
= netdev_priv(dev
);
345 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
346 * mailbox is disabled. The next 11 mailboxes are used as a
347 * reception FIFO. The last mailbox is configured with
348 * overwrite option. The overwrite flag indicates a FIFO
351 reg_mid
= at91_can_id_to_reg_mid(priv
->mb0_id
);
352 for (i
= 0; i
< get_mb_rx_first(priv
); i
++) {
353 set_mb_mode(priv
, i
, AT91_MB_MODE_DISABLED
);
354 at91_write(priv
, AT91_MID(i
), reg_mid
);
355 at91_write(priv
, AT91_MCR(i
), 0x0); /* clear dlc */
358 for (i
= get_mb_rx_first(priv
); i
< get_mb_rx_last(priv
); i
++)
359 set_mb_mode(priv
, i
, AT91_MB_MODE_RX
);
360 set_mb_mode(priv
, get_mb_rx_last(priv
), AT91_MB_MODE_RX_OVRWR
);
362 /* reset acceptance mask and id register */
363 for (i
= get_mb_rx_first(priv
); i
<= get_mb_rx_last(priv
); i
++) {
364 at91_write(priv
, AT91_MAM(i
), 0x0);
365 at91_write(priv
, AT91_MID(i
), AT91_MID_MIDE
);
368 /* The last 4 mailboxes are used for transmitting. */
369 for (i
= get_mb_tx_first(priv
); i
<= get_mb_tx_last(priv
); i
++)
370 set_mb_mode_prio(priv
, i
, AT91_MB_MODE_TX
, 0);
372 /* Reset tx and rx helper pointers */
373 priv
->tx_next
= priv
->tx_echo
= 0;
374 priv
->rx_next
= get_mb_rx_first(priv
);
377 static int at91_set_bittiming(struct net_device
*dev
)
379 const struct at91_priv
*priv
= netdev_priv(dev
);
380 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
383 reg_br
= ((priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
) ? 1 << 24 : 0) |
384 ((bt
->brp
- 1) << 16) | ((bt
->sjw
- 1) << 12) |
385 ((bt
->prop_seg
- 1) << 8) | ((bt
->phase_seg1
- 1) << 4) |
386 ((bt
->phase_seg2
- 1) << 0);
388 netdev_info(dev
, "writing AT91_BR: 0x%08x\n", reg_br
);
390 at91_write(priv
, AT91_BR
, reg_br
);
395 static int at91_get_berr_counter(const struct net_device
*dev
,
396 struct can_berr_counter
*bec
)
398 const struct at91_priv
*priv
= netdev_priv(dev
);
399 u32 reg_ecr
= at91_read(priv
, AT91_ECR
);
401 bec
->rxerr
= reg_ecr
& 0xff;
402 bec
->txerr
= reg_ecr
>> 16;
407 static void at91_chip_start(struct net_device
*dev
)
409 struct at91_priv
*priv
= netdev_priv(dev
);
412 /* disable interrupts */
413 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
416 reg_mr
= at91_read(priv
, AT91_MR
);
417 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
419 at91_set_bittiming(dev
);
420 at91_setup_mailboxes(dev
);
421 at91_transceiver_switch(priv
, 1);
424 at91_write(priv
, AT91_MR
, AT91_MR_CANEN
);
426 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
428 /* Enable interrupts */
429 reg_ier
= get_irq_mb_rx(priv
) | AT91_IRQ_ERRP
| AT91_IRQ_ERR_FRAME
;
430 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
431 at91_write(priv
, AT91_IER
, reg_ier
);
434 static void at91_chip_stop(struct net_device
*dev
, enum can_state state
)
436 struct at91_priv
*priv
= netdev_priv(dev
);
439 /* disable interrupts */
440 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
442 reg_mr
= at91_read(priv
, AT91_MR
);
443 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
445 at91_transceiver_switch(priv
, 0);
446 priv
->can
.state
= state
;
450 * theory of operation:
452 * According to the datasheet priority 0 is the highest priority, 15
453 * is the lowest. If two mailboxes have the same priority level the
454 * message of the mailbox with the lowest number is sent first.
456 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
457 * the next mailbox with prio 0, and so on, until all mailboxes are
458 * used. Then we start from the beginning with mailbox
459 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
460 * prio 1. When we reach the last mailbox with prio 15, we have to
461 * stop sending, waiting for all messages to be delivered, then start
462 * again with mailbox AT91_MB_TX_FIRST prio 0.
464 * We use the priv->tx_next as counter for the next transmission
465 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
466 * encode the mailbox number, the upper 4 bits the mailbox priority:
468 * priv->tx_next = (prio << get_next_prio_shift(priv)) |
469 * (mb - get_mb_tx_first(priv));
472 static netdev_tx_t
at91_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
474 struct at91_priv
*priv
= netdev_priv(dev
);
475 struct net_device_stats
*stats
= &dev
->stats
;
476 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
477 unsigned int mb
, prio
;
478 u32 reg_mid
, reg_mcr
;
480 if (can_dropped_invalid_skb(dev
, skb
))
483 mb
= get_tx_next_mb(priv
);
484 prio
= get_tx_next_prio(priv
);
486 if (unlikely(!(at91_read(priv
, AT91_MSR(mb
)) & AT91_MSR_MRDY
))) {
487 netif_stop_queue(dev
);
489 netdev_err(dev
, "BUG! TX buffer full when queue awake!\n");
490 return NETDEV_TX_BUSY
;
492 reg_mid
= at91_can_id_to_reg_mid(cf
->can_id
);
493 reg_mcr
= ((cf
->can_id
& CAN_RTR_FLAG
) ? AT91_MCR_MRTR
: 0) |
494 (cf
->can_dlc
<< 16) | AT91_MCR_MTCR
;
496 /* disable MB while writing ID (see datasheet) */
497 set_mb_mode(priv
, mb
, AT91_MB_MODE_DISABLED
);
498 at91_write(priv
, AT91_MID(mb
), reg_mid
);
499 set_mb_mode_prio(priv
, mb
, AT91_MB_MODE_TX
, prio
);
501 at91_write(priv
, AT91_MDL(mb
), *(u32
*)(cf
->data
+ 0));
502 at91_write(priv
, AT91_MDH(mb
), *(u32
*)(cf
->data
+ 4));
504 /* This triggers transmission */
505 at91_write(priv
, AT91_MCR(mb
), reg_mcr
);
507 stats
->tx_bytes
+= cf
->can_dlc
;
509 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
510 can_put_echo_skb(skb
, dev
, mb
- get_mb_tx_first(priv
));
513 * we have to stop the queue and deliver all messages in case
514 * of a prio+mb counter wrap around. This is the case if
515 * tx_next buffer prio and mailbox equals 0.
517 * also stop the queue if next buffer is still in use
521 if (!(at91_read(priv
, AT91_MSR(get_tx_next_mb(priv
))) &
523 (priv
->tx_next
& get_next_mask(priv
)) == 0)
524 netif_stop_queue(dev
);
526 /* Enable interrupt for this mailbox */
527 at91_write(priv
, AT91_IER
, 1 << mb
);
533 * at91_activate_rx_low - activate lower rx mailboxes
536 * Reenables the lower mailboxes for reception of new CAN messages
538 static inline void at91_activate_rx_low(const struct at91_priv
*priv
)
540 u32 mask
= get_mb_rx_low_mask(priv
);
541 at91_write(priv
, AT91_TCR
, mask
);
545 * at91_activate_rx_mb - reactive single rx mailbox
547 * @mb: mailbox to reactivate
549 * Reenables given mailbox for reception of new CAN messages
551 static inline void at91_activate_rx_mb(const struct at91_priv
*priv
,
555 at91_write(priv
, AT91_TCR
, mask
);
559 * at91_rx_overflow_err - send error frame due to rx overflow
562 static void at91_rx_overflow_err(struct net_device
*dev
)
564 struct net_device_stats
*stats
= &dev
->stats
;
566 struct can_frame
*cf
;
568 netdev_dbg(dev
, "RX buffer overflow\n");
569 stats
->rx_over_errors
++;
572 skb
= alloc_can_err_skb(dev
, &cf
);
576 cf
->can_id
|= CAN_ERR_CRTL
;
577 cf
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
578 netif_receive_skb(skb
);
581 stats
->rx_bytes
+= cf
->can_dlc
;
585 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
587 * @mb: mailbox number to read from
588 * @cf: can frame where to store message
590 * Reads a CAN message from the given mailbox and stores data into
591 * given can frame. "mb" and "cf" must be valid.
593 static void at91_read_mb(struct net_device
*dev
, unsigned int mb
,
594 struct can_frame
*cf
)
596 const struct at91_priv
*priv
= netdev_priv(dev
);
597 u32 reg_msr
, reg_mid
;
599 reg_mid
= at91_read(priv
, AT91_MID(mb
));
600 if (reg_mid
& AT91_MID_MIDE
)
601 cf
->can_id
= ((reg_mid
>> 0) & CAN_EFF_MASK
) | CAN_EFF_FLAG
;
603 cf
->can_id
= (reg_mid
>> 18) & CAN_SFF_MASK
;
605 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
606 cf
->can_dlc
= get_can_dlc((reg_msr
>> 16) & 0xf);
608 if (reg_msr
& AT91_MSR_MRTR
)
609 cf
->can_id
|= CAN_RTR_FLAG
;
611 *(u32
*)(cf
->data
+ 0) = at91_read(priv
, AT91_MDL(mb
));
612 *(u32
*)(cf
->data
+ 4) = at91_read(priv
, AT91_MDH(mb
));
615 /* allow RX of extended frames */
616 at91_write(priv
, AT91_MID(mb
), AT91_MID_MIDE
);
618 if (unlikely(mb
== get_mb_rx_last(priv
) && reg_msr
& AT91_MSR_MMI
))
619 at91_rx_overflow_err(dev
);
623 * at91_read_msg - read CAN message from mailbox
625 * @mb: mail box to read from
627 * Reads a CAN message from given mailbox, and put into linux network
628 * RX queue, does all housekeeping chores (stats, ...)
630 static void at91_read_msg(struct net_device
*dev
, unsigned int mb
)
632 struct net_device_stats
*stats
= &dev
->stats
;
633 struct can_frame
*cf
;
636 skb
= alloc_can_skb(dev
, &cf
);
637 if (unlikely(!skb
)) {
642 at91_read_mb(dev
, mb
, cf
);
643 netif_receive_skb(skb
);
646 stats
->rx_bytes
+= cf
->can_dlc
;
648 can_led_event(dev
, CAN_LED_EVENT_RX
);
652 * at91_poll_rx - read multiple CAN messages from mailboxes
654 * @quota: max number of pkgs we're allowed to receive
656 * Theory of Operation:
658 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
659 * on the chip are reserved for RX. We split them into 2 groups. The
660 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
662 * Like it or not, but the chip always saves a received CAN message
663 * into the first free mailbox it finds (starting with the
664 * lowest). This makes it very difficult to read the messages in the
665 * right order from the chip. This is how we work around that problem:
667 * The first message goes into mb nr. 1 and issues an interrupt. All
668 * rx ints are disabled in the interrupt handler and a napi poll is
669 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
670 * receive another message).
675 * +-+-+-+-+-+-+-+-++-+-+-+-+
676 * | |x|x|x|x|x|x|x|| | | | |
677 * +-+-+-+-+-+-+-+-++-+-+-+-+
678 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
679 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
683 * unused, due to chip bug
685 * The variable priv->rx_next points to the next mailbox to read a
686 * message from. As long we're in the lower mailboxes we just read the
687 * mailbox but not reenable it.
689 * With completion of the last of the lower mailboxes, we reenable the
690 * whole first group, but continue to look for filled mailboxes in the
691 * upper mailboxes. Imagine the second group like overflow mailboxes,
692 * which takes CAN messages if the lower goup is full. While in the
693 * upper group we reenable the mailbox right after reading it. Giving
694 * the chip more room to store messages.
696 * After finishing we look again in the lower group if we've still
700 static int at91_poll_rx(struct net_device
*dev
, int quota
)
702 struct at91_priv
*priv
= netdev_priv(dev
);
703 u32 reg_sr
= at91_read(priv
, AT91_SR
);
704 const unsigned long *addr
= (unsigned long *)®_sr
;
708 if (priv
->rx_next
> get_mb_rx_low_last(priv
) &&
709 reg_sr
& get_mb_rx_low_mask(priv
))
711 "order of incoming frames cannot be guaranteed\n");
714 for (mb
= find_next_bit(addr
, get_mb_tx_first(priv
), priv
->rx_next
);
715 mb
< get_mb_tx_first(priv
) && quota
> 0;
716 reg_sr
= at91_read(priv
, AT91_SR
),
717 mb
= find_next_bit(addr
, get_mb_tx_first(priv
), ++priv
->rx_next
)) {
718 at91_read_msg(dev
, mb
);
720 /* reactivate mailboxes */
721 if (mb
== get_mb_rx_low_last(priv
))
722 /* all lower mailboxed, if just finished it */
723 at91_activate_rx_low(priv
);
724 else if (mb
> get_mb_rx_low_last(priv
))
725 /* only the mailbox we read */
726 at91_activate_rx_mb(priv
, mb
);
732 /* upper group completed, look again in lower */
733 if (priv
->rx_next
> get_mb_rx_low_last(priv
) &&
734 mb
> get_mb_rx_last(priv
)) {
735 priv
->rx_next
= get_mb_rx_first(priv
);
743 static void at91_poll_err_frame(struct net_device
*dev
,
744 struct can_frame
*cf
, u32 reg_sr
)
746 struct at91_priv
*priv
= netdev_priv(dev
);
749 if (reg_sr
& AT91_IRQ_CERR
) {
750 netdev_dbg(dev
, "CERR irq\n");
751 dev
->stats
.rx_errors
++;
752 priv
->can
.can_stats
.bus_error
++;
753 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
757 if (reg_sr
& AT91_IRQ_SERR
) {
758 netdev_dbg(dev
, "SERR irq\n");
759 dev
->stats
.rx_errors
++;
760 priv
->can
.can_stats
.bus_error
++;
761 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
762 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
765 /* Acknowledgement Error */
766 if (reg_sr
& AT91_IRQ_AERR
) {
767 netdev_dbg(dev
, "AERR irq\n");
768 dev
->stats
.tx_errors
++;
769 cf
->can_id
|= CAN_ERR_ACK
;
773 if (reg_sr
& AT91_IRQ_FERR
) {
774 netdev_dbg(dev
, "FERR irq\n");
775 dev
->stats
.rx_errors
++;
776 priv
->can
.can_stats
.bus_error
++;
777 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
778 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
782 if (reg_sr
& AT91_IRQ_BERR
) {
783 netdev_dbg(dev
, "BERR irq\n");
784 dev
->stats
.tx_errors
++;
785 priv
->can
.can_stats
.bus_error
++;
786 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
787 cf
->data
[2] |= CAN_ERR_PROT_BIT
;
791 static int at91_poll_err(struct net_device
*dev
, int quota
, u32 reg_sr
)
794 struct can_frame
*cf
;
799 skb
= alloc_can_err_skb(dev
, &cf
);
803 at91_poll_err_frame(dev
, cf
, reg_sr
);
804 netif_receive_skb(skb
);
806 dev
->stats
.rx_packets
++;
807 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
812 static int at91_poll(struct napi_struct
*napi
, int quota
)
814 struct net_device
*dev
= napi
->dev
;
815 const struct at91_priv
*priv
= netdev_priv(dev
);
816 u32 reg_sr
= at91_read(priv
, AT91_SR
);
819 if (reg_sr
& get_irq_mb_rx(priv
))
820 work_done
+= at91_poll_rx(dev
, quota
- work_done
);
823 * The error bits are clear on read,
824 * so use saved value from irq handler.
826 reg_sr
|= priv
->reg_sr
;
827 if (reg_sr
& AT91_IRQ_ERR_FRAME
)
828 work_done
+= at91_poll_err(dev
, quota
- work_done
, reg_sr
);
830 if (work_done
< quota
) {
831 /* enable IRQs for frame errors and all mailboxes >= rx_next */
832 u32 reg_ier
= AT91_IRQ_ERR_FRAME
;
833 reg_ier
|= get_irq_mb_rx(priv
) & ~AT91_MB_MASK(priv
->rx_next
);
836 at91_write(priv
, AT91_IER
, reg_ier
);
843 * theory of operation:
845 * priv->tx_echo holds the number of the oldest can_frame put for
846 * transmission into the hardware, but not yet ACKed by the CAN tx
849 * We iterate from priv->tx_echo to priv->tx_next and check if the
850 * packet has been transmitted, echo it back to the CAN framework. If
851 * we discover a not yet transmitted package, stop looking for more.
854 static void at91_irq_tx(struct net_device
*dev
, u32 reg_sr
)
856 struct at91_priv
*priv
= netdev_priv(dev
);
860 /* masking of reg_sr not needed, already done by at91_irq */
862 for (/* nix */; (priv
->tx_next
- priv
->tx_echo
) > 0; priv
->tx_echo
++) {
863 mb
= get_tx_echo_mb(priv
);
865 /* no event in mailbox? */
866 if (!(reg_sr
& (1 << mb
)))
869 /* Disable irq for this TX mailbox */
870 at91_write(priv
, AT91_IDR
, 1 << mb
);
873 * only echo if mailbox signals us a transfer
874 * complete (MSR_MRDY). Otherwise it's a tansfer
875 * abort. "can_bus_off()" takes care about the skbs
876 * parked in the echo queue.
878 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
879 if (likely(reg_msr
& AT91_MSR_MRDY
&&
880 ~reg_msr
& AT91_MSR_MABT
)) {
881 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
882 can_get_echo_skb(dev
, mb
- get_mb_tx_first(priv
));
883 dev
->stats
.tx_packets
++;
884 can_led_event(dev
, CAN_LED_EVENT_TX
);
889 * restart queue if we don't have a wrap around but restart if
890 * we get a TX int for the last can frame directly before a
893 if ((priv
->tx_next
& get_next_mask(priv
)) != 0 ||
894 (priv
->tx_echo
& get_next_mask(priv
)) == 0)
895 netif_wake_queue(dev
);
898 static void at91_irq_err_state(struct net_device
*dev
,
899 struct can_frame
*cf
, enum can_state new_state
)
901 struct at91_priv
*priv
= netdev_priv(dev
);
902 u32 reg_idr
= 0, reg_ier
= 0;
903 struct can_berr_counter bec
;
905 at91_get_berr_counter(dev
, &bec
);
907 switch (priv
->can
.state
) {
908 case CAN_STATE_ERROR_ACTIVE
:
911 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
912 * => : there was a warning int
914 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
915 new_state
<= CAN_STATE_BUS_OFF
) {
916 netdev_dbg(dev
, "Error Warning IRQ\n");
917 priv
->can
.can_stats
.error_warning
++;
919 cf
->can_id
|= CAN_ERR_CRTL
;
920 cf
->data
[1] = (bec
.txerr
> bec
.rxerr
) ?
921 CAN_ERR_CRTL_TX_WARNING
:
922 CAN_ERR_CRTL_RX_WARNING
;
924 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
926 * from: ERROR_ACTIVE, ERROR_WARNING
927 * to : ERROR_PASSIVE, BUS_OFF
928 * => : error passive int
930 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
931 new_state
<= CAN_STATE_BUS_OFF
) {
932 netdev_dbg(dev
, "Error Passive IRQ\n");
933 priv
->can
.can_stats
.error_passive
++;
935 cf
->can_id
|= CAN_ERR_CRTL
;
936 cf
->data
[1] = (bec
.txerr
> bec
.rxerr
) ?
937 CAN_ERR_CRTL_TX_PASSIVE
:
938 CAN_ERR_CRTL_RX_PASSIVE
;
941 case CAN_STATE_BUS_OFF
:
944 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
946 if (new_state
<= CAN_STATE_ERROR_PASSIVE
) {
947 cf
->can_id
|= CAN_ERR_RESTARTED
;
949 netdev_dbg(dev
, "restarted\n");
950 priv
->can
.can_stats
.restarts
++;
952 netif_carrier_on(dev
);
953 netif_wake_queue(dev
);
961 /* process state changes depending on the new state */
963 case CAN_STATE_ERROR_ACTIVE
:
965 * actually we want to enable AT91_IRQ_WARN here, but
966 * it screws up the system under certain
967 * circumstances. so just enable AT91_IRQ_ERRP, thus
970 netdev_dbg(dev
, "Error Active\n");
971 cf
->can_id
|= CAN_ERR_PROT
;
972 cf
->data
[2] = CAN_ERR_PROT_ACTIVE
;
973 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
974 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
975 reg_ier
= AT91_IRQ_ERRP
;
977 case CAN_STATE_ERROR_PASSIVE
:
978 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_ERRP
;
979 reg_ier
= AT91_IRQ_BOFF
;
981 case CAN_STATE_BUS_OFF
:
982 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_ERRP
|
983 AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
986 cf
->can_id
|= CAN_ERR_BUSOFF
;
988 netdev_dbg(dev
, "bus-off\n");
989 netif_carrier_off(dev
);
990 priv
->can
.can_stats
.bus_off
++;
992 /* turn off chip, if restart is disabled */
993 if (!priv
->can
.restart_ms
) {
994 at91_chip_stop(dev
, CAN_STATE_BUS_OFF
);
1002 at91_write(priv
, AT91_IDR
, reg_idr
);
1003 at91_write(priv
, AT91_IER
, reg_ier
);
1006 static int at91_get_state_by_bec(const struct net_device
*dev
,
1007 enum can_state
*state
)
1009 struct can_berr_counter bec
;
1012 err
= at91_get_berr_counter(dev
, &bec
);
1016 if (bec
.txerr
< 96 && bec
.rxerr
< 96)
1017 *state
= CAN_STATE_ERROR_ACTIVE
;
1018 else if (bec
.txerr
< 128 && bec
.rxerr
< 128)
1019 *state
= CAN_STATE_ERROR_WARNING
;
1020 else if (bec
.txerr
< 256 && bec
.rxerr
< 256)
1021 *state
= CAN_STATE_ERROR_PASSIVE
;
1023 *state
= CAN_STATE_BUS_OFF
;
1029 static void at91_irq_err(struct net_device
*dev
)
1031 struct at91_priv
*priv
= netdev_priv(dev
);
1032 struct sk_buff
*skb
;
1033 struct can_frame
*cf
;
1034 enum can_state new_state
;
1038 if (at91_is_sam9263(priv
)) {
1039 reg_sr
= at91_read(priv
, AT91_SR
);
1041 /* we need to look at the unmasked reg_sr */
1042 if (unlikely(reg_sr
& AT91_IRQ_BOFF
))
1043 new_state
= CAN_STATE_BUS_OFF
;
1044 else if (unlikely(reg_sr
& AT91_IRQ_ERRP
))
1045 new_state
= CAN_STATE_ERROR_PASSIVE
;
1046 else if (unlikely(reg_sr
& AT91_IRQ_WARN
))
1047 new_state
= CAN_STATE_ERROR_WARNING
;
1048 else if (likely(reg_sr
& AT91_IRQ_ERRA
))
1049 new_state
= CAN_STATE_ERROR_ACTIVE
;
1051 netdev_err(dev
, "BUG! hardware in undefined state\n");
1055 err
= at91_get_state_by_bec(dev
, &new_state
);
1060 /* state hasn't changed */
1061 if (likely(new_state
== priv
->can
.state
))
1064 skb
= alloc_can_err_skb(dev
, &cf
);
1068 at91_irq_err_state(dev
, cf
, new_state
);
1071 dev
->stats
.rx_packets
++;
1072 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
1074 priv
->can
.state
= new_state
;
1080 static irqreturn_t
at91_irq(int irq
, void *dev_id
)
1082 struct net_device
*dev
= dev_id
;
1083 struct at91_priv
*priv
= netdev_priv(dev
);
1084 irqreturn_t handled
= IRQ_NONE
;
1085 u32 reg_sr
, reg_imr
;
1087 reg_sr
= at91_read(priv
, AT91_SR
);
1088 reg_imr
= at91_read(priv
, AT91_IMR
);
1090 /* Ignore masked interrupts */
1095 handled
= IRQ_HANDLED
;
1097 /* Receive or error interrupt? -> napi */
1098 if (reg_sr
& (get_irq_mb_rx(priv
) | AT91_IRQ_ERR_FRAME
)) {
1100 * The error bits are clear on read,
1101 * save for later use.
1103 priv
->reg_sr
= reg_sr
;
1104 at91_write(priv
, AT91_IDR
,
1105 get_irq_mb_rx(priv
) | AT91_IRQ_ERR_FRAME
);
1106 napi_schedule(&priv
->napi
);
1109 /* Transmission complete interrupt */
1110 if (reg_sr
& get_irq_mb_tx(priv
))
1111 at91_irq_tx(dev
, reg_sr
);
1119 static int at91_open(struct net_device
*dev
)
1121 struct at91_priv
*priv
= netdev_priv(dev
);
1124 clk_enable(priv
->clk
);
1126 /* check or determine and set bittime */
1127 err
= open_candev(dev
);
1131 /* register interrupt handler */
1132 if (request_irq(dev
->irq
, at91_irq
, IRQF_SHARED
,
1138 can_led_event(dev
, CAN_LED_EVENT_OPEN
);
1140 /* start chip and queuing */
1141 at91_chip_start(dev
);
1142 napi_enable(&priv
->napi
);
1143 netif_start_queue(dev
);
1150 clk_disable(priv
->clk
);
1156 * stop CAN bus activity
1158 static int at91_close(struct net_device
*dev
)
1160 struct at91_priv
*priv
= netdev_priv(dev
);
1162 netif_stop_queue(dev
);
1163 napi_disable(&priv
->napi
);
1164 at91_chip_stop(dev
, CAN_STATE_STOPPED
);
1166 free_irq(dev
->irq
, dev
);
1167 clk_disable(priv
->clk
);
1171 can_led_event(dev
, CAN_LED_EVENT_STOP
);
1176 static int at91_set_mode(struct net_device
*dev
, enum can_mode mode
)
1179 case CAN_MODE_START
:
1180 at91_chip_start(dev
);
1181 netif_wake_queue(dev
);
1191 static const struct net_device_ops at91_netdev_ops
= {
1192 .ndo_open
= at91_open
,
1193 .ndo_stop
= at91_close
,
1194 .ndo_start_xmit
= at91_start_xmit
,
1197 static ssize_t
at91_sysfs_show_mb0_id(struct device
*dev
,
1198 struct device_attribute
*attr
, char *buf
)
1200 struct at91_priv
*priv
= netdev_priv(to_net_dev(dev
));
1202 if (priv
->mb0_id
& CAN_EFF_FLAG
)
1203 return snprintf(buf
, PAGE_SIZE
, "0x%08x\n", priv
->mb0_id
);
1205 return snprintf(buf
, PAGE_SIZE
, "0x%03x\n", priv
->mb0_id
);
1208 static ssize_t
at91_sysfs_set_mb0_id(struct device
*dev
,
1209 struct device_attribute
*attr
, const char *buf
, size_t count
)
1211 struct net_device
*ndev
= to_net_dev(dev
);
1212 struct at91_priv
*priv
= netdev_priv(ndev
);
1213 unsigned long can_id
;
1219 if (ndev
->flags
& IFF_UP
) {
1224 err
= kstrtoul(buf
, 0, &can_id
);
1230 if (can_id
& CAN_EFF_FLAG
)
1231 can_id
&= CAN_EFF_MASK
| CAN_EFF_FLAG
;
1233 can_id
&= CAN_SFF_MASK
;
1235 priv
->mb0_id
= can_id
;
1243 static DEVICE_ATTR(mb0_id
, S_IWUSR
| S_IRUGO
,
1244 at91_sysfs_show_mb0_id
, at91_sysfs_set_mb0_id
);
1246 static struct attribute
*at91_sysfs_attrs
[] = {
1247 &dev_attr_mb0_id
.attr
,
1251 static struct attribute_group at91_sysfs_attr_group
= {
1252 .attrs
= at91_sysfs_attrs
,
1255 #if defined(CONFIG_OF)
1256 static const struct of_device_id at91_can_dt_ids
[] = {
1258 .compatible
= "atmel,at91sam9x5-can",
1259 .data
= &at91_at91sam9x5_data
,
1261 .compatible
= "atmel,at91sam9263-can",
1262 .data
= &at91_at91sam9263_data
,
1267 MODULE_DEVICE_TABLE(of
, at91_can_dt_ids
);
1270 static const struct at91_devtype_data
*at91_can_get_driver_data(struct platform_device
*pdev
)
1272 if (pdev
->dev
.of_node
) {
1273 const struct of_device_id
*match
;
1275 match
= of_match_node(at91_can_dt_ids
, pdev
->dev
.of_node
);
1277 dev_err(&pdev
->dev
, "no matching node found in dtb\n");
1280 return (const struct at91_devtype_data
*)match
->data
;
1282 return (const struct at91_devtype_data
*)
1283 platform_get_device_id(pdev
)->driver_data
;
1286 static int at91_can_probe(struct platform_device
*pdev
)
1288 const struct at91_devtype_data
*devtype_data
;
1289 struct net_device
*dev
;
1290 struct at91_priv
*priv
;
1291 struct resource
*res
;
1296 devtype_data
= at91_can_get_driver_data(pdev
);
1297 if (!devtype_data
) {
1298 dev_err(&pdev
->dev
, "no driver data\n");
1303 clk
= clk_get(&pdev
->dev
, "can_clk");
1305 dev_err(&pdev
->dev
, "no clock defined\n");
1310 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1311 irq
= platform_get_irq(pdev
, 0);
1312 if (!res
|| irq
<= 0) {
1317 if (!request_mem_region(res
->start
,
1324 addr
= ioremap_nocache(res
->start
, resource_size(res
));
1330 dev
= alloc_candev(sizeof(struct at91_priv
),
1331 1 << devtype_data
->tx_shift
);
1337 dev
->netdev_ops
= &at91_netdev_ops
;
1339 dev
->flags
|= IFF_ECHO
;
1341 priv
= netdev_priv(dev
);
1342 priv
->can
.clock
.freq
= clk_get_rate(clk
);
1343 priv
->can
.bittiming_const
= &at91_bittiming_const
;
1344 priv
->can
.do_set_mode
= at91_set_mode
;
1345 priv
->can
.do_get_berr_counter
= at91_get_berr_counter
;
1346 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
;
1348 priv
->reg_base
= addr
;
1349 priv
->devtype_data
= *devtype_data
;
1351 priv
->pdata
= pdev
->dev
.platform_data
;
1352 priv
->mb0_id
= 0x7ff;
1354 netif_napi_add(dev
, &priv
->napi
, at91_poll
, get_mb_rx_num(priv
));
1356 if (at91_is_sam9263(priv
))
1357 dev
->sysfs_groups
[0] = &at91_sysfs_attr_group
;
1359 platform_set_drvdata(pdev
, dev
);
1360 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1362 err
= register_candev(dev
);
1364 dev_err(&pdev
->dev
, "registering netdev failed\n");
1368 devm_can_led_init(dev
);
1370 dev_info(&pdev
->dev
, "device registered (reg_base=%p, irq=%d)\n",
1371 priv
->reg_base
, dev
->irq
);
1380 release_mem_region(res
->start
, resource_size(res
));
1387 static int at91_can_remove(struct platform_device
*pdev
)
1389 struct net_device
*dev
= platform_get_drvdata(pdev
);
1390 struct at91_priv
*priv
= netdev_priv(dev
);
1391 struct resource
*res
;
1393 unregister_netdev(dev
);
1395 iounmap(priv
->reg_base
);
1397 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1398 release_mem_region(res
->start
, resource_size(res
));
1407 static const struct platform_device_id at91_can_id_table
[] = {
1409 .name
= "at91sam9x5_can",
1410 .driver_data
= (kernel_ulong_t
)&at91_at91sam9x5_data
,
1413 .driver_data
= (kernel_ulong_t
)&at91_at91sam9263_data
,
1418 MODULE_DEVICE_TABLE(platform
, at91_can_id_table
);
1420 static struct platform_driver at91_can_driver
= {
1421 .probe
= at91_can_probe
,
1422 .remove
= at91_can_remove
,
1424 .name
= KBUILD_MODNAME
,
1425 .owner
= THIS_MODULE
,
1426 .of_match_table
= of_match_ptr(at91_can_dt_ids
),
1428 .id_table
= at91_can_id_table
,
1431 module_platform_driver(at91_can_driver
);
1433 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1434 MODULE_LICENSE("GPL v2");
1435 MODULE_DESCRIPTION(KBUILD_MODNAME
" CAN netdevice driver");