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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / net / can / flexcan.c
blob57536e935fb9a78c4e09ba9d4872b80c24608d6a
1 /*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
40
41 #define DRV_NAME "flexcan"
42
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95 /* FLEXCAN error and status register (ESR) bits */
96 #define FLEXCAN_ESR_TWRN_INT BIT(17)
97 #define FLEXCAN_ESR_RWRN_INT BIT(16)
98 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
99 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
100 #define FLEXCAN_ESR_ACK_ERR BIT(13)
101 #define FLEXCAN_ESR_CRC_ERR BIT(12)
102 #define FLEXCAN_ESR_FRM_ERR BIT(11)
103 #define FLEXCAN_ESR_STF_ERR BIT(10)
104 #define FLEXCAN_ESR_TX_WRN BIT(9)
105 #define FLEXCAN_ESR_RX_WRN BIT(8)
106 #define FLEXCAN_ESR_IDLE BIT(7)
107 #define FLEXCAN_ESR_TXRX BIT(6)
108 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112 #define FLEXCAN_ESR_BOFF_INT BIT(2)
113 #define FLEXCAN_ESR_ERR_INT BIT(1)
114 #define FLEXCAN_ESR_WAK_INT BIT(0)
115 #define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119 #define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121 #define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
123 #define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
126
127 /* FLEXCAN interrupt flag register (IFLAG) bits */
128 #define FLEXCAN_TX_BUF_ID 8
129 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
130 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133 #define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136
137 /* FLEXCAN message buffers */
138 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139 #define FLEXCAN_MB_CNT_SRR BIT(22)
140 #define FLEXCAN_MB_CNT_IDE BIT(21)
141 #define FLEXCAN_MB_CNT_RTR BIT(20)
142 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
144
145 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
146
147 #define FLEXCAN_TIMEOUT_US (50)
148
149 /*
150 * FLEXCAN hardware feature flags
151 *
152 * Below is some version info we got:
153 * SOC Version IP-Version Glitch- [TR]WRN_INT
154 * Filter? connected?
155 * MX25 FlexCAN2 03.00.00.00 no no
156 * MX28 FlexCAN2 03.00.04.00 yes yes
157 * MX35 FlexCAN2 03.00.00.00 no no
158 * MX53 FlexCAN2 03.00.00.00 yes no
159 * MX6s FlexCAN3 10.00.12.00 yes yes
160 *
161 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
162 */
163 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
164 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
165
166 /* Structure of the message buffer */
167 struct flexcan_mb {
168 u32 can_ctrl;
169 u32 can_id;
170 u32 data[2];
171 };
172
173 /* Structure of the hardware registers */
174 struct flexcan_regs {
175 u32 mcr; /* 0x00 */
176 u32 ctrl; /* 0x04 */
177 u32 timer; /* 0x08 */
178 u32 _reserved1; /* 0x0c */
179 u32 rxgmask; /* 0x10 */
180 u32 rx14mask; /* 0x14 */
181 u32 rx15mask; /* 0x18 */
182 u32 ecr; /* 0x1c */
183 u32 esr; /* 0x20 */
184 u32 imask2; /* 0x24 */
185 u32 imask1; /* 0x28 */
186 u32 iflag2; /* 0x2c */
187 u32 iflag1; /* 0x30 */
188 u32 crl2; /* 0x34 */
189 u32 esr2; /* 0x38 */
190 u32 imeur; /* 0x3c */
191 u32 lrfr; /* 0x40 */
192 u32 crcr; /* 0x44 */
193 u32 rxfgmask; /* 0x48 */
194 u32 rxfir; /* 0x4c */
195 u32 _reserved3[12];
196 struct flexcan_mb cantxfg[64];
197 };
198
199 struct flexcan_devtype_data {
200 u32 features; /* hardware controller features */
201 };
202
203 struct flexcan_priv {
204 struct can_priv can;
205 struct net_device *dev;
206 struct napi_struct napi;
207
208 void __iomem *base;
209 u32 reg_esr;
210 u32 reg_ctrl_default;
211
212 struct clk *clk_ipg;
213 struct clk *clk_per;
214 struct flexcan_platform_data *pdata;
215 const struct flexcan_devtype_data *devtype_data;
216 struct regulator *reg_xceiver;
217 };
218
219 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
220 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
221 };
222 static struct flexcan_devtype_data fsl_imx28_devtype_data;
223 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
224 .features = FLEXCAN_HAS_V10_FEATURES,
225 };
226
227 static const struct can_bittiming_const flexcan_bittiming_const = {
228 .name = DRV_NAME,
229 .tseg1_min = 4,
230 .tseg1_max = 16,
231 .tseg2_min = 2,
232 .tseg2_max = 8,
233 .sjw_max = 4,
234 .brp_min = 1,
235 .brp_max = 256,
236 .brp_inc = 1,
237 };
238
239 /*
240 * Abstract off the read/write for arm versus ppc.
241 */
242 #if defined(__BIG_ENDIAN)
243 static inline u32 flexcan_read(void __iomem *addr)
244 {
245 return in_be32(addr);
246 }
247
248 static inline void flexcan_write(u32 val, void __iomem *addr)
249 {
250 out_be32(addr, val);
251 }
252 #else
253 static inline u32 flexcan_read(void __iomem *addr)
254 {
255 return readl(addr);
256 }
257
258 static inline void flexcan_write(u32 val, void __iomem *addr)
259 {
260 writel(val, addr);
261 }
262 #endif
263
264 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
265 {
266 if (!priv->reg_xceiver)
267 return 0;
268
269 return regulator_enable(priv->reg_xceiver);
270 }
271
272 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
273 {
274 if (!priv->reg_xceiver)
275 return 0;
276
277 return regulator_disable(priv->reg_xceiver);
278 }
279
280 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
281 u32 reg_esr)
282 {
283 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
284 (reg_esr & FLEXCAN_ESR_ERR_BUS);
285 }
286
287 static int flexcan_chip_enable(struct flexcan_priv *priv)
288 {
289 struct flexcan_regs __iomem *regs = priv->base;
290 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
291 u32 reg;
292
293 reg = flexcan_read(&regs->mcr);
294 reg &= ~FLEXCAN_MCR_MDIS;
295 flexcan_write(reg, &regs->mcr);
296
297 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
298 usleep_range(10, 20);
299
300 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
301 return -ETIMEDOUT;
302
303 return 0;
304 }
305
306 static int flexcan_chip_disable(struct flexcan_priv *priv)
307 {
308 struct flexcan_regs __iomem *regs = priv->base;
309 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
310 u32 reg;
311
312 reg = flexcan_read(&regs->mcr);
313 reg |= FLEXCAN_MCR_MDIS;
314 flexcan_write(reg, &regs->mcr);
315
316 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
317 usleep_range(10, 20);
318
319 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
320 return -ETIMEDOUT;
321
322 return 0;
323 }
324
325 static int flexcan_get_berr_counter(const struct net_device *dev,
326 struct can_berr_counter *bec)
327 {
328 const struct flexcan_priv *priv = netdev_priv(dev);
329 struct flexcan_regs __iomem *regs = priv->base;
330 u32 reg = flexcan_read(&regs->ecr);
331
332 bec->txerr = (reg >> 0) & 0xff;
333 bec->rxerr = (reg >> 8) & 0xff;
334
335 return 0;
336 }
337
338 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
339 {
340 const struct flexcan_priv *priv = netdev_priv(dev);
341 struct flexcan_regs __iomem *regs = priv->base;
342 struct can_frame *cf = (struct can_frame *)skb->data;
343 u32 can_id;
344 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
345
346 if (can_dropped_invalid_skb(dev, skb))
347 return NETDEV_TX_OK;
348
349 netif_stop_queue(dev);
350
351 if (cf->can_id & CAN_EFF_FLAG) {
352 can_id = cf->can_id & CAN_EFF_MASK;
353 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
354 } else {
355 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
356 }
357
358 if (cf->can_id & CAN_RTR_FLAG)
359 ctrl |= FLEXCAN_MB_CNT_RTR;
360
361 if (cf->can_dlc > 0) {
362 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
363 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
364 }
365 if (cf->can_dlc > 3) {
366 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
367 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
368 }
369
370 can_put_echo_skb(skb, dev, 0);
371
372 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
373 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
374
375 return NETDEV_TX_OK;
376 }
377
378 static void do_bus_err(struct net_device *dev,
379 struct can_frame *cf, u32 reg_esr)
380 {
381 struct flexcan_priv *priv = netdev_priv(dev);
382 int rx_errors = 0, tx_errors = 0;
383
384 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
385
386 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
387 netdev_dbg(dev, "BIT1_ERR irq\n");
388 cf->data[2] |= CAN_ERR_PROT_BIT1;
389 tx_errors = 1;
390 }
391 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
392 netdev_dbg(dev, "BIT0_ERR irq\n");
393 cf->data[2] |= CAN_ERR_PROT_BIT0;
394 tx_errors = 1;
395 }
396 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
397 netdev_dbg(dev, "ACK_ERR irq\n");
398 cf->can_id |= CAN_ERR_ACK;
399 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
400 tx_errors = 1;
401 }
402 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
403 netdev_dbg(dev, "CRC_ERR irq\n");
404 cf->data[2] |= CAN_ERR_PROT_BIT;
405 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
406 rx_errors = 1;
407 }
408 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
409 netdev_dbg(dev, "FRM_ERR irq\n");
410 cf->data[2] |= CAN_ERR_PROT_FORM;
411 rx_errors = 1;
412 }
413 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
414 netdev_dbg(dev, "STF_ERR irq\n");
415 cf->data[2] |= CAN_ERR_PROT_STUFF;
416 rx_errors = 1;
417 }
418
419 priv->can.can_stats.bus_error++;
420 if (rx_errors)
421 dev->stats.rx_errors++;
422 if (tx_errors)
423 dev->stats.tx_errors++;
424 }
425
426 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
427 {
428 struct sk_buff *skb;
429 struct can_frame *cf;
430
431 skb = alloc_can_err_skb(dev, &cf);
432 if (unlikely(!skb))
433 return 0;
434
435 do_bus_err(dev, cf, reg_esr);
436 netif_receive_skb(skb);
437
438 dev->stats.rx_packets++;
439 dev->stats.rx_bytes += cf->can_dlc;
440
441 return 1;
442 }
443
444 static void do_state(struct net_device *dev,
445 struct can_frame *cf, enum can_state new_state)
446 {
447 struct flexcan_priv *priv = netdev_priv(dev);
448 struct can_berr_counter bec;
449
450 flexcan_get_berr_counter(dev, &bec);
451
452 switch (priv->can.state) {
453 case CAN_STATE_ERROR_ACTIVE:
454 /*
455 * from: ERROR_ACTIVE
456 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
457 * => : there was a warning int
458 */
459 if (new_state >= CAN_STATE_ERROR_WARNING &&
460 new_state <= CAN_STATE_BUS_OFF) {
461 netdev_dbg(dev, "Error Warning IRQ\n");
462 priv->can.can_stats.error_warning++;
463
464 cf->can_id |= CAN_ERR_CRTL;
465 cf->data[1] = (bec.txerr > bec.rxerr) ?
466 CAN_ERR_CRTL_TX_WARNING :
467 CAN_ERR_CRTL_RX_WARNING;
468 }
469 case CAN_STATE_ERROR_WARNING: /* fallthrough */
470 /*
471 * from: ERROR_ACTIVE, ERROR_WARNING
472 * to : ERROR_PASSIVE, BUS_OFF
473 * => : error passive int
474 */
475 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
476 new_state <= CAN_STATE_BUS_OFF) {
477 netdev_dbg(dev, "Error Passive IRQ\n");
478 priv->can.can_stats.error_passive++;
479
480 cf->can_id |= CAN_ERR_CRTL;
481 cf->data[1] = (bec.txerr > bec.rxerr) ?
482 CAN_ERR_CRTL_TX_PASSIVE :
483 CAN_ERR_CRTL_RX_PASSIVE;
484 }
485 break;
486 case CAN_STATE_BUS_OFF:
487 netdev_err(dev, "BUG! "
488 "hardware recovered automatically from BUS_OFF\n");
489 break;
490 default:
491 break;
492 }
493
494 /* process state changes depending on the new state */
495 switch (new_state) {
496 case CAN_STATE_ERROR_ACTIVE:
497 netdev_dbg(dev, "Error Active\n");
498 cf->can_id |= CAN_ERR_PROT;
499 cf->data[2] = CAN_ERR_PROT_ACTIVE;
500 break;
501 case CAN_STATE_BUS_OFF:
502 cf->can_id |= CAN_ERR_BUSOFF;
503 can_bus_off(dev);
504 break;
505 default:
506 break;
507 }
508 }
509
510 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
511 {
512 struct flexcan_priv *priv = netdev_priv(dev);
513 struct sk_buff *skb;
514 struct can_frame *cf;
515 enum can_state new_state;
516 int flt;
517
518 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
519 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
520 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
521 FLEXCAN_ESR_RX_WRN))))
522 new_state = CAN_STATE_ERROR_ACTIVE;
523 else
524 new_state = CAN_STATE_ERROR_WARNING;
525 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
526 new_state = CAN_STATE_ERROR_PASSIVE;
527 else
528 new_state = CAN_STATE_BUS_OFF;
529
530 /* state hasn't changed */
531 if (likely(new_state == priv->can.state))
532 return 0;
533
534 skb = alloc_can_err_skb(dev, &cf);
535 if (unlikely(!skb))
536 return 0;
537
538 do_state(dev, cf, new_state);
539 priv->can.state = new_state;
540 netif_receive_skb(skb);
541
542 dev->stats.rx_packets++;
543 dev->stats.rx_bytes += cf->can_dlc;
544
545 return 1;
546 }
547
548 static void flexcan_read_fifo(const struct net_device *dev,
549 struct can_frame *cf)
550 {
551 const struct flexcan_priv *priv = netdev_priv(dev);
552 struct flexcan_regs __iomem *regs = priv->base;
553 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
554 u32 reg_ctrl, reg_id;
555
556 reg_ctrl = flexcan_read(&mb->can_ctrl);
557 reg_id = flexcan_read(&mb->can_id);
558 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
559 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
560 else
561 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
562
563 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
564 cf->can_id |= CAN_RTR_FLAG;
565 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
566
567 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
568 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
569
570 /* mark as read */
571 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
572 flexcan_read(&regs->timer);
573 }
574
575 static int flexcan_read_frame(struct net_device *dev)
576 {
577 struct net_device_stats *stats = &dev->stats;
578 struct can_frame *cf;
579 struct sk_buff *skb;
580
581 skb = alloc_can_skb(dev, &cf);
582 if (unlikely(!skb)) {
583 stats->rx_dropped++;
584 return 0;
585 }
586
587 flexcan_read_fifo(dev, cf);
588 netif_receive_skb(skb);
589
590 stats->rx_packets++;
591 stats->rx_bytes += cf->can_dlc;
592
593 can_led_event(dev, CAN_LED_EVENT_RX);
594
595 return 1;
596 }
597
598 static int flexcan_poll(struct napi_struct *napi, int quota)
599 {
600 struct net_device *dev = napi->dev;
601 const struct flexcan_priv *priv = netdev_priv(dev);
602 struct flexcan_regs __iomem *regs = priv->base;
603 u32 reg_iflag1, reg_esr;
604 int work_done = 0;
605
606 /*
607 * The error bits are cleared on read,
608 * use saved value from irq handler.
609 */
610 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
611
612 /* handle state changes */
613 work_done += flexcan_poll_state(dev, reg_esr);
614
615 /* handle RX-FIFO */
616 reg_iflag1 = flexcan_read(&regs->iflag1);
617 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
618 work_done < quota) {
619 work_done += flexcan_read_frame(dev);
620 reg_iflag1 = flexcan_read(&regs->iflag1);
621 }
622
623 /* report bus errors */
624 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
625 work_done += flexcan_poll_bus_err(dev, reg_esr);
626
627 if (work_done < quota) {
628 napi_complete(napi);
629 /* enable IRQs */
630 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
631 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
632 }
633
634 return work_done;
635 }
636
637 static irqreturn_t flexcan_irq(int irq, void *dev_id)
638 {
639 struct net_device *dev = dev_id;
640 struct net_device_stats *stats = &dev->stats;
641 struct flexcan_priv *priv = netdev_priv(dev);
642 struct flexcan_regs __iomem *regs = priv->base;
643 u32 reg_iflag1, reg_esr;
644
645 reg_iflag1 = flexcan_read(&regs->iflag1);
646 reg_esr = flexcan_read(&regs->esr);
647 /* ACK all bus error and state change IRQ sources */
648 if (reg_esr & FLEXCAN_ESR_ALL_INT)
649 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
650
651 /*
652 * schedule NAPI in case of:
653 * - rx IRQ
654 * - state change IRQ
655 * - bus error IRQ and bus error reporting is activated
656 */
657 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
658 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
659 flexcan_has_and_handle_berr(priv, reg_esr)) {
660 /*
661 * The error bits are cleared on read,
662 * save them for later use.
663 */
664 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
665 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
666 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
667 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
668 &regs->ctrl);
669 napi_schedule(&priv->napi);
670 }
671
672 /* FIFO overflow */
673 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
674 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
675 dev->stats.rx_over_errors++;
676 dev->stats.rx_errors++;
677 }
678
679 /* transmission complete interrupt */
680 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
681 stats->tx_bytes += can_get_echo_skb(dev, 0);
682 stats->tx_packets++;
683 can_led_event(dev, CAN_LED_EVENT_TX);
684 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
685 netif_wake_queue(dev);
686 }
687
688 return IRQ_HANDLED;
689 }
690
691 static void flexcan_set_bittiming(struct net_device *dev)
692 {
693 const struct flexcan_priv *priv = netdev_priv(dev);
694 const struct can_bittiming *bt = &priv->can.bittiming;
695 struct flexcan_regs __iomem *regs = priv->base;
696 u32 reg;
697
698 reg = flexcan_read(&regs->ctrl);
699 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
700 FLEXCAN_CTRL_RJW(0x3) |
701 FLEXCAN_CTRL_PSEG1(0x7) |
702 FLEXCAN_CTRL_PSEG2(0x7) |
703 FLEXCAN_CTRL_PROPSEG(0x7) |
704 FLEXCAN_CTRL_LPB |
705 FLEXCAN_CTRL_SMP |
706 FLEXCAN_CTRL_LOM);
707
708 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
709 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
710 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
711 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
712 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
713
714 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
715 reg |= FLEXCAN_CTRL_LPB;
716 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
717 reg |= FLEXCAN_CTRL_LOM;
718 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
719 reg |= FLEXCAN_CTRL_SMP;
720
721 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
722 flexcan_write(reg, &regs->ctrl);
723
724 /* print chip status */
725 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
726 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
727 }
728
729 /*
730 * flexcan_chip_start
731 *
732 * this functions is entered with clocks enabled
733 *
734 */
735 static int flexcan_chip_start(struct net_device *dev)
736 {
737 struct flexcan_priv *priv = netdev_priv(dev);
738 struct flexcan_regs __iomem *regs = priv->base;
739 int err;
740 u32 reg_mcr, reg_ctrl;
741
742 /* enable module */
743 err = flexcan_chip_enable(priv);
744 if (err)
745 return err;
746
747 /* soft reset */
748 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
749 udelay(10);
750
751 reg_mcr = flexcan_read(&regs->mcr);
752 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
753 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
754 reg_mcr);
755 err = -ENODEV;
756 goto out;
757 }
758
759 flexcan_set_bittiming(dev);
760
761 /*
762 * MCR
763 *
764 * enable freeze
765 * enable fifo
766 * halt now
767 * only supervisor access
768 * enable warning int
769 * choose format C
770 * disable local echo
771 *
772 */
773 reg_mcr = flexcan_read(&regs->mcr);
774 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
775 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
776 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
777 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
778 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
779 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
780 flexcan_write(reg_mcr, &regs->mcr);
781
782 /*
783 * CTRL
784 *
785 * disable timer sync feature
786 *
787 * disable auto busoff recovery
788 * transmit lowest buffer first
789 *
790 * enable tx and rx warning interrupt
791 * enable bus off interrupt
792 * (== FLEXCAN_CTRL_ERR_STATE)
793 */
794 reg_ctrl = flexcan_read(&regs->ctrl);
795 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
796 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
797 FLEXCAN_CTRL_ERR_STATE;
798 /*
799 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
800 * on most Flexcan cores, too. Otherwise we don't get
801 * any error warning or passive interrupts.
802 */
803 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
804 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
805 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
806
807 /* save for later use */
808 priv->reg_ctrl_default = reg_ctrl;
809 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
810 flexcan_write(reg_ctrl, &regs->ctrl);
811
812 /* Abort any pending TX, mark Mailbox as INACTIVE */
813 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
814 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
815
816 /* acceptance mask/acceptance code (accept everything) */
817 flexcan_write(0x0, &regs->rxgmask);
818 flexcan_write(0x0, &regs->rx14mask);
819 flexcan_write(0x0, &regs->rx15mask);
820
821 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
822 flexcan_write(0x0, &regs->rxfgmask);
823
824 err = flexcan_transceiver_enable(priv);
825 if (err)
826 goto out;
827
828 /* synchronize with the can bus */
829 reg_mcr = flexcan_read(&regs->mcr);
830 reg_mcr &= ~FLEXCAN_MCR_HALT;
831 flexcan_write(reg_mcr, &regs->mcr);
832
833 priv->can.state = CAN_STATE_ERROR_ACTIVE;
834
835 /* enable FIFO interrupts */
836 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
837
838 /* print chip status */
839 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
840 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
841
842 return 0;
843
844 out:
845 flexcan_chip_disable(priv);
846 return err;
847 }
848
849 /*
850 * flexcan_chip_stop
851 *
852 * this functions is entered with clocks enabled
853 *
854 */
855 static void flexcan_chip_stop(struct net_device *dev)
856 {
857 struct flexcan_priv *priv = netdev_priv(dev);
858 struct flexcan_regs __iomem *regs = priv->base;
859 u32 reg;
860
861 /* Disable + halt module */
862 reg = flexcan_read(&regs->mcr);
863 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
864 flexcan_write(reg, &regs->mcr);
865
866 /* Disable all interrupts */
867 flexcan_write(0, &regs->imask1);
868 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
869 &regs->ctrl);
870
871 flexcan_transceiver_disable(priv);
872 priv->can.state = CAN_STATE_STOPPED;
873
874 return;
875 }
876
877 static int flexcan_open(struct net_device *dev)
878 {
879 struct flexcan_priv *priv = netdev_priv(dev);
880 int err;
881
882 err = clk_prepare_enable(priv->clk_ipg);
883 if (err)
884 return err;
885
886 err = clk_prepare_enable(priv->clk_per);
887 if (err)
888 goto out_disable_ipg;
889
890 err = open_candev(dev);
891 if (err)
892 goto out_disable_per;
893
894 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
895 if (err)
896 goto out_close;
897
898 /* start chip and queuing */
899 err = flexcan_chip_start(dev);
900 if (err)
901 goto out_free_irq;
902
903 can_led_event(dev, CAN_LED_EVENT_OPEN);
904
905 napi_enable(&priv->napi);
906 netif_start_queue(dev);
907
908 return 0;
909
910 out_free_irq:
911 free_irq(dev->irq, dev);
912 out_close:
913 close_candev(dev);
914 out_disable_per:
915 clk_disable_unprepare(priv->clk_per);
916 out_disable_ipg:
917 clk_disable_unprepare(priv->clk_ipg);
918
919 return err;
920 }
921
922 static int flexcan_close(struct net_device *dev)
923 {
924 struct flexcan_priv *priv = netdev_priv(dev);
925
926 netif_stop_queue(dev);
927 napi_disable(&priv->napi);
928 flexcan_chip_stop(dev);
929
930 free_irq(dev->irq, dev);
931 clk_disable_unprepare(priv->clk_per);
932 clk_disable_unprepare(priv->clk_ipg);
933
934 close_candev(dev);
935
936 can_led_event(dev, CAN_LED_EVENT_STOP);
937
938 return 0;
939 }
940
941 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
942 {
943 int err;
944
945 switch (mode) {
946 case CAN_MODE_START:
947 err = flexcan_chip_start(dev);
948 if (err)
949 return err;
950
951 netif_wake_queue(dev);
952 break;
953
954 default:
955 return -EOPNOTSUPP;
956 }
957
958 return 0;
959 }
960
961 static const struct net_device_ops flexcan_netdev_ops = {
962 .ndo_open = flexcan_open,
963 .ndo_stop = flexcan_close,
964 .ndo_start_xmit = flexcan_start_xmit,
965 };
966
967 static int register_flexcandev(struct net_device *dev)
968 {
969 struct flexcan_priv *priv = netdev_priv(dev);
970 struct flexcan_regs __iomem *regs = priv->base;
971 u32 reg, err;
972
973 err = clk_prepare_enable(priv->clk_ipg);
974 if (err)
975 return err;
976
977 err = clk_prepare_enable(priv->clk_per);
978 if (err)
979 goto out_disable_ipg;
980
981 /* select "bus clock", chip must be disabled */
982 err = flexcan_chip_disable(priv);
983 if (err)
984 goto out_disable_per;
985 reg = flexcan_read(&regs->ctrl);
986 reg |= FLEXCAN_CTRL_CLK_SRC;
987 flexcan_write(reg, &regs->ctrl);
988
989 err = flexcan_chip_enable(priv);
990 if (err)
991 goto out_chip_disable;
992
993 /* set freeze, halt and activate FIFO, restrict register access */
994 reg = flexcan_read(&regs->mcr);
995 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
996 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
997 flexcan_write(reg, &regs->mcr);
998
999 /*
1000 * Currently we only support newer versions of this core
1001 * featuring a RX FIFO. Older cores found on some Coldfire
1002 * derivates are not yet supported.
1003 */
1004 reg = flexcan_read(&regs->mcr);
1005 if (!(reg & FLEXCAN_MCR_FEN)) {
1006 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1007 err = -ENODEV;
1008 goto out_chip_disable;
1009 }
1010
1011 err = register_candev(dev);
1012
1013 /* disable core and turn off clocks */
1014 out_chip_disable:
1015 flexcan_chip_disable(priv);
1016 out_disable_per:
1017 clk_disable_unprepare(priv->clk_per);
1018 out_disable_ipg:
1019 clk_disable_unprepare(priv->clk_ipg);
1020
1021 return err;
1022 }
1023
1024 static void unregister_flexcandev(struct net_device *dev)
1025 {
1026 unregister_candev(dev);
1027 }
1028
1029 static const struct of_device_id flexcan_of_match[] = {
1030 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1031 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1032 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1033 { /* sentinel */ },
1034 };
1035 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1036
1037 static const struct platform_device_id flexcan_id_table[] = {
1038 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1039 { /* sentinel */ },
1040 };
1041 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1042
1043 static int flexcan_probe(struct platform_device *pdev)
1044 {
1045 const struct of_device_id *of_id;
1046 const struct flexcan_devtype_data *devtype_data;
1047 struct net_device *dev;
1048 struct flexcan_priv *priv;
1049 struct regulator *reg_xceiver;
1050 struct resource *mem;
1051 struct clk *clk_ipg = NULL, *clk_per = NULL;
1052 void __iomem *base;
1053 int err, irq;
1054 u32 clock_freq = 0;
1055
1056 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1057 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1058 return -EPROBE_DEFER;
1059 else if (IS_ERR(reg_xceiver))
1060 reg_xceiver = NULL;
1061
1062 if (pdev->dev.of_node)
1063 of_property_read_u32(pdev->dev.of_node,
1064 "clock-frequency", &clock_freq);
1065
1066 if (!clock_freq) {
1067 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1068 if (IS_ERR(clk_ipg)) {
1069 dev_err(&pdev->dev, "no ipg clock defined\n");
1070 return PTR_ERR(clk_ipg);
1071 }
1072
1073 clk_per = devm_clk_get(&pdev->dev, "per");
1074 if (IS_ERR(clk_per)) {
1075 dev_err(&pdev->dev, "no per clock defined\n");
1076 return PTR_ERR(clk_per);
1077 }
1078 clock_freq = clk_get_rate(clk_per);
1079 }
1080
1081 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 irq = platform_get_irq(pdev, 0);
1083 if (irq <= 0)
1084 return -ENODEV;
1085
1086 base = devm_ioremap_resource(&pdev->dev, mem);
1087 if (IS_ERR(base))
1088 return PTR_ERR(base);
1089
1090 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1091 if (of_id) {
1092 devtype_data = of_id->data;
1093 } else if (pdev->id_entry->driver_data) {
1094 devtype_data = (struct flexcan_devtype_data *)
1095 pdev->id_entry->driver_data;
1096 } else {
1097 return -ENODEV;
1098 }
1099
1100 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1101 if (!dev)
1102 return -ENOMEM;
1103
1104 dev->netdev_ops = &flexcan_netdev_ops;
1105 dev->irq = irq;
1106 dev->flags |= IFF_ECHO;
1107
1108 priv = netdev_priv(dev);
1109 priv->can.clock.freq = clock_freq;
1110 priv->can.bittiming_const = &flexcan_bittiming_const;
1111 priv->can.do_set_mode = flexcan_set_mode;
1112 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1113 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1114 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1115 CAN_CTRLMODE_BERR_REPORTING;
1116 priv->base = base;
1117 priv->dev = dev;
1118 priv->clk_ipg = clk_ipg;
1119 priv->clk_per = clk_per;
1120 priv->pdata = pdev->dev.platform_data;
1121 priv->devtype_data = devtype_data;
1122
1123 priv->reg_xceiver = reg_xceiver;
1124
1125 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1126
1127 platform_set_drvdata(pdev, dev);
1128 SET_NETDEV_DEV(dev, &pdev->dev);
1129
1130 err = register_flexcandev(dev);
1131 if (err) {
1132 dev_err(&pdev->dev, "registering netdev failed\n");
1133 goto failed_register;
1134 }
1135
1136 devm_can_led_init(dev);
1137
1138 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1139 priv->base, dev->irq);
1140
1141 return 0;
1142
1143 failed_register:
1144 free_candev(dev);
1145 return err;
1146 }
1147
1148 static int flexcan_remove(struct platform_device *pdev)
1149 {
1150 struct net_device *dev = platform_get_drvdata(pdev);
1151 struct flexcan_priv *priv = netdev_priv(dev);
1152
1153 unregister_flexcandev(dev);
1154 netif_napi_del(&priv->napi);
1155 free_candev(dev);
1156
1157 return 0;
1158 }
1159
1160 #ifdef CONFIG_PM_SLEEP
1161 static int flexcan_suspend(struct device *device)
1162 {
1163 struct net_device *dev = dev_get_drvdata(device);
1164 struct flexcan_priv *priv = netdev_priv(dev);
1165 int err;
1166
1167 if (netif_running(dev)) {
1168 err = flexcan_chip_disable(priv);
1169 if (err)
1170 return err;
1171 netif_stop_queue(dev);
1172 netif_device_detach(dev);
1173 }
1174 priv->can.state = CAN_STATE_SLEEPING;
1175
1176 return 0;
1177 }
1178
1179 static int flexcan_resume(struct device *device)
1180 {
1181 struct net_device *dev = dev_get_drvdata(device);
1182 struct flexcan_priv *priv = netdev_priv(dev);
1183 int err;
1184
1185 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1186 if (netif_running(dev)) {
1187 netif_device_attach(dev);
1188 netif_start_queue(dev);
1189 err = flexcan_chip_enable(priv);
1190 if (err)
1191 return err;
1192 }
1193 return 0;
1194 }
1195 #endif /* CONFIG_PM_SLEEP */
1196
1197 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1198
1199 static struct platform_driver flexcan_driver = {
1200 .driver = {
1201 .name = DRV_NAME,
1202 .owner = THIS_MODULE,
1203 .pm = &flexcan_pm_ops,
1204 .of_match_table = flexcan_of_match,
1205 },
1206 .probe = flexcan_probe,
1207 .remove = flexcan_remove,
1208 .id_table = flexcan_id_table,
1209 };
1210
1211 module_platform_driver(flexcan_driver);
1212
1213 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1214 "Marc Kleine-Budde <kernel@pengutronix.de>");
1215 MODULE_LICENSE("GPL v2");
1216 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux with added FPC-III support