drivers/net/wireless/iwlwifi/pcie/internal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #ifndef __iwl_trans_int_pcie_h__
  30 #define __iwl_trans_int_pcie_h__
  31
  32 #include <linux/spinlock.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/wait.h>
  36 #include <linux/pci.h>
  37 #include <linux/timer.h>
  38
  39 #include "iwl-fh.h"
  40 #include "iwl-csr.h"
  41 #include "iwl-trans.h"
  42 #include "iwl-debug.h"
  43 #include "iwl-io.h"
  44 #include "iwl-op-mode.h"
  45
  46 struct iwl_host_cmd;
  47
  48 /*This file includes the declaration that are internal to the
  49  * trans_pcie layer */
  50
  51 struct iwl_rx_mem_buffer {
  52         dma_addr_t page_dma;
  53         struct page *page;
  54         struct list_head list;
  55 };
  56
  57 /**
  58  * struct isr_statistics - interrupt statistics
  59  *
  60  */
  61 struct isr_statistics {
  62         u32 hw;
  63         u32 sw;
  64         u32 err_code;
  65         u32 sch;
  66         u32 alive;
  67         u32 rfkill;
  68         u32 ctkill;
  69         u32 wakeup;
  70         u32 rx;
  71         u32 tx;
  72         u32 unhandled;
  73 };
  74
  75 /**
  76  * struct iwl_rxq - Rx queue
  77  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
  78  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
  79  * @pool:
  80  * @queue:
  81  * @read: Shared index to newest available Rx buffer
  82  * @write: Shared index to oldest written Rx packet
  83  * @free_count: Number of pre-allocated buffers in rx_free
  84  * @write_actual:
  85  * @rx_free: list of free SKBs for use
  86  * @rx_used: List of Rx buffers with no SKB
  87  * @need_update: flag to indicate we need to update read/write index
  88  * @rb_stts: driver's pointer to receive buffer status
  89  * @rb_stts_dma: bus address of receive buffer status
  90  * @lock:
  91  *
  92  * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
  93  */
  94 struct iwl_rxq {
  95         __le32 *bd;
  96         dma_addr_t bd_dma;
  97         struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
  98         struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
  99         u32 read;
 100         u32 write;
 101         u32 free_count;
 102         u32 write_actual;
 103         struct list_head rx_free;
 104         struct list_head rx_used;
 105         int need_update;
 106         struct iwl_rb_status *rb_stts;
 107         dma_addr_t rb_stts_dma;
 108         spinlock_t lock;
 109 };
 110
 111 struct iwl_dma_ptr {
 112         dma_addr_t dma;
 113         void *addr;
 114         size_t size;
 115 };
 116
 117 /**
 118  * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
 119  * @index -- current index
 120  * @n_bd -- total number of entries in queue (must be power of 2)
 121  */
 122 static inline int iwl_queue_inc_wrap(int index, int n_bd)
 123 {
 124         return ++index & (n_bd - 1);
 125 }
 126
 127 /**
 128  * iwl_queue_dec_wrap - decrement queue index, wrap back to end
 129  * @index -- current index
 130  * @n_bd -- total number of entries in queue (must be power of 2)
 131  */
 132 static inline int iwl_queue_dec_wrap(int index, int n_bd)
 133 {
 134         return --index & (n_bd - 1);
 135 }
 136
 137 struct iwl_cmd_meta {
 138         /* only for SYNC commands, iff the reply skb is wanted */
 139         struct iwl_host_cmd *source;
 140         u32 flags;
 141 };
 142
 143 /*
 144  * Generic queue structure
 145  *
 146  * Contains common data for Rx and Tx queues.
 147  *
 148  * Note the difference between n_bd and n_window: the hardware
 149  * always assumes 256 descriptors, so n_bd is always 256 (unless
 150  * there might be HW changes in the future). For the normal TX
 151  * queues, n_window, which is the size of the software queue data
 152  * is also 256; however, for the command queue, n_window is only
 153  * 32 since we don't need so many commands pending. Since the HW
 154  * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
 155  * the software buffers (in the variables @meta, @txb in struct
 156  * iwl_txq) only have 32 entries, while the HW buffers (@tfds in
 157  * the same struct) have 256.
 158  * This means that we end up with the following:
 159  *  HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
 160  *  SW entries:           | 0      | ... | 31          |
 161  * where N is a number between 0 and 7. This means that the SW
 162  * data is a window overlayed over the HW queue.
 163  */
 164 struct iwl_queue {
 165         int n_bd;              /* number of BDs in this queue */
 166         int write_ptr;       /* 1-st empty entry (index) host_w*/
 167         int read_ptr;         /* last used entry (index) host_r*/
 168         /* use for monitoring and recovering the stuck queue */
 169         dma_addr_t dma_addr;   /* physical addr for BD's */
 170         int n_window;          /* safe queue window */
 171         u32 id;
 172         int low_mark;          /* low watermark, resume queue if free
 173                                 * space more than this */
 174         int high_mark;         /* high watermark, stop queue if free
 175                                 * space less than this */
 176 };
 177
 178 #define TFD_TX_CMD_SLOTS 256
 179 #define TFD_CMD_SLOTS 32
 180
 181 /*
 182  * The FH will write back to the first TB only, so we need
 183  * to copy some data into the buffer regardless of whether
 184  * it should be mapped or not. This indicates how big the
 185  * first TB must be to include the scratch buffer. Since
 186  * the scratch is 4 bytes at offset 12, it's 16 now. If we
 187  * make it bigger then allocations will be bigger and copy
 188  * slower, so that's probably not useful.
 189  */
 190 #define IWL_HCMD_SCRATCHBUF_SIZE        16
 191
 192 struct iwl_pcie_txq_entry {
 193         struct iwl_device_cmd *cmd;
 194         struct sk_buff *skb;
 195         /* buffer to free after command completes */
 196         const void *free_buf;
 197         struct iwl_cmd_meta meta;
 198 };
 199
 200 struct iwl_pcie_txq_scratch_buf {
 201         struct iwl_cmd_header hdr;
 202         u8 buf[8];
 203         __le32 scratch;
 204 };
 205
 206 /**
 207  * struct iwl_txq - Tx Queue for DMA
 208  * @q: generic Rx/Tx queue descriptor
 209  * @tfds: transmit frame descriptors (DMA memory)
 210  * @scratchbufs: start of command headers, including scratch buffers, for
 211  *      the writeback -- this is DMA memory and an array holding one buffer
 212  *      for each command on the queue
 213  * @scratchbufs_dma: DMA address for the scratchbufs start
 214  * @entries: transmit entries (driver state)
 215  * @lock: queue lock
 216  * @stuck_timer: timer that fires if queue gets stuck
 217  * @trans_pcie: pointer back to transport (for timer)
 218  * @need_update: indicates need to update read/write index
 219  * @active: stores if queue is active
 220  * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
 221  *
 222  * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
 223  * descriptors) and required locking structures.
 224  */
 225 struct iwl_txq {
 226         struct iwl_queue q;
 227         struct iwl_tfd *tfds;
 228         struct iwl_pcie_txq_scratch_buf *scratchbufs;
 229         dma_addr_t scratchbufs_dma;
 230         struct iwl_pcie_txq_entry *entries;
 231         spinlock_t lock;
 232         struct timer_list stuck_timer;
 233         struct iwl_trans_pcie *trans_pcie;
 234         u8 need_update;
 235         u8 active;
 236         bool ampdu;
 237 };
 238
 239 static inline dma_addr_t
 240 iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
 241 {
 242         return txq->scratchbufs_dma +
 243                sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
 244 }
 245
 246 /**
 247  * struct iwl_trans_pcie - PCIe transport specific data
 248  * @rxq: all the RX queue data
 249  * @rx_replenish: work that will be called when buffers need to be allocated
 250  * @drv - pointer to iwl_drv
 251  * @trans: pointer to the generic transport area
 252  * @scd_base_addr: scheduler sram base address in SRAM
 253  * @scd_bc_tbls: pointer to the byte count table of the scheduler
 254  * @kw: keep warm address
 255  * @pci_dev: basic pci-network driver stuff
 256  * @hw_base: pci hardware address support
 257  * @ucode_write_complete: indicates that the ucode has been copied.
 258  * @ucode_write_waitq: wait queue for uCode load
 259  * @status - transport specific status flags
 260  * @cmd_queue - command queue number
 261  * @rx_buf_size_8k: 8 kB RX buffer size
 262  * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
 263  * @rx_page_order: page order for receive buffer size
 264  * @wd_timeout: queue watchdog timeout (jiffies)
 265  * @reg_lock: protect hw register access
 266  */
 267 struct iwl_trans_pcie {
 268         struct iwl_rxq rxq;
 269         struct work_struct rx_replenish;
 270         struct iwl_trans *trans;
 271         struct iwl_drv *drv;
 272
 273         /* INT ICT Table */
 274         __le32 *ict_tbl;
 275         dma_addr_t ict_tbl_dma;
 276         int ict_index;
 277         u32 inta;
 278         bool use_ict;
 279         struct isr_statistics isr_stats;
 280
 281         spinlock_t irq_lock;
 282         u32 inta_mask;
 283         u32 scd_base_addr;
 284         struct iwl_dma_ptr scd_bc_tbls;
 285         struct iwl_dma_ptr kw;
 286
 287         struct iwl_txq *txq;
 288         unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
 289         unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
 290
 291         /* PCI bus related data */
 292         struct pci_dev *pci_dev;
 293         void __iomem *hw_base;
 294
 295         bool ucode_write_complete;
 296         wait_queue_head_t ucode_write_waitq;
 297         wait_queue_head_t wait_command_queue;
 298
 299         unsigned long status;
 300         u8 cmd_queue;
 301         u8 cmd_fifo;
 302         u8 n_no_reclaim_cmds;
 303         u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
 304
 305         bool rx_buf_size_8k;
 306         bool bc_table_dword;
 307         u32 rx_page_order;
 308
 309         const char **command_names;
 310
 311         /* queue watchdog */
 312         unsigned long wd_timeout;
 313
 314         /*protect hw register */
 315         spinlock_t reg_lock;
 316 };
 317
 318 /**
 319  * enum iwl_pcie_status: status of the PCIe transport
 320  * @STATUS_HCMD_ACTIVE: a SYNC command is being processed
 321  * @STATUS_DEVICE_ENABLED: APM is enabled
 322  * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
 323  * @STATUS_INT_ENABLED: interrupts are enabled
 324  * @STATUS_RFKILL: the HW RFkill switch is in KILL position
 325  * @STATUS_FW_ERROR: the fw is in error state
 326  */
 327 enum iwl_pcie_status {
 328         STATUS_HCMD_ACTIVE,
 329         STATUS_DEVICE_ENABLED,
 330         STATUS_TPOWER_PMI,
 331         STATUS_INT_ENABLED,
 332         STATUS_RFKILL,
 333         STATUS_FW_ERROR,
 334 };
 335
 336 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
 337         ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
 338
 339 static inline struct iwl_trans *
 340 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
 341 {
 342         return container_of((void *)trans_pcie, struct iwl_trans,
 343                             trans_specific);
 344 }
 345
 346 /*
 347  * Convention: trans API functions: iwl_trans_pcie_XXX
 348  *      Other functions: iwl_pcie_XXX
 349  */
 350 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
 351                                        const struct pci_device_id *ent,
 352                                        const struct iwl_cfg *cfg);
 353 void iwl_trans_pcie_free(struct iwl_trans *trans);
 354
 355 /*****************************************************
 356 * RX
 357 ******************************************************/
 358 int iwl_pcie_rx_init(struct iwl_trans *trans);
 359 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
 360 int iwl_pcie_rx_stop(struct iwl_trans *trans);
 361 void iwl_pcie_rx_free(struct iwl_trans *trans);
 362
 363 /*****************************************************
 364 * ICT - interrupt handling
 365 ******************************************************/
 366 irqreturn_t iwl_pcie_isr_ict(int irq, void *data);
 367 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
 368 void iwl_pcie_free_ict(struct iwl_trans *trans);
 369 void iwl_pcie_reset_ict(struct iwl_trans *trans);
 370 void iwl_pcie_disable_ict(struct iwl_trans *trans);
 371
 372 /*****************************************************
 373 * TX / HCMD
 374 ******************************************************/
 375 int iwl_pcie_tx_init(struct iwl_trans *trans);
 376 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
 377 int iwl_pcie_tx_stop(struct iwl_trans *trans);
 378 void iwl_pcie_tx_free(struct iwl_trans *trans);
 379 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
 380                                int sta_id, int tid, int frame_limit, u16 ssn);
 381 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
 382 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
 383                       struct iwl_device_cmd *dev_cmd, int txq_id);
 384 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq);
 385 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
 386 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
 387                             struct iwl_rx_cmd_buffer *rxb, int handler_status);
 388 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
 389                             struct sk_buff_head *skbs);
 390 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
 391
 392 /*****************************************************
 393 * Error handling
 394 ******************************************************/
 395 void iwl_pcie_dump_csr(struct iwl_trans *trans);
 396
 397 /*****************************************************
 398 * Helpers
 399 ******************************************************/
 400 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
 401 {
 402         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 403         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 404
 405         /* disable interrupts from uCode/NIC to host */
 406         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 407
 408         /* acknowledge/clear/reset any interrupts still pending
 409          * from uCode or flow handler (Rx/Tx DMA) */
 410         iwl_write32(trans, CSR_INT, 0xffffffff);
 411         iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
 412         IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
 413 }
 414
 415 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
 416 {
 417         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 418
 419         IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
 420         set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 421         iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 422 }
 423
 424 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
 425 {
 426         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
 427         iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
 428 }
 429
 430 static inline void iwl_wake_queue(struct iwl_trans *trans,
 431                                   struct iwl_txq *txq)
 432 {
 433         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 434
 435         if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
 436                 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
 437                 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
 438         }
 439 }
 440
 441 static inline void iwl_stop_queue(struct iwl_trans *trans,
 442                                   struct iwl_txq *txq)
 443 {
 444         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 445
 446         if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
 447                 iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
 448                 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
 449         } else
 450                 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
 451                                     txq->q.id);
 452 }
 453
 454 static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
 455 {
 456         return q->write_ptr >= q->read_ptr ?
 457                 (i >= q->read_ptr && i < q->write_ptr) :
 458                 !(i < q->read_ptr && i >= q->write_ptr);
 459 }
 460
 461 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
 462 {
 463         return index & (q->n_window - 1);
 464 }
 465
 466 static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie,
 467                                          u8 cmd)
 468 {
 469         if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
 470                 return "UNKNOWN";
 471         return trans_pcie->command_names[cmd];
 472 }
 473
 474 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
 475 {
 476         return !(iwl_read32(trans, CSR_GP_CNTRL) &
 477                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
 478 }
 479
 480 #endif /* __iwl_trans_int_pcie_h__ */