?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
blob6c769009587b6f903d432cf2888cc52d562dd190
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-op-mode.h"
38 #include "internal.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
41
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
44
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
46 * DMA services
47 *
48 * Theory of operation
49 *
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
55 * queue states.
56 *
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
59 *
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
63 * Tx queue resumed.
64 *
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue *q)
67 {
68 unsigned int max;
69 unsigned int used;
70
71 /*
72 * To avoid ambiguity between empty and completely full queues, there
73 * should always be less than q->n_bd elements in the queue.
74 * If q->n_window is smaller than q->n_bd, there is no need to reserve
75 * any queue entries for this purpose.
76 */
77 if (q->n_window < q->n_bd)
78 max = q->n_window;
79 else
80 max = q->n_bd - 1;
81
82 /*
83 * q->n_bd is a power of 2, so the following is equivalent to modulo by
84 * q->n_bd and is well defined for negative dividends.
85 */
86 used = (q->write_ptr - q->read_ptr) & (q->n_bd - 1);
87
88 if (WARN_ON(used > max))
89 return 0;
90
91 return max - used;
92 }
93
94 /*
95 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
96 */
97 static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
98 {
99 q->n_bd = count;
100 q->n_window = slots_num;
101 q->id = id;
102
103 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
104 * and iwl_queue_dec_wrap are broken. */
105 if (WARN_ON(!is_power_of_2(count)))
106 return -EINVAL;
107
108 /* slots_num must be power-of-two size, otherwise
109 * get_cmd_index is broken. */
110 if (WARN_ON(!is_power_of_2(slots_num)))
111 return -EINVAL;
112
113 q->low_mark = q->n_window / 4;
114 if (q->low_mark < 4)
115 q->low_mark = 4;
116
117 q->high_mark = q->n_window / 8;
118 if (q->high_mark < 2)
119 q->high_mark = 2;
120
121 q->write_ptr = 0;
122 q->read_ptr = 0;
123
124 return 0;
125 }
126
127 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
128 struct iwl_dma_ptr *ptr, size_t size)
129 {
130 if (WARN_ON(ptr->addr))
131 return -EINVAL;
132
133 ptr->addr = dma_alloc_coherent(trans->dev, size,
134 &ptr->dma, GFP_KERNEL);
135 if (!ptr->addr)
136 return -ENOMEM;
137 ptr->size = size;
138 return 0;
139 }
140
141 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
142 struct iwl_dma_ptr *ptr)
143 {
144 if (unlikely(!ptr->addr))
145 return;
146
147 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
148 memset(ptr, 0, sizeof(*ptr));
149 }
150
151 static void iwl_pcie_txq_stuck_timer(unsigned long data)
152 {
153 struct iwl_txq *txq = (void *)data;
154 struct iwl_queue *q = &txq->q;
155 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
156 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
157 u32 scd_sram_addr = trans_pcie->scd_base_addr +
158 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
159 u8 buf[16];
160 int i;
161
162 spin_lock(&txq->lock);
163 /* check if triggered erroneously */
164 if (txq->q.read_ptr == txq->q.write_ptr) {
165 spin_unlock(&txq->lock);
166 return;
167 }
168 spin_unlock(&txq->lock);
169
170 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
171 jiffies_to_msecs(trans_pcie->wd_timeout));
172 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
173 txq->q.read_ptr, txq->q.write_ptr);
174
175 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
176
177 iwl_print_hex_error(trans, buf, sizeof(buf));
178
179 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
180 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
181 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
182
183 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
184 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
185 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
186 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
187 u32 tbl_dw =
188 iwl_trans_read_mem32(trans,
189 trans_pcie->scd_base_addr +
190 SCD_TRANS_TBL_OFFSET_QUEUE(i));
191
192 if (i & 0x1)
193 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
194 else
195 tbl_dw = tbl_dw & 0x0000FFFF;
196
197 IWL_ERR(trans,
198 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
199 i, active ? "" : "in", fifo, tbl_dw,
200 iwl_read_prph(trans,
201 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
202 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
203 }
204
205 for (i = q->read_ptr; i != q->write_ptr;
206 i = iwl_queue_inc_wrap(i, q->n_bd))
207 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
208 le32_to_cpu(txq->scratchbufs[i].scratch));
209
210 iwl_op_mode_nic_error(trans->op_mode);
211 }
212
213 /*
214 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
215 */
216 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
217 struct iwl_txq *txq, u16 byte_cnt)
218 {
219 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
221 int write_ptr = txq->q.write_ptr;
222 int txq_id = txq->q.id;
223 u8 sec_ctl = 0;
224 u8 sta_id = 0;
225 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
226 __le16 bc_ent;
227 struct iwl_tx_cmd *tx_cmd =
228 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
229
230 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
231
232 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
233
234 sta_id = tx_cmd->sta_id;
235 sec_ctl = tx_cmd->sec_ctl;
236
237 switch (sec_ctl & TX_CMD_SEC_MSK) {
238 case TX_CMD_SEC_CCM:
239 len += IEEE80211_CCMP_MIC_LEN;
240 break;
241 case TX_CMD_SEC_TKIP:
242 len += IEEE80211_TKIP_ICV_LEN;
243 break;
244 case TX_CMD_SEC_WEP:
245 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
246 break;
247 }
248
249 if (trans_pcie->bc_table_dword)
250 len = DIV_ROUND_UP(len, 4);
251
252 bc_ent = cpu_to_le16(len | (sta_id << 12));
253
254 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
255
256 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
257 scd_bc_tbl[txq_id].
258 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
259 }
260
261 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
262 struct iwl_txq *txq)
263 {
264 struct iwl_trans_pcie *trans_pcie =
265 IWL_TRANS_GET_PCIE_TRANS(trans);
266 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
267 int txq_id = txq->q.id;
268 int read_ptr = txq->q.read_ptr;
269 u8 sta_id = 0;
270 __le16 bc_ent;
271 struct iwl_tx_cmd *tx_cmd =
272 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
273
274 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
275
276 if (txq_id != trans_pcie->cmd_queue)
277 sta_id = tx_cmd->sta_id;
278
279 bc_ent = cpu_to_le16(1 | (sta_id << 12));
280 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
281
282 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
283 scd_bc_tbl[txq_id].
284 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
285 }
286
287 /*
288 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
289 */
290 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
291 {
292 u32 reg = 0;
293 int txq_id = txq->q.id;
294
295 if (txq->need_update == 0)
296 return;
297
298 if (trans->cfg->base_params->shadow_reg_enable) {
299 /* shadow register enabled */
300 iwl_write32(trans, HBUS_TARG_WRPTR,
301 txq->q.write_ptr | (txq_id << 8));
302 } else {
303 struct iwl_trans_pcie *trans_pcie =
304 IWL_TRANS_GET_PCIE_TRANS(trans);
305 /* if we're trying to save power */
306 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
307 /* wake up nic if it's powered down ...
308 * uCode will wake up, and interrupt us again, so next
309 * time we'll skip this part. */
310 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
311
312 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
313 IWL_DEBUG_INFO(trans,
314 "Tx queue %d requesting wakeup,"
315 " GP1 = 0x%x\n", txq_id, reg);
316 iwl_set_bit(trans, CSR_GP_CNTRL,
317 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
318 return;
319 }
320
321 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id,
322 txq->q.write_ptr);
323
324 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
325 txq->q.write_ptr | (txq_id << 8));
326
327 /*
328 * else not in power-save mode,
329 * uCode will never sleep when we're
330 * trying to tx (during RFKILL, we're not trying to tx).
331 */
332 } else
333 iwl_write32(trans, HBUS_TARG_WRPTR,
334 txq->q.write_ptr | (txq_id << 8));
335 }
336 txq->need_update = 0;
337 }
338
339 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
340 {
341 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
342
343 dma_addr_t addr = get_unaligned_le32(&tb->lo);
344 if (sizeof(dma_addr_t) > sizeof(u32))
345 addr |=
346 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
347
348 return addr;
349 }
350
351 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
352 {
353 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
354
355 return le16_to_cpu(tb->hi_n_len) >> 4;
356 }
357
358 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
359 dma_addr_t addr, u16 len)
360 {
361 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
362 u16 hi_n_len = len << 4;
363
364 put_unaligned_le32(addr, &tb->lo);
365 if (sizeof(dma_addr_t) > sizeof(u32))
366 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
367
368 tb->hi_n_len = cpu_to_le16(hi_n_len);
369
370 tfd->num_tbs = idx + 1;
371 }
372
373 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
374 {
375 return tfd->num_tbs & 0x1f;
376 }
377
378 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
379 struct iwl_cmd_meta *meta,
380 struct iwl_tfd *tfd)
381 {
382 int i;
383 int num_tbs;
384
385 /* Sanity check on number of chunks */
386 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
387
388 if (num_tbs >= IWL_NUM_OF_TBS) {
389 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
390 /* @todo issue fatal error, it is quite serious situation */
391 return;
392 }
393
394 /* first TB is never freed - it's the scratchbuf data */
395
396 for (i = 1; i < num_tbs; i++)
397 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
398 iwl_pcie_tfd_tb_get_len(tfd, i),
399 DMA_TO_DEVICE);
400
401 tfd->num_tbs = 0;
402 }
403
404 /*
405 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
406 * @trans - transport private data
407 * @txq - tx queue
408 * @dma_dir - the direction of the DMA mapping
409 *
410 * Does NOT advance any TFD circular buffer read/write indexes
411 * Does NOT free the TFD itself (which is within circular buffer)
412 */
413 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
414 {
415 struct iwl_tfd *tfd_tmp = txq->tfds;
416
417 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
418 int rd_ptr = txq->q.read_ptr;
419 int idx = get_cmd_index(&txq->q, rd_ptr);
420
421 lockdep_assert_held(&txq->lock);
422
423 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
424 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
425
426 /* free SKB */
427 if (txq->entries) {
428 struct sk_buff *skb;
429
430 skb = txq->entries[idx].skb;
431
432 /* Can be called from irqs-disabled context
433 * If skb is not NULL, it means that the whole queue is being
434 * freed and that the queue is not empty - free the skb
435 */
436 if (skb) {
437 iwl_op_mode_free_skb(trans->op_mode, skb);
438 txq->entries[idx].skb = NULL;
439 }
440 }
441 }
442
443 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
444 dma_addr_t addr, u16 len, u8 reset)
445 {
446 struct iwl_queue *q;
447 struct iwl_tfd *tfd, *tfd_tmp;
448 u32 num_tbs;
449
450 q = &txq->q;
451 tfd_tmp = txq->tfds;
452 tfd = &tfd_tmp[q->write_ptr];
453
454 if (reset)
455 memset(tfd, 0, sizeof(*tfd));
456
457 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
458
459 /* Each TFD can point to a maximum 20 Tx buffers */
460 if (num_tbs >= IWL_NUM_OF_TBS) {
461 IWL_ERR(trans, "Error can not send more than %d chunks\n",
462 IWL_NUM_OF_TBS);
463 return -EINVAL;
464 }
465
466 if (WARN(addr & ~IWL_TX_DMA_MASK,
467 "Unaligned address = %llx\n", (unsigned long long)addr))
468 return -EINVAL;
469
470 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
471
472 return 0;
473 }
474
475 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
476 struct iwl_txq *txq, int slots_num,
477 u32 txq_id)
478 {
479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
480 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
481 size_t scratchbuf_sz;
482 int i;
483
484 if (WARN_ON(txq->entries || txq->tfds))
485 return -EINVAL;
486
487 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
488 (unsigned long)txq);
489 txq->trans_pcie = trans_pcie;
490
491 txq->q.n_window = slots_num;
492
493 txq->entries = kcalloc(slots_num,
494 sizeof(struct iwl_pcie_txq_entry),
495 GFP_KERNEL);
496
497 if (!txq->entries)
498 goto error;
499
500 if (txq_id == trans_pcie->cmd_queue)
501 for (i = 0; i < slots_num; i++) {
502 txq->entries[i].cmd =
503 kmalloc(sizeof(struct iwl_device_cmd),
504 GFP_KERNEL);
505 if (!txq->entries[i].cmd)
506 goto error;
507 }
508
509 /* Circular buffer of transmit frame descriptors (TFDs),
510 * shared with device */
511 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
512 &txq->q.dma_addr, GFP_KERNEL);
513 if (!txq->tfds)
514 goto error;
515
516 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
517 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
518 sizeof(struct iwl_cmd_header) +
519 offsetof(struct iwl_tx_cmd, scratch));
520
521 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
522
523 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
524 &txq->scratchbufs_dma,
525 GFP_KERNEL);
526 if (!txq->scratchbufs)
527 goto err_free_tfds;
528
529 txq->q.id = txq_id;
530
531 return 0;
532 err_free_tfds:
533 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
534 error:
535 if (txq->entries && txq_id == trans_pcie->cmd_queue)
536 for (i = 0; i < slots_num; i++)
537 kfree(txq->entries[i].cmd);
538 kfree(txq->entries);
539 txq->entries = NULL;
540
541 return -ENOMEM;
542
543 }
544
545 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
546 int slots_num, u32 txq_id)
547 {
548 int ret;
549
550 txq->need_update = 0;
551
552 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
553 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
554 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
555
556 /* Initialize queue's high/low-water marks, and head/tail indexes */
557 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
558 txq_id);
559 if (ret)
560 return ret;
561
562 spin_lock_init(&txq->lock);
563
564 /*
565 * Tell nic where to find circular buffer of Tx Frame Descriptors for
566 * given Tx queue, and enable the DMA channel used for that queue.
567 * Circular buffer (TFD queue in DRAM) physical base address */
568 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
569 txq->q.dma_addr >> 8);
570
571 return 0;
572 }
573
574 /*
575 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
576 */
577 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
578 {
579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
580 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
581 struct iwl_queue *q = &txq->q;
582
583 if (!q->n_bd)
584 return;
585
586 spin_lock_bh(&txq->lock);
587 while (q->write_ptr != q->read_ptr) {
588 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
589 txq_id, q->read_ptr);
590 iwl_pcie_txq_free_tfd(trans, txq);
591 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
592 }
593 txq->active = false;
594 spin_unlock_bh(&txq->lock);
595
596 /* just in case - this queue may have been stopped */
597 iwl_wake_queue(trans, txq);
598 }
599
600 /*
601 * iwl_pcie_txq_free - Deallocate DMA queue.
602 * @txq: Transmit queue to deallocate.
603 *
604 * Empty queue by removing and destroying all BD's.
605 * Free all buffers.
606 * 0-fill, but do not free "txq" descriptor structure.
607 */
608 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
609 {
610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
611 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
612 struct device *dev = trans->dev;
613 int i;
614
615 if (WARN_ON(!txq))
616 return;
617
618 iwl_pcie_txq_unmap(trans, txq_id);
619
620 /* De-alloc array of command/tx buffers */
621 if (txq_id == trans_pcie->cmd_queue)
622 for (i = 0; i < txq->q.n_window; i++) {
623 kfree(txq->entries[i].cmd);
624 kfree(txq->entries[i].free_buf);
625 }
626
627 /* De-alloc circular buffer of TFDs */
628 if (txq->q.n_bd) {
629 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
630 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
631 txq->q.dma_addr = 0;
632
633 dma_free_coherent(dev,
634 sizeof(*txq->scratchbufs) * txq->q.n_window,
635 txq->scratchbufs, txq->scratchbufs_dma);
636 }
637
638 kfree(txq->entries);
639 txq->entries = NULL;
640
641 del_timer_sync(&txq->stuck_timer);
642
643 /* 0-fill queue descriptor structure */
644 memset(txq, 0, sizeof(*txq));
645 }
646
647 /*
648 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
649 */
650 static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
651 {
652 struct iwl_trans_pcie __maybe_unused *trans_pcie =
653 IWL_TRANS_GET_PCIE_TRANS(trans);
654
655 iwl_write_prph(trans, SCD_TXFACT, mask);
656 }
657
658 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
659 {
660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
661 int nq = trans->cfg->base_params->num_of_queues;
662 int chan;
663 u32 reg_val;
664 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
665 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
666
667 /* make sure all queue are not stopped/used */
668 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
669 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
670
671 trans_pcie->scd_base_addr =
672 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
673
674 WARN_ON(scd_base_addr != 0 &&
675 scd_base_addr != trans_pcie->scd_base_addr);
676
677 /* reset context data, TX status and translation data */
678 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
679 SCD_CONTEXT_MEM_LOWER_BOUND,
680 NULL, clear_dwords);
681
682 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
683 trans_pcie->scd_bc_tbls.dma >> 10);
684
685 /* The chain extension of the SCD doesn't work well. This feature is
686 * enabled by default by the HW, so we need to disable it manually.
687 */
688 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
689
690 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
691 trans_pcie->cmd_fifo);
692
693 /* Activate all Tx DMA/FIFO channels */
694 iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
695
696 /* Enable DMA channel */
697 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
698 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
699 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
700 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
701
702 /* Update FH chicken bits */
703 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
704 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
705 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
706
707 /* Enable L1-Active */
708 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
709 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
710 }
711
712 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
713 {
714 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
715 int txq_id;
716
717 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
718 txq_id++) {
719 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
720
721 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
722 txq->q.dma_addr >> 8);
723 iwl_pcie_txq_unmap(trans, txq_id);
724 txq->q.read_ptr = 0;
725 txq->q.write_ptr = 0;
726 }
727
728 /* Tell NIC where to find the "keep warm" buffer */
729 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
730 trans_pcie->kw.dma >> 4);
731
732 /*
733 * Send 0 as the scd_base_addr since the device may have be reset
734 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
735 * contain garbage.
736 */
737 iwl_pcie_tx_start(trans, 0);
738 }
739
740 /*
741 * iwl_pcie_tx_stop - Stop all Tx DMA channels
742 */
743 int iwl_pcie_tx_stop(struct iwl_trans *trans)
744 {
745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
746 int ch, txq_id, ret;
747 unsigned long flags;
748
749 /* Turn off all Tx DMA fifos */
750 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
751
752 iwl_pcie_txq_set_sched(trans, 0);
753
754 /* Stop each Tx DMA channel, and wait for it to be idle */
755 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
756 iwl_write_direct32(trans,
757 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
758 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
759 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
760 if (ret < 0)
761 IWL_ERR(trans,
762 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
763 ch,
764 iwl_read_direct32(trans,
765 FH_TSSR_TX_STATUS_REG));
766 }
767 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
768
769 if (!trans_pcie->txq) {
770 IWL_WARN(trans,
771 "Stopping tx queues that aren't allocated...\n");
772 return 0;
773 }
774
775 /* Unmap DMA from host system and free skb's */
776 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
777 txq_id++)
778 iwl_pcie_txq_unmap(trans, txq_id);
779
780 return 0;
781 }
782
783 /*
784 * iwl_trans_tx_free - Free TXQ Context
785 *
786 * Destroy all TX DMA queues and structures
787 */
788 void iwl_pcie_tx_free(struct iwl_trans *trans)
789 {
790 int txq_id;
791 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
792
793 /* Tx queues */
794 if (trans_pcie->txq) {
795 for (txq_id = 0;
796 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
797 iwl_pcie_txq_free(trans, txq_id);
798 }
799
800 kfree(trans_pcie->txq);
801 trans_pcie->txq = NULL;
802
803 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
804
805 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
806 }
807
808 /*
809 * iwl_pcie_tx_alloc - allocate TX context
810 * Allocate all Tx DMA structures and initialize them
811 */
812 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
813 {
814 int ret;
815 int txq_id, slots_num;
816 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
817
818 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
819 sizeof(struct iwlagn_scd_bc_tbl);
820
821 /*It is not allowed to alloc twice, so warn when this happens.
822 * We cannot rely on the previous allocation, so free and fail */
823 if (WARN_ON(trans_pcie->txq)) {
824 ret = -EINVAL;
825 goto error;
826 }
827
828 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
829 scd_bc_tbls_size);
830 if (ret) {
831 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
832 goto error;
833 }
834
835 /* Alloc keep-warm buffer */
836 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
837 if (ret) {
838 IWL_ERR(trans, "Keep Warm allocation failed\n");
839 goto error;
840 }
841
842 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
843 sizeof(struct iwl_txq), GFP_KERNEL);
844 if (!trans_pcie->txq) {
845 IWL_ERR(trans, "Not enough memory for txq\n");
846 ret = -ENOMEM;
847 goto error;
848 }
849
850 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
851 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
852 txq_id++) {
853 slots_num = (txq_id == trans_pcie->cmd_queue) ?
854 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
855 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
856 slots_num, txq_id);
857 if (ret) {
858 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
859 goto error;
860 }
861 }
862
863 return 0;
864
865 error:
866 iwl_pcie_tx_free(trans);
867
868 return ret;
869 }
870 int iwl_pcie_tx_init(struct iwl_trans *trans)
871 {
872 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
873 int ret;
874 int txq_id, slots_num;
875 unsigned long flags;
876 bool alloc = false;
877
878 if (!trans_pcie->txq) {
879 ret = iwl_pcie_tx_alloc(trans);
880 if (ret)
881 goto error;
882 alloc = true;
883 }
884
885 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
886
887 /* Turn off all Tx DMA fifos */
888 iwl_write_prph(trans, SCD_TXFACT, 0);
889
890 /* Tell NIC where to find the "keep warm" buffer */
891 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
892 trans_pcie->kw.dma >> 4);
893
894 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
895
896 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
897 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
898 txq_id++) {
899 slots_num = (txq_id == trans_pcie->cmd_queue) ?
900 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
901 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
902 slots_num, txq_id);
903 if (ret) {
904 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
905 goto error;
906 }
907 }
908
909 return 0;
910 error:
911 /*Upon error, free only if we allocated something */
912 if (alloc)
913 iwl_pcie_tx_free(trans);
914 return ret;
915 }
916
917 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
918 struct iwl_txq *txq)
919 {
920 if (!trans_pcie->wd_timeout)
921 return;
922
923 /*
924 * if empty delete timer, otherwise move timer forward
925 * since we're making progress on this queue
926 */
927 if (txq->q.read_ptr == txq->q.write_ptr)
928 del_timer(&txq->stuck_timer);
929 else
930 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
931 }
932
933 /* Frees buffers until index _not_ inclusive */
934 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
935 struct sk_buff_head *skbs)
936 {
937 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
938 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
939 /* n_bd is usually 256 => n_bd - 1 = 0xff */
940 int tfd_num = ssn & (txq->q.n_bd - 1);
941 struct iwl_queue *q = &txq->q;
942 int last_to_free;
943
944 /* This function is not meant to release cmd queue*/
945 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
946 return;
947
948 spin_lock_bh(&txq->lock);
949
950 if (!txq->active) {
951 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
952 txq_id, ssn);
953 goto out;
954 }
955
956 if (txq->q.read_ptr == tfd_num)
957 goto out;
958
959 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
960 txq_id, txq->q.read_ptr, tfd_num, ssn);
961
962 /*Since we free until index _not_ inclusive, the one before index is
963 * the last we will free. This one must be used */
964 last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);
965
966 if (!iwl_queue_used(q, last_to_free)) {
967 IWL_ERR(trans,
968 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
969 __func__, txq_id, last_to_free, q->n_bd,
970 q->write_ptr, q->read_ptr);
971 goto out;
972 }
973
974 if (WARN_ON(!skb_queue_empty(skbs)))
975 goto out;
976
977 for (;
978 q->read_ptr != tfd_num;
979 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
980
981 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
982 continue;
983
984 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
985
986 txq->entries[txq->q.read_ptr].skb = NULL;
987
988 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
989
990 iwl_pcie_txq_free_tfd(trans, txq);
991 }
992
993 iwl_pcie_txq_progress(trans_pcie, txq);
994
995 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
996 iwl_wake_queue(trans, txq);
997 out:
998 spin_unlock_bh(&txq->lock);
999 }
1000
1001 /*
1002 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1003 *
1004 * When FW advances 'R' index, all entries between old and new 'R' index
1005 * need to be reclaimed. As result, some free space forms. If there is
1006 * enough free space (> low mark), wake the stack that feeds us.
1007 */
1008 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1009 {
1010 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1011 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1012 struct iwl_queue *q = &txq->q;
1013 int nfreed = 0;
1014
1015 lockdep_assert_held(&txq->lock);
1016
1017 if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {
1018 IWL_ERR(trans,
1019 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1020 __func__, txq_id, idx, q->n_bd,
1021 q->write_ptr, q->read_ptr);
1022 return;
1023 }
1024
1025 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1026 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1027
1028 if (nfreed++ > 0) {
1029 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1030 idx, q->write_ptr, q->read_ptr);
1031 iwl_op_mode_nic_error(trans->op_mode);
1032 }
1033 }
1034
1035 iwl_pcie_txq_progress(trans_pcie, txq);
1036 }
1037
1038 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1039 u16 txq_id)
1040 {
1041 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1042 u32 tbl_dw_addr;
1043 u32 tbl_dw;
1044 u16 scd_q2ratid;
1045
1046 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1047
1048 tbl_dw_addr = trans_pcie->scd_base_addr +
1049 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1050
1051 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1052
1053 if (txq_id & 0x1)
1054 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1055 else
1056 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1057
1058 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1059
1060 return 0;
1061 }
1062
1063 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
1064 u16 txq_id)
1065 {
1066 /* Simply stop the queue, but don't change any configuration;
1067 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1068 iwl_write_prph(trans,
1069 SCD_QUEUE_STATUS_BITS(txq_id),
1070 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1071 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1072 }
1073
1074 /* Receiver address (actually, Rx station's index into station table),
1075 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1076 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1077
1078 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
1079 int sta_id, int tid, int frame_limit, u16 ssn)
1080 {
1081 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1082
1083 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1084 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1085
1086 /* Stop this Tx queue before configuring it */
1087 iwl_pcie_txq_set_inactive(trans, txq_id);
1088
1089 /* Set this queue as a chain-building queue unless it is CMD queue */
1090 if (txq_id != trans_pcie->cmd_queue)
1091 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
1092
1093 /* If this queue is mapped to a certain station: it is an AGG queue */
1094 if (sta_id >= 0) {
1095 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
1096
1097 /* Map receiver-address / traffic-ID to this queue */
1098 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1099
1100 /* enable aggregations for the queue */
1101 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1102 trans_pcie->txq[txq_id].ampdu = true;
1103 } else {
1104 /*
1105 * disable aggregations for the queue, this will also make the
1106 * ra_tid mapping configuration irrelevant since it is now a
1107 * non-AGG queue.
1108 */
1109 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1110
1111 ssn = trans_pcie->txq[txq_id].q.read_ptr;
1112 }
1113
1114 /* Place first TFD at index corresponding to start sequence number.
1115 * Assumes that ssn_idx is valid (!= 0xFFF) */
1116 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1117 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1118
1119 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1120 (ssn & 0xff) | (txq_id << 8));
1121 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1122
1123 /* Set up Tx window size and frame limit for this queue */
1124 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1125 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1126 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1127 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1128 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1129 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1130 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1131 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1132
1133 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1134 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1135 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1136 (fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1137 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1138 SCD_QUEUE_STTS_REG_MSK);
1139 trans_pcie->txq[txq_id].active = true;
1140 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1141 txq_id, fifo, ssn & 0xff);
1142 }
1143
1144 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
1145 {
1146 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1147 u32 stts_addr = trans_pcie->scd_base_addr +
1148 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1149 static const u32 zero_val[4] = {};
1150
1151 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1152 WARN_ONCE(1, "queue %d not used", txq_id);
1153 return;
1154 }
1155
1156 iwl_pcie_txq_set_inactive(trans, txq_id);
1157
1158 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1159 ARRAY_SIZE(zero_val));
1160
1161 iwl_pcie_txq_unmap(trans, txq_id);
1162 trans_pcie->txq[txq_id].ampdu = false;
1163
1164 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1165 }
1166
1167 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1168
1169 /*
1170 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1171 * @priv: device private data point
1172 * @cmd: a pointer to the ucode command structure
1173 *
1174 * The function returns < 0 values to indicate the operation
1175 * failed. On success, it returns the index (>= 0) of command in the
1176 * command queue.
1177 */
1178 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1179 struct iwl_host_cmd *cmd)
1180 {
1181 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1182 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1183 struct iwl_queue *q = &txq->q;
1184 struct iwl_device_cmd *out_cmd;
1185 struct iwl_cmd_meta *out_meta;
1186 void *dup_buf = NULL;
1187 dma_addr_t phys_addr;
1188 int idx;
1189 u16 copy_size, cmd_size, scratch_size;
1190 bool had_nocopy = false;
1191 int i;
1192 u32 cmd_pos;
1193 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1194 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1195
1196 copy_size = sizeof(out_cmd->hdr);
1197 cmd_size = sizeof(out_cmd->hdr);
1198
1199 /* need one for the header if the first is NOCOPY */
1200 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1201
1202 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1203 cmddata[i] = cmd->data[i];
1204 cmdlen[i] = cmd->len[i];
1205
1206 if (!cmd->len[i])
1207 continue;
1208
1209 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1210 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1211 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1212
1213 if (copy > cmdlen[i])
1214 copy = cmdlen[i];
1215 cmdlen[i] -= copy;
1216 cmddata[i] += copy;
1217 copy_size += copy;
1218 }
1219
1220 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1221 had_nocopy = true;
1222 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1223 idx = -EINVAL;
1224 goto free_dup_buf;
1225 }
1226 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1227 /*
1228 * This is also a chunk that isn't copied
1229 * to the static buffer so set had_nocopy.
1230 */
1231 had_nocopy = true;
1232
1233 /* only allowed once */
1234 if (WARN_ON(dup_buf)) {
1235 idx = -EINVAL;
1236 goto free_dup_buf;
1237 }
1238
1239 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1240 GFP_ATOMIC);
1241 if (!dup_buf)
1242 return -ENOMEM;
1243 } else {
1244 /* NOCOPY must not be followed by normal! */
1245 if (WARN_ON(had_nocopy)) {
1246 idx = -EINVAL;
1247 goto free_dup_buf;
1248 }
1249 copy_size += cmdlen[i];
1250 }
1251 cmd_size += cmd->len[i];
1252 }
1253
1254 /*
1255 * If any of the command structures end up being larger than
1256 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1257 * allocated into separate TFDs, then we will need to
1258 * increase the size of the buffers.
1259 */
1260 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1261 "Command %s (%#x) is too large (%d bytes)\n",
1262 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1263 idx = -EINVAL;
1264 goto free_dup_buf;
1265 }
1266
1267 spin_lock_bh(&txq->lock);
1268
1269 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1270 spin_unlock_bh(&txq->lock);
1271
1272 IWL_ERR(trans, "No space in command queue\n");
1273 iwl_op_mode_cmd_queue_full(trans->op_mode);
1274 idx = -ENOSPC;
1275 goto free_dup_buf;
1276 }
1277
1278 idx = get_cmd_index(q, q->write_ptr);
1279 out_cmd = txq->entries[idx].cmd;
1280 out_meta = &txq->entries[idx].meta;
1281
1282 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1283 if (cmd->flags & CMD_WANT_SKB)
1284 out_meta->source = cmd;
1285
1286 /* set up the header */
1287
1288 out_cmd->hdr.cmd = cmd->id;
1289 out_cmd->hdr.flags = 0;
1290 out_cmd->hdr.sequence =
1291 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1292 INDEX_TO_SEQ(q->write_ptr));
1293
1294 /* and copy the data that needs to be copied */
1295 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1296 copy_size = sizeof(out_cmd->hdr);
1297 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1298 int copy = 0;
1299
1300 if (!cmd->len[i])
1301 continue;
1302
1303 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1304 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1305 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1306
1307 if (copy > cmd->len[i])
1308 copy = cmd->len[i];
1309 }
1310
1311 /* copy everything if not nocopy/dup */
1312 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1313 IWL_HCMD_DFL_DUP)))
1314 copy = cmd->len[i];
1315
1316 if (copy) {
1317 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1318 cmd_pos += copy;
1319 copy_size += copy;
1320 }
1321 }
1322
1323 IWL_DEBUG_HC(trans,
1324 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1325 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1326 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1327 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1328
1329 /* start the TFD with the scratchbuf */
1330 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1331 memcpy(&txq->scratchbufs[idx], &out_cmd->hdr, scratch_size);
1332 iwl_pcie_txq_build_tfd(trans, txq,
1333 iwl_pcie_get_scratchbuf_dma(txq, idx),
1334 scratch_size, 1);
1335
1336 /* map first command fragment, if any remains */
1337 if (copy_size > scratch_size) {
1338 phys_addr = dma_map_single(trans->dev,
1339 ((u8 *)&out_cmd->hdr) + scratch_size,
1340 copy_size - scratch_size,
1341 DMA_TO_DEVICE);
1342 if (dma_mapping_error(trans->dev, phys_addr)) {
1343 iwl_pcie_tfd_unmap(trans, out_meta,
1344 &txq->tfds[q->write_ptr]);
1345 idx = -ENOMEM;
1346 goto out;
1347 }
1348
1349 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1350 copy_size - scratch_size, 0);
1351 }
1352
1353 /* map the remaining (adjusted) nocopy/dup fragments */
1354 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1355 const void *data = cmddata[i];
1356
1357 if (!cmdlen[i])
1358 continue;
1359 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1360 IWL_HCMD_DFL_DUP)))
1361 continue;
1362 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1363 data = dup_buf;
1364 phys_addr = dma_map_single(trans->dev, (void *)data,
1365 cmdlen[i], DMA_TO_DEVICE);
1366 if (dma_mapping_error(trans->dev, phys_addr)) {
1367 iwl_pcie_tfd_unmap(trans, out_meta,
1368 &txq->tfds[q->write_ptr]);
1369 idx = -ENOMEM;
1370 goto out;
1371 }
1372
1373 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0);
1374 }
1375
1376 out_meta->flags = cmd->flags;
1377 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1378 kfree(txq->entries[idx].free_buf);
1379 txq->entries[idx].free_buf = dup_buf;
1380
1381 txq->need_update = 1;
1382
1383 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1384
1385 /* start timer if queue currently empty */
1386 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1387 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1388
1389 /* Increment and update queue's write index */
1390 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1391 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1392
1393 out:
1394 spin_unlock_bh(&txq->lock);
1395 free_dup_buf:
1396 if (idx < 0)
1397 kfree(dup_buf);
1398 return idx;
1399 }
1400
1401 /*
1402 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1403 * @rxb: Rx buffer to reclaim
1404 * @handler_status: return value of the handler of the command
1405 * (put in setup_rx_handlers)
1406 *
1407 * If an Rx buffer has an async callback associated with it the callback
1408 * will be executed. The attached skb (if present) will only be freed
1409 * if the callback returns 1
1410 */
1411 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1412 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1413 {
1414 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1415 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1416 int txq_id = SEQ_TO_QUEUE(sequence);
1417 int index = SEQ_TO_INDEX(sequence);
1418 int cmd_index;
1419 struct iwl_device_cmd *cmd;
1420 struct iwl_cmd_meta *meta;
1421 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1422 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1423
1424 /* If a Tx command is being handled and it isn't in the actual
1425 * command queue then there a command routing bug has been introduced
1426 * in the queue management code. */
1427 if (WARN(txq_id != trans_pcie->cmd_queue,
1428 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1429 txq_id, trans_pcie->cmd_queue, sequence,
1430 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1431 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1432 iwl_print_hex_error(trans, pkt, 32);
1433 return;
1434 }
1435
1436 spin_lock_bh(&txq->lock);
1437
1438 cmd_index = get_cmd_index(&txq->q, index);
1439 cmd = txq->entries[cmd_index].cmd;
1440 meta = &txq->entries[cmd_index].meta;
1441
1442 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1443
1444 /* Input error checking is done when commands are added to queue. */
1445 if (meta->flags & CMD_WANT_SKB) {
1446 struct page *p = rxb_steal_page(rxb);
1447
1448 meta->source->resp_pkt = pkt;
1449 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1450 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1451 meta->source->handler_status = handler_status;
1452 }
1453
1454 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1455
1456 if (!(meta->flags & CMD_ASYNC)) {
1457 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1458 IWL_WARN(trans,
1459 "HCMD_ACTIVE already clear for command %s\n",
1460 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1461 }
1462 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1463 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1464 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1465 wake_up(&trans_pcie->wait_command_queue);
1466 }
1467
1468 meta->flags = 0;
1469
1470 spin_unlock_bh(&txq->lock);
1471 }
1472
1473 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1474
1475 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1476 struct iwl_host_cmd *cmd)
1477 {
1478 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1479 int ret;
1480
1481 /* An asynchronous command can not expect an SKB to be set. */
1482 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1483 return -EINVAL;
1484
1485 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1486 if (ret < 0) {
1487 IWL_ERR(trans,
1488 "Error sending %s: enqueue_hcmd failed: %d\n",
1489 get_cmd_string(trans_pcie, cmd->id), ret);
1490 return ret;
1491 }
1492 return 0;
1493 }
1494
1495 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1496 struct iwl_host_cmd *cmd)
1497 {
1498 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1499 int cmd_idx;
1500 int ret;
1501
1502 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1503 get_cmd_string(trans_pcie, cmd->id));
1504
1505 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
1506 &trans_pcie->status))) {
1507 IWL_ERR(trans, "Command %s: a command is already active!\n",
1508 get_cmd_string(trans_pcie, cmd->id));
1509 return -EIO;
1510 }
1511
1512 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1513 get_cmd_string(trans_pcie, cmd->id));
1514
1515 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1516 if (cmd_idx < 0) {
1517 ret = cmd_idx;
1518 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1519 IWL_ERR(trans,
1520 "Error sending %s: enqueue_hcmd failed: %d\n",
1521 get_cmd_string(trans_pcie, cmd->id), ret);
1522 return ret;
1523 }
1524
1525 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1526 !test_bit(STATUS_HCMD_ACTIVE,
1527 &trans_pcie->status),
1528 HOST_COMPLETE_TIMEOUT);
1529 if (!ret) {
1530 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1531 struct iwl_txq *txq =
1532 &trans_pcie->txq[trans_pcie->cmd_queue];
1533 struct iwl_queue *q = &txq->q;
1534
1535 IWL_ERR(trans,
1536 "Error sending %s: time out after %dms.\n",
1537 get_cmd_string(trans_pcie, cmd->id),
1538 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1539
1540 IWL_ERR(trans,
1541 "Current CMD queue read_ptr %d write_ptr %d\n",
1542 q->read_ptr, q->write_ptr);
1543
1544 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1545 IWL_DEBUG_INFO(trans,
1546 "Clearing HCMD_ACTIVE for command %s\n",
1547 get_cmd_string(trans_pcie, cmd->id));
1548 ret = -ETIMEDOUT;
1549 goto cancel;
1550 }
1551 }
1552
1553 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) {
1554 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1555 get_cmd_string(trans_pcie, cmd->id));
1556 dump_stack();
1557 ret = -EIO;
1558 goto cancel;
1559 }
1560
1561 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1562 test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1563 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1564 ret = -ERFKILL;
1565 goto cancel;
1566 }
1567
1568 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1569 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1570 get_cmd_string(trans_pcie, cmd->id));
1571 ret = -EIO;
1572 goto cancel;
1573 }
1574
1575 return 0;
1576
1577 cancel:
1578 if (cmd->flags & CMD_WANT_SKB) {
1579 /*
1580 * Cancel the CMD_WANT_SKB flag for the cmd in the
1581 * TX cmd queue. Otherwise in case the cmd comes
1582 * in later, it will possibly set an invalid
1583 * address (cmd->meta.source).
1584 */
1585 trans_pcie->txq[trans_pcie->cmd_queue].
1586 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1587 }
1588
1589 if (cmd->resp_pkt) {
1590 iwl_free_resp(cmd);
1591 cmd->resp_pkt = NULL;
1592 }
1593
1594 return ret;
1595 }
1596
1597 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1598 {
1599 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1600
1601 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status))
1602 return -EIO;
1603
1604 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1605 test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1606 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1607 cmd->id);
1608 return -ERFKILL;
1609 }
1610
1611 if (cmd->flags & CMD_ASYNC)
1612 return iwl_pcie_send_hcmd_async(trans, cmd);
1613
1614 /* We still can fail on RFKILL that can be asserted while we wait */
1615 return iwl_pcie_send_hcmd_sync(trans, cmd);
1616 }
1617
1618 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1619 struct iwl_device_cmd *dev_cmd, int txq_id)
1620 {
1621 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1622 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1623 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1624 struct iwl_cmd_meta *out_meta;
1625 struct iwl_txq *txq;
1626 struct iwl_queue *q;
1627 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1628 void *tb1_addr;
1629 u16 len, tb1_len, tb2_len;
1630 u8 wait_write_ptr = 0;
1631 __le16 fc = hdr->frame_control;
1632 u8 hdr_len = ieee80211_hdrlen(fc);
1633 u16 wifi_seq;
1634
1635 txq = &trans_pcie->txq[txq_id];
1636 q = &txq->q;
1637
1638 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1639 "TX on unused queue %d\n", txq_id))
1640 return -EINVAL;
1641
1642 spin_lock(&txq->lock);
1643
1644 /* In AGG mode, the index in the ring must correspond to the WiFi
1645 * sequence number. This is a HW requirements to help the SCD to parse
1646 * the BA.
1647 * Check here that the packets are in the right place on the ring.
1648 */
1649 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1650 WARN_ONCE(txq->ampdu &&
1651 (wifi_seq & 0xff) != q->write_ptr,
1652 "Q: %d WiFi Seq %d tfdNum %d",
1653 txq_id, wifi_seq, q->write_ptr);
1654
1655 /* Set up driver data for this TFD */
1656 txq->entries[q->write_ptr].skb = skb;
1657 txq->entries[q->write_ptr].cmd = dev_cmd;
1658
1659 dev_cmd->hdr.cmd = REPLY_TX;
1660 dev_cmd->hdr.sequence =
1661 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1662 INDEX_TO_SEQ(q->write_ptr)));
1663
1664 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1665 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1666 offsetof(struct iwl_tx_cmd, scratch);
1667
1668 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1669 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1670
1671 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1672 out_meta = &txq->entries[q->write_ptr].meta;
1673
1674 /*
1675 * The second TB (tb1) points to the remainder of the TX command
1676 * and the 802.11 header - dword aligned size
1677 * (This calculation modifies the TX command, so do it before the
1678 * setup of the first TB)
1679 */
1680 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1681 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1682 tb1_len = ALIGN(len, 4);
1683
1684 /* Tell NIC about any 2-byte padding after MAC header */
1685 if (tb1_len != len)
1686 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1687
1688 /* The first TB points to the scratchbuf data - min_copy bytes */
1689 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1690 IWL_HCMD_SCRATCHBUF_SIZE);
1691 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1692 IWL_HCMD_SCRATCHBUF_SIZE, 1);
1693
1694 /* there must be data left over for TB1 or this code must be changed */
1695 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1696
1697 /* map the data for TB1 */
1698 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1699 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1700 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1701 goto out_err;
1702 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0);
1703
1704 /*
1705 * Set up TFD's third entry to point directly to remainder
1706 * of skb, if any (802.11 null frames have no payload).
1707 */
1708 tb2_len = skb->len - hdr_len;
1709 if (tb2_len > 0) {
1710 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1711 skb->data + hdr_len,
1712 tb2_len, DMA_TO_DEVICE);
1713 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1714 iwl_pcie_tfd_unmap(trans, out_meta,
1715 &txq->tfds[q->write_ptr]);
1716 goto out_err;
1717 }
1718 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0);
1719 }
1720
1721 /* Set up entry for this TFD in Tx byte-count array */
1722 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1723
1724 trace_iwlwifi_dev_tx(trans->dev, skb,
1725 &txq->tfds[txq->q.write_ptr],
1726 sizeof(struct iwl_tfd),
1727 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1728 skb->data + hdr_len, tb2_len);
1729 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1730 skb->data + hdr_len, tb2_len);
1731
1732 if (!ieee80211_has_morefrags(fc)) {
1733 txq->need_update = 1;
1734 } else {
1735 wait_write_ptr = 1;
1736 txq->need_update = 0;
1737 }
1738
1739 /* start timer if queue currently empty */
1740 if (txq->need_update && q->read_ptr == q->write_ptr &&
1741 trans_pcie->wd_timeout)
1742 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1743
1744 /* Tell device the write index *just past* this latest filled TFD */
1745 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1746 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1747
1748 /*
1749 * At this point the frame is "transmitted" successfully
1750 * and we will get a TX status notification eventually,
1751 * regardless of the value of ret. "ret" only indicates
1752 * whether or not we should update the write pointer.
1753 */
1754 if (iwl_queue_space(q) < q->high_mark) {
1755 if (wait_write_ptr) {
1756 txq->need_update = 1;
1757 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1758 } else {
1759 iwl_stop_queue(trans, txq);
1760 }
1761 }
1762 spin_unlock(&txq->lock);
1763 return 0;
1764 out_err:
1765 spin_unlock(&txq->lock);
1766 return -1;
1767 }
Linux with added FPC-III support