| blob | 71f70c724fc9fd319165fc4148dbfe379e6a5f7e |
1 /*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
29 /*
30 Module: rt2800
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
33 */
35 #ifndef RT2800_H
36 #define RT2800_H
38 /*
39 * RF chip defines.
40 *
41 * RF2820 2.4G 2T3R
42 * RF2850 2.4G/5G 2T3R
43 * RF2720 2.4G 1T2R
44 * RF2750 2.4G/5G 1T2R
45 * RF3020 2.4G 1T1R
46 * RF2020 2.4G B/G
47 * RF3021 2.4G 1T2R
48 * RF3022 2.4G 2T2R
49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5592 2.4G/5G 2T2R
55 * RF3070 2.4G 1T1R
56 * RF5360 2.4G 1T1R
57 * RF5362 2.4G 1T1R
58 * RF5370 2.4G 1T1R
59 * RF5390 2.4G 1T1R
60 */
61 #define RF2820 0x0001
62 #define RF2850 0x0002
63 #define RF2720 0x0003
64 #define RF2750 0x0004
65 #define RF3020 0x0005
66 #define RF2020 0x0006
67 #define RF3021 0x0007
68 #define RF3022 0x0008
69 #define RF3052 0x0009
70 #define RF2853 0x000a
71 #define RF3320 0x000b
72 #define RF3322 0x000c
73 #define RF3053 0x000d
74 #define RF5592 0x000f
75 #define RF3070 0x3070
76 #define RF3290 0x3290
77 #define RF5360 0x5360
78 #define RF5362 0x5362
79 #define RF5370 0x5370
80 #define RF5372 0x5372
81 #define RF5390 0x5390
82 #define RF5392 0x5392
84 /*
85 * Chipset revisions.
86 */
87 #define REV_RT2860C 0x0100
88 #define REV_RT2860D 0x0101
89 #define REV_RT2872E 0x0200
90 #define REV_RT3070E 0x0200
91 #define REV_RT3070F 0x0201
92 #define REV_RT3071E 0x0211
93 #define REV_RT3090E 0x0211
94 #define REV_RT3390E 0x0211
95 #define REV_RT3593E 0x0211
96 #define REV_RT5390F 0x0502
97 #define REV_RT5390R 0x1502
98 #define REV_RT5592C 0x0221
100 #define DEFAULT_RSSI_OFFSET 120
102 /*
103 * Register layout information.
104 */
105 #define CSR_REG_BASE 0x1000
106 #define CSR_REG_SIZE 0x0800
107 #define EEPROM_BASE 0x0000
108 #define EEPROM_SIZE 0x0200
109 #define BBP_BASE 0x0000
110 #define BBP_SIZE 0x00ff
111 #define RF_BASE 0x0004
112 #define RF_SIZE 0x0010
113 #define RFCSR_BASE 0x0000
114 #define RFCSR_SIZE 0x0040
116 /*
117 * Number of TX queues.
118 */
119 #define NUM_TX_QUEUES 4
121 /*
122 * Registers.
123 */
126 /*
127 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
128 */
129 #define MAC_CSR0_3290 0x0000
131 /*
132 * E2PROM_CSR: PCI EEPROM control register.
133 * RELOAD: Write 1 to reload eeprom content.
134 * TYPE: 0: 93c46, 1:93c66.
135 * LOAD_STATUS: 1:loading, 0:done.
136 */
137 #define E2PROM_CSR 0x0004
138 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
139 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
140 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
141 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
142 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
143 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
144 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
146 /*
147 * CMB_CTRL_CFG
148 */
149 #define CMB_CTRL 0x0020
150 #define AUX_OPT_BIT0 FIELD32(0x00000001)
151 #define AUX_OPT_BIT1 FIELD32(0x00000002)
152 #define AUX_OPT_BIT2 FIELD32(0x00000004)
153 #define AUX_OPT_BIT3 FIELD32(0x00000008)
154 #define AUX_OPT_BIT4 FIELD32(0x00000010)
155 #define AUX_OPT_BIT5 FIELD32(0x00000020)
156 #define AUX_OPT_BIT6 FIELD32(0x00000040)
157 #define AUX_OPT_BIT7 FIELD32(0x00000080)
158 #define AUX_OPT_BIT8 FIELD32(0x00000100)
159 #define AUX_OPT_BIT9 FIELD32(0x00000200)
160 #define AUX_OPT_BIT10 FIELD32(0x00000400)
161 #define AUX_OPT_BIT11 FIELD32(0x00000800)
162 #define AUX_OPT_BIT12 FIELD32(0x00001000)
163 #define AUX_OPT_BIT13 FIELD32(0x00002000)
164 #define AUX_OPT_BIT14 FIELD32(0x00004000)
165 #define AUX_OPT_BIT15 FIELD32(0x00008000)
166 #define LDO25_LEVEL FIELD32(0x00030000)
167 #define LDO25_LARGEA FIELD32(0x00040000)
168 #define LDO25_FRC_ON FIELD32(0x00080000)
169 #define CMB_RSV FIELD32(0x00300000)
170 #define XTAL_RDY FIELD32(0x00400000)
171 #define PLL_LD FIELD32(0x00800000)
172 #define LDO_CORE_LEVEL FIELD32(0x0F000000)
173 #define LDO_BGSEL FIELD32(0x30000000)
174 #define LDO3_EN FIELD32(0x40000000)
175 #define LDO0_EN FIELD32(0x80000000)
177 /*
178 * EFUSE_CSR_3290: RT3290 EEPROM
179 */
180 #define EFUSE_CTRL_3290 0x0024
182 /*
183 * EFUSE_DATA3 of 3290
184 */
185 #define EFUSE_DATA3_3290 0x0028
187 /*
188 * EFUSE_DATA2 of 3290
189 */
190 #define EFUSE_DATA2_3290 0x002c
192 /*
193 * EFUSE_DATA1 of 3290
194 */
195 #define EFUSE_DATA1_3290 0x0030
197 /*
198 * EFUSE_DATA0 of 3290
199 */
200 #define EFUSE_DATA0_3290 0x0034
202 /*
203 * OSC_CTRL_CFG
204 * Ring oscillator configuration
205 */
206 #define OSC_CTRL 0x0038
207 #define OSC_REF_CYCLE FIELD32(0x00001fff)
208 #define OSC_RSV FIELD32(0x0000e000)
209 #define OSC_CAL_CNT FIELD32(0x0fff0000)
210 #define OSC_CAL_ACK FIELD32(0x10000000)
211 #define OSC_CLK_32K_VLD FIELD32(0x20000000)
212 #define OSC_CAL_REQ FIELD32(0x40000000)
213 #define OSC_ROSC_EN FIELD32(0x80000000)
215 /*
216 * COEX_CFG_0
217 */
218 #define COEX_CFG0 0x0040
219 #define COEX_CFG_ANT FIELD32(0xff000000)
220 /*
221 * COEX_CFG_1
222 */
223 #define COEX_CFG1 0x0044
225 /*
226 * COEX_CFG_2
227 */
228 #define COEX_CFG2 0x0048
229 #define BT_COEX_CFG1 FIELD32(0xff000000)
230 #define BT_COEX_CFG0 FIELD32(0x00ff0000)
231 #define WL_COEX_CFG1 FIELD32(0x0000ff00)
232 #define WL_COEX_CFG0 FIELD32(0x000000ff)
233 /*
234 * PLL_CTRL_CFG
235 * PLL configuration register
236 */
237 #define PLL_CTRL 0x0050
238 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
239 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
240 #define PLL_CONTROL FIELD32(0x00070000)
241 #define PLL_LPF_R1 FIELD32(0x00080000)
242 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
243 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
244 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
245 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
246 #define PLL_LOCK_CTRL FIELD32(0x70000000)
247 #define PLL_VBGBK_EN FIELD32(0x80000000)
250 /*
251 * WLAN_CTRL_CFG
252 * RT3290 wlan configuration
253 */
254 #define WLAN_FUN_CTRL 0x0080
255 #define WLAN_EN FIELD32(0x00000001)
256 #define WLAN_CLK_EN FIELD32(0x00000002)
257 #define WLAN_RSV1 FIELD32(0x00000004)
258 #define WLAN_RESET FIELD32(0x00000008)
259 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
260 #define FRC_WL_ANT_SET FIELD32(0x00000020)
261 #define INV_TR_SW0 FIELD32(0x00000040)
262 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
263 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
264 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
265 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
266 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
267 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
268 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
269 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
270 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
271 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
272 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
273 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
274 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
275 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
276 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
277 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
278 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
279 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
280 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
281 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
282 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
283 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
284 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
285 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
286 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
287 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
288 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
290 /*
291 * AUX_CTRL: Aux/PCI-E related configuration
292 */
293 #define AUX_CTRL 0x10c
294 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
295 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
297 /*
298 * OPT_14: Unknown register used by rt3xxx devices.
299 */
300 #define OPT_14_CSR 0x0114
301 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
303 /*
304 * INT_SOURCE_CSR: Interrupt source register.
305 * Write one to clear corresponding bit.
306 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
307 */
308 #define INT_SOURCE_CSR 0x0200
309 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
310 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
311 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
312 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
313 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
314 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
315 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
316 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
317 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
318 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
319 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
320 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
321 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
322 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
323 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
324 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
325 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
326 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
328 /*
329 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
330 */
331 #define INT_MASK_CSR 0x0204
332 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
333 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
334 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
335 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
336 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
337 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
338 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
339 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
340 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
341 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
342 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
343 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
344 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
345 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
346 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
347 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
348 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
349 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
351 /*
352 * WPDMA_GLO_CFG
353 */
354 #define WPDMA_GLO_CFG 0x0208
355 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
356 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
357 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
358 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
359 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
360 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
361 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
362 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
363 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
365 /*
366 * WPDMA_RST_IDX
367 */
368 #define WPDMA_RST_IDX 0x020c
369 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
370 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
371 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
372 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
373 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
374 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
375 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
377 /*
378 * DELAY_INT_CFG
379 */
380 #define DELAY_INT_CFG 0x0210
381 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
382 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
383 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
384 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
385 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
386 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
388 /*
389 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
390 * AIFSN0: AC_VO
391 * AIFSN1: AC_VI
392 * AIFSN2: AC_BE
393 * AIFSN3: AC_BK
394 */
395 #define WMM_AIFSN_CFG 0x0214
396 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
397 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
398 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
399 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
401 /*
402 * WMM_CWMIN_CSR: CWmin for each EDCA AC
403 * CWMIN0: AC_VO
404 * CWMIN1: AC_VI
405 * CWMIN2: AC_BE
406 * CWMIN3: AC_BK
407 */
408 #define WMM_CWMIN_CFG 0x0218
409 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
410 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
411 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
412 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
414 /*
415 * WMM_CWMAX_CSR: CWmax for each EDCA AC
416 * CWMAX0: AC_VO
417 * CWMAX1: AC_VI
418 * CWMAX2: AC_BE
419 * CWMAX3: AC_BK
420 */
421 #define WMM_CWMAX_CFG 0x021c
422 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
423 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
424 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
425 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
427 /*
428 * AC_TXOP0: AC_VO/AC_VI TXOP register
429 * AC0TXOP: AC_VO in unit of 32us
430 * AC1TXOP: AC_VI in unit of 32us
431 */
432 #define WMM_TXOP0_CFG 0x0220
433 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
434 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
436 /*
437 * AC_TXOP1: AC_BE/AC_BK TXOP register
438 * AC2TXOP: AC_BE in unit of 32us
439 * AC3TXOP: AC_BK in unit of 32us
440 */
441 #define WMM_TXOP1_CFG 0x0224
442 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
443 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
445 /*
446 * GPIO_CTRL:
447 * GPIO_CTRL_VALx: GPIO value
448 * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
449 */
450 #define GPIO_CTRL 0x0228
451 #define GPIO_CTRL_VAL0 FIELD32(0x00000001)
452 #define GPIO_CTRL_VAL1 FIELD32(0x00000002)
453 #define GPIO_CTRL_VAL2 FIELD32(0x00000004)
454 #define GPIO_CTRL_VAL3 FIELD32(0x00000008)
455 #define GPIO_CTRL_VAL4 FIELD32(0x00000010)
456 #define GPIO_CTRL_VAL5 FIELD32(0x00000020)
457 #define GPIO_CTRL_VAL6 FIELD32(0x00000040)
458 #define GPIO_CTRL_VAL7 FIELD32(0x00000080)
459 #define GPIO_CTRL_DIR0 FIELD32(0x00000100)
460 #define GPIO_CTRL_DIR1 FIELD32(0x00000200)
461 #define GPIO_CTRL_DIR2 FIELD32(0x00000400)
462 #define GPIO_CTRL_DIR3 FIELD32(0x00000800)
463 #define GPIO_CTRL_DIR4 FIELD32(0x00001000)
464 #define GPIO_CTRL_DIR5 FIELD32(0x00002000)
465 #define GPIO_CTRL_DIR6 FIELD32(0x00004000)
466 #define GPIO_CTRL_DIR7 FIELD32(0x00008000)
467 #define GPIO_CTRL_VAL8 FIELD32(0x00010000)
468 #define GPIO_CTRL_VAL9 FIELD32(0x00020000)
469 #define GPIO_CTRL_VAL10 FIELD32(0x00040000)
470 #define GPIO_CTRL_DIR8 FIELD32(0x01000000)
471 #define GPIO_CTRL_DIR9 FIELD32(0x02000000)
472 #define GPIO_CTRL_DIR10 FIELD32(0x04000000)
474 /*
475 * MCU_CMD_CFG
476 */
477 #define MCU_CMD_CFG 0x022c
479 /*
480 * AC_VO register offsets
481 */
482 #define TX_BASE_PTR0 0x0230
483 #define TX_MAX_CNT0 0x0234
484 #define TX_CTX_IDX0 0x0238
485 #define TX_DTX_IDX0 0x023c
487 /*
488 * AC_VI register offsets
489 */
490 #define TX_BASE_PTR1 0x0240
491 #define TX_MAX_CNT1 0x0244
492 #define TX_CTX_IDX1 0x0248
493 #define TX_DTX_IDX1 0x024c
495 /*
496 * AC_BE register offsets
497 */
498 #define TX_BASE_PTR2 0x0250
499 #define TX_MAX_CNT2 0x0254
500 #define TX_CTX_IDX2 0x0258
501 #define TX_DTX_IDX2 0x025c
503 /*
504 * AC_BK register offsets
505 */
506 #define TX_BASE_PTR3 0x0260
507 #define TX_MAX_CNT3 0x0264
508 #define TX_CTX_IDX3 0x0268
509 #define TX_DTX_IDX3 0x026c
511 /*
512 * HCCA register offsets
513 */
514 #define TX_BASE_PTR4 0x0270
515 #define TX_MAX_CNT4 0x0274
516 #define TX_CTX_IDX4 0x0278
517 #define TX_DTX_IDX4 0x027c
519 /*
520 * MGMT register offsets
521 */
522 #define TX_BASE_PTR5 0x0280
523 #define TX_MAX_CNT5 0x0284
524 #define TX_CTX_IDX5 0x0288
525 #define TX_DTX_IDX5 0x028c
527 /*
528 * RX register offsets
529 */
530 #define RX_BASE_PTR 0x0290
531 #define RX_MAX_CNT 0x0294
532 #define RX_CRX_IDX 0x0298
533 #define RX_DRX_IDX 0x029c
535 /*
536 * USB_DMA_CFG
537 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
538 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
539 * PHY_CLEAR: phy watch dog enable.
540 * TX_CLEAR: Clear USB DMA TX path.
541 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
542 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
543 * RX_BULK_EN: Enable USB DMA Rx.
544 * TX_BULK_EN: Enable USB DMA Tx.
545 * EP_OUT_VALID: OUT endpoint data valid.
546 * RX_BUSY: USB DMA RX FSM busy.
547 * TX_BUSY: USB DMA TX FSM busy.
548 */
549 #define USB_DMA_CFG 0x02a0
550 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
551 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
552 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
553 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
554 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
555 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
556 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
557 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
558 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
559 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
560 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
562 /*
563 * US_CYC_CNT
564 * BT_MODE_EN: Bluetooth mode enable
565 * CLOCK CYCLE: Clock cycle count in 1us.
566 * PCI:0x21, PCIE:0x7d, USB:0x1e
567 */
568 #define US_CYC_CNT 0x02a4
569 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
570 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
572 /*
573 * PBF_SYS_CTRL
574 * HOST_RAM_WRITE: enable Host program ram write selection
575 */
576 #define PBF_SYS_CTRL 0x0400
577 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
578 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
580 /*
581 * HOST-MCU shared memory
582 */
583 #define HOST_CMD_CSR 0x0404
584 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
586 /*
587 * PBF registers
588 * Most are for debug. Driver doesn't touch PBF register.
589 */
590 #define PBF_CFG 0x0408
591 #define PBF_MAX_PCNT 0x040c
592 #define PBF_CTRL 0x0410
593 #define PBF_INT_STA 0x0414
594 #define PBF_INT_ENA 0x0418
596 /*
597 * BCN_OFFSET0:
598 */
599 #define BCN_OFFSET0 0x042c
600 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
601 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
602 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
603 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
605 /*
606 * BCN_OFFSET1:
607 */
608 #define BCN_OFFSET1 0x0430
609 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
610 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
611 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
612 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
614 /*
615 * TXRXQ_PCNT: PBF register
616 * PCNT_TX0Q: Page count for TX hardware queue 0
617 * PCNT_TX1Q: Page count for TX hardware queue 1
618 * PCNT_TX2Q: Page count for TX hardware queue 2
619 * PCNT_RX0Q: Page count for RX hardware queue
620 */
621 #define TXRXQ_PCNT 0x0438
622 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
623 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
624 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
625 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
627 /*
628 * PBF register
629 * Debug. Driver doesn't touch PBF register.
630 */
631 #define PBF_DBG 0x043c
633 /*
634 * RF registers
635 */
636 #define RF_CSR_CFG 0x0500
637 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
638 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
639 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
640 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
642 /*
643 * EFUSE_CSR: RT30x0 EEPROM
644 */
645 #define EFUSE_CTRL 0x0580
646 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
647 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
648 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
649 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
651 /*
652 * EFUSE_DATA0
653 */
654 #define EFUSE_DATA0 0x0590
656 /*
657 * EFUSE_DATA1
658 */
659 #define EFUSE_DATA1 0x0594
661 /*
662 * EFUSE_DATA2
663 */
664 #define EFUSE_DATA2 0x0598
666 /*
667 * EFUSE_DATA3
668 */
669 #define EFUSE_DATA3 0x059c
671 /*
672 * LDO_CFG0
673 */
674 #define LDO_CFG0 0x05d4
675 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
676 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
677 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
678 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
679 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
680 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
681 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
683 /*
684 * GPIO_SWITCH
685 */
686 #define GPIO_SWITCH 0x05dc
687 #define GPIO_SWITCH_0 FIELD32(0x00000001)
688 #define GPIO_SWITCH_1 FIELD32(0x00000002)
689 #define GPIO_SWITCH_2 FIELD32(0x00000004)
690 #define GPIO_SWITCH_3 FIELD32(0x00000008)
691 #define GPIO_SWITCH_4 FIELD32(0x00000010)
692 #define GPIO_SWITCH_5 FIELD32(0x00000020)
693 #define GPIO_SWITCH_6 FIELD32(0x00000040)
694 #define GPIO_SWITCH_7 FIELD32(0x00000080)
696 /*
697 * FIXME: where the DEBUG_INDEX name come from?
698 */
699 #define MAC_DEBUG_INDEX 0x05e8
700 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
702 /*
703 * MAC Control/Status Registers(CSR).
704 * Some values are set in TU, whereas 1 TU == 1024 us.
705 */
707 /*
708 * MAC_CSR0: ASIC revision number.
709 * ASIC_REV: 0
710 * ASIC_VER: 2860 or 2870
711 */
712 #define MAC_CSR0 0x1000
713 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
714 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
716 /*
717 * MAC_SYS_CTRL:
718 */
719 #define MAC_SYS_CTRL 0x1004
720 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
721 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
722 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
723 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
724 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
725 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
726 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
727 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
729 /*
730 * MAC_ADDR_DW0: STA MAC register 0
731 */
732 #define MAC_ADDR_DW0 0x1008
733 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
734 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
735 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
736 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
738 /*
739 * MAC_ADDR_DW1: STA MAC register 1
740 * UNICAST_TO_ME_MASK:
741 * Used to mask off bits from byte 5 of the MAC address
742 * to determine the UNICAST_TO_ME bit for RX frames.
743 * The full mask is complemented by BSS_ID_MASK:
744 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
745 */
746 #define MAC_ADDR_DW1 0x100c
747 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
748 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
749 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
751 /*
752 * MAC_BSSID_DW0: BSSID register 0
753 */
754 #define MAC_BSSID_DW0 0x1010
755 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
756 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
757 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
758 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
760 /*
761 * MAC_BSSID_DW1: BSSID register 1
762 * BSS_ID_MASK:
763 * 0: 1-BSSID mode (BSS index = 0)
764 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
765 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
766 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
767 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
768 * BSSID. This will make sure that those bits will be ignored
769 * when determining the MY_BSS of RX frames.
770 */
771 #define MAC_BSSID_DW1 0x1014
772 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
773 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
774 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
775 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
777 /*
778 * MAX_LEN_CFG: Maximum frame length register.
779 * MAX_MPDU: rt2860b max 16k bytes
780 * MAX_PSDU: Maximum PSDU length
781 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
782 */
783 #define MAX_LEN_CFG 0x1018
784 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
785 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
786 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
787 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
789 /*
790 * BBP_CSR_CFG: BBP serial control register
791 * VALUE: Register value to program into BBP
792 * REG_NUM: Selected BBP register
793 * READ_CONTROL: 0 write BBP, 1 read BBP
794 * BUSY: ASIC is busy executing BBP commands
795 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
796 * BBP_RW_MODE: 0 serial, 1 parallel
797 */
798 #define BBP_CSR_CFG 0x101c
799 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
800 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
801 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
802 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
803 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
804 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
806 /*
807 * RF_CSR_CFG0: RF control register
808 * REGID_AND_VALUE: Register value to program into RF
809 * BITWIDTH: Selected RF register
810 * STANDBYMODE: 0 high when standby, 1 low when standby
811 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
812 * BUSY: ASIC is busy executing RF commands
813 */
814 #define RF_CSR_CFG0 0x1020
815 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
816 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
817 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
818 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
819 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
820 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
822 /*
823 * RF_CSR_CFG1: RF control register
824 * REGID_AND_VALUE: Register value to program into RF
825 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
826 * 0: 3 system clock cycle (37.5usec)
827 * 1: 5 system clock cycle (62.5usec)
828 */
829 #define RF_CSR_CFG1 0x1024
830 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
831 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
833 /*
834 * RF_CSR_CFG2: RF control register
835 * VALUE: Register value to program into RF
836 */
837 #define RF_CSR_CFG2 0x1028
838 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
840 /*
841 * LED_CFG: LED control
842 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
843 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
844 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
845 * color LED's:
846 * 0: off
847 * 1: blinking upon TX2
848 * 2: periodic slow blinking
849 * 3: always on
850 * LED polarity:
851 * 0: active low
852 * 1: active high
853 */
854 #define LED_CFG 0x102c
855 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
856 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
857 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
858 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
859 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
860 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
861 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
863 /*
864 * AMPDU_BA_WINSIZE: Force BlockAck window size
865 * FORCE_WINSIZE_ENABLE:
866 * 0: Disable forcing of BlockAck window size
867 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
868 * window size values in the TXWI
869 * FORCE_WINSIZE: BlockAck window size
870 */
871 #define AMPDU_BA_WINSIZE 0x1040
872 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
873 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
875 /*
876 * XIFS_TIME_CFG: MAC timing
877 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
878 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
879 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
880 * when MAC doesn't reference BBP signal BBRXEND
881 * EIFS: unit 1us
882 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
883 *
884 */
885 #define XIFS_TIME_CFG 0x1100
886 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
887 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
888 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
889 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
890 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
892 /*
893 * BKOFF_SLOT_CFG:
894 */
895 #define BKOFF_SLOT_CFG 0x1104
896 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
897 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
899 /*
900 * NAV_TIME_CFG:
901 */
902 #define NAV_TIME_CFG 0x1108
903 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
904 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
905 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
906 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
908 /*
909 * CH_TIME_CFG: count as channel busy
910 * EIFS_BUSY: Count EIFS as channel busy
911 * NAV_BUSY: Count NAS as channel busy
912 * RX_BUSY: Count RX as channel busy
913 * TX_BUSY: Count TX as channel busy
914 * TMR_EN: Enable channel statistics timer
915 */
916 #define CH_TIME_CFG 0x110c
917 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
918 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
919 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
920 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
921 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
923 /*
924 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
925 */
926 #define PBF_LIFE_TIMER 0x1110
928 /*
929 * BCN_TIME_CFG:
930 * BEACON_INTERVAL: in unit of 1/16 TU
931 * TSF_TICKING: Enable TSF auto counting
932 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
933 * BEACON_GEN: Enable beacon generator
934 */
935 #define BCN_TIME_CFG 0x1114
936 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
937 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
938 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
939 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
940 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
941 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
943 /*
944 * TBTT_SYNC_CFG:
945 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
946 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
947 */
948 #define TBTT_SYNC_CFG 0x1118
949 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
950 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
951 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
952 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
954 /*
955 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
956 */
957 #define TSF_TIMER_DW0 0x111c
958 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
960 /*
961 * TSF_TIMER_DW1: Local msb TSF timer, read-only
962 */
963 #define TSF_TIMER_DW1 0x1120
964 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
966 /*
967 * TBTT_TIMER: TImer remains till next TBTT, read-only
968 */
969 #define TBTT_TIMER 0x1124
971 /*
972 * INT_TIMER_CFG: timer configuration
973 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
974 * GP_TIMER: period of general purpose timer in units of 1/16 TU
975 */
976 #define INT_TIMER_CFG 0x1128
977 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
978 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
980 /*
981 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
982 */
983 #define INT_TIMER_EN 0x112c
984 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
985 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
987 /*
988 * CH_IDLE_STA: channel idle time (in us)
989 */
990 #define CH_IDLE_STA 0x1130
992 /*
993 * CH_BUSY_STA: channel busy time on primary channel (in us)
994 */
995 #define CH_BUSY_STA 0x1134
997 /*
998 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
999 */
1000 #define CH_BUSY_STA_SEC 0x1138
1002 /*
1003 * MAC_STATUS_CFG:
1004 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
1005 * if 1 or higher one of the 2 registers is busy.
1006 */
1007 #define MAC_STATUS_CFG 0x1200
1008 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1010 /*
1011 * PWR_PIN_CFG:
1012 */
1013 #define PWR_PIN_CFG 0x1204
1015 /*
1016 * AUTOWAKEUP_CFG: Manual power control / status register
1017 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
1018 * AUTOWAKE: 0:sleep, 1:awake
1019 */
1020 #define AUTOWAKEUP_CFG 0x1208
1021 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1022 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1023 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1025 /*
1026 * EDCA_AC0_CFG:
1027 */
1028 #define EDCA_AC0_CFG 0x1300
1029 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1030 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1031 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1032 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1034 /*
1035 * EDCA_AC1_CFG:
1036 */
1037 #define EDCA_AC1_CFG 0x1304
1038 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1039 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1040 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1041 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1043 /*
1044 * EDCA_AC2_CFG:
1045 */
1046 #define EDCA_AC2_CFG 0x1308
1047 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1048 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1049 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1050 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1052 /*
1053 * EDCA_AC3_CFG:
1054 */
1055 #define EDCA_AC3_CFG 0x130c
1056 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1057 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1058 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1059 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1061 /*
1062 * EDCA_TID_AC_MAP:
1063 */
1064 #define EDCA_TID_AC_MAP 0x1310
1066 /*
1067 * TX_PWR_CFG:
1068 */
1069 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1070 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1071 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1072 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1073 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1074 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1075 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1076 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1078 /*
1079 * TX_PWR_CFG_0:
1080 */
1081 #define TX_PWR_CFG_0 0x1314
1082 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1083 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1084 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1085 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1086 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1087 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1088 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1089 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1090 /* bits for 3T devices */
1091 #define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
1092 #define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
1093 #define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
1094 #define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
1095 #define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
1096 #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
1097 #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
1098 #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
1100 /*
1101 * TX_PWR_CFG_1:
1102 */
1103 #define TX_PWR_CFG_1 0x1318
1104 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1105 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1106 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1107 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1108 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1109 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1110 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1111 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1112 /* bits for 3T devices */
1113 #define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
1114 #define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
1115 #define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
1116 #define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
1117 #define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
1118 #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
1119 #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
1120 #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
1122 /*
1123 * TX_PWR_CFG_2:
1124 */
1125 #define TX_PWR_CFG_2 0x131c
1126 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1127 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1128 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1129 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1130 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1131 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1132 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1133 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1134 /* bits for 3T devices */
1135 #define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
1136 #define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
1137 #define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
1138 #define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
1139 #define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
1140 #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
1141 #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
1142 #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
1144 /*
1145 * TX_PWR_CFG_3:
1146 */
1147 #define TX_PWR_CFG_3 0x1320
1148 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1149 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1150 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1151 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1152 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
1153 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
1154 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
1155 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
1156 /* bits for 3T devices */
1157 #define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
1158 #define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
1159 #define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
1160 #define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
1161 #define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
1162 #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
1163 #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
1164 #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
1166 /*
1167 * TX_PWR_CFG_4:
1168 */
1169 #define TX_PWR_CFG_4 0x1324
1170 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
1171 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
1172 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
1173 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
1174 /* bits for 3T devices */
1175 #define TX_PWR_CFG_3_STBC4_CH0 FIELD32(0x0000000f)
1176 #define TX_PWR_CFG_3_STBC4_CH1 FIELD32(0x000000f0)
1177 #define TX_PWR_CFG_3_STBC6_CH0 FIELD32(0x00000f00)
1178 #define TX_PWR_CFG_3_STBC6_CH1 FIELD32(0x0000f000)
1180 /*
1181 * TX_PIN_CFG:
1182 */
1183 #define TX_PIN_CFG 0x1328
1184 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
1185 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1186 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1187 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1188 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1189 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1190 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1191 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1192 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1193 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1194 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1195 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1196 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1197 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1198 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1199 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1200 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1201 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1202 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1203 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1204 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1205 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1206 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1207 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1208 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1209 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1210 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1211 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1212 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1214 /*
1215 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1216 */
1217 #define TX_BAND_CFG 0x132c
1218 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1219 #define TX_BAND_CFG_A FIELD32(0x00000002)
1220 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1222 /*
1223 * TX_SW_CFG0:
1224 */
1225 #define TX_SW_CFG0 0x1330
1227 /*
1228 * TX_SW_CFG1:
1229 */
1230 #define TX_SW_CFG1 0x1334
1232 /*
1233 * TX_SW_CFG2:
1234 */
1235 #define TX_SW_CFG2 0x1338
1237 /*
1238 * TXOP_THRES_CFG:
1239 */
1240 #define TXOP_THRES_CFG 0x133c
1242 /*
1243 * TXOP_CTRL_CFG:
1244 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1245 * AC_TRUN_EN: Enable/Disable truncation for AC change
1246 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1247 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1248 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1249 * RESERVED_TRUN_EN: Reserved
1250 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1251 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1252 * transmissions if extension CCA is clear).
1253 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1254 * EXT_CWMIN: CwMin for extension channel backoff
1255 * 0: Disabled
1256 *
1257 */
1258 #define TXOP_CTRL_CFG 0x1340
1259 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1260 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1261 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1262 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1263 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1264 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1265 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1266 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1267 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1268 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1270 /*
1271 * TX_RTS_CFG:
1272 * RTS_THRES: unit:byte
1273 * RTS_FBK_EN: enable rts rate fallback
1274 */
1275 #define TX_RTS_CFG 0x1344
1276 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1277 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1278 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1280 /*
1281 * TX_TIMEOUT_CFG:
1282 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1283 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1284 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1285 * it is recommended that:
1286 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1287 */
1288 #define TX_TIMEOUT_CFG 0x1348
1289 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1290 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1291 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1293 /*
1294 * TX_RTY_CFG:
1295 * SHORT_RTY_LIMIT: short retry limit
1296 * LONG_RTY_LIMIT: long retry limit
1297 * LONG_RTY_THRE: Long retry threshoold
1298 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1299 * 0:expired by retry limit, 1: expired by mpdu life timer
1300 * AGG_RTY_MODE: Aggregate MPDU retry mode
1301 * 0:expired by retry limit, 1: expired by mpdu life timer
1302 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1303 */
1304 #define TX_RTY_CFG 0x134c
1305 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1306 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1307 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1308 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1309 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1310 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1312 /*
1313 * TX_LINK_CFG:
1314 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1315 * MFB_ENABLE: TX apply remote MFB 1:enable
1316 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1317 * 0: not apply remote remote unsolicit (MFS=7)
1318 * TX_MRQ_EN: MCS request TX enable
1319 * TX_RDG_EN: RDG TX enable
1320 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1321 * REMOTE_MFB: remote MCS feedback
1322 * REMOTE_MFS: remote MCS feedback sequence number
1323 */
1324 #define TX_LINK_CFG 0x1350
1325 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1326 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1327 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1328 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1329 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1330 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1331 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1332 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1334 /*
1335 * HT_FBK_CFG0:
1336 */
1337 #define HT_FBK_CFG0 0x1354
1338 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1339 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1340 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1341 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1342 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1343 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1344 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1345 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1347 /*
1348 * HT_FBK_CFG1:
1349 */
1350 #define HT_FBK_CFG1 0x1358
1351 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1352 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1353 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1354 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1355 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1356 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1357 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1358 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1360 /*
1361 * LG_FBK_CFG0:
1362 */
1363 #define LG_FBK_CFG0 0x135c
1364 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1365 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1366 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1367 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1368 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1369 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1370 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1371 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1373 /*
1374 * LG_FBK_CFG1:
1375 */
1376 #define LG_FBK_CFG1 0x1360
1377 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1378 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1379 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1380 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1382 /*
1383 * CCK_PROT_CFG: CCK Protection
1384 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1385 * PROTECT_CTRL: Protection control frame type for CCK TX
1386 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1387 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1388 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1389 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1390 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1391 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1392 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1393 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1394 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1395 * RTS_TH_EN: RTS threshold enable on CCK TX
1396 */
1397 #define CCK_PROT_CFG 0x1364
1398 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1399 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1400 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1401 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1402 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1403 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1404 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1405 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1406 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1407 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1408 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1410 /*
1411 * OFDM_PROT_CFG: OFDM Protection
1412 */
1413 #define OFDM_PROT_CFG 0x1368
1414 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1415 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1416 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1417 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1418 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1419 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1420 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1421 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1422 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1423 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1424 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1426 /*
1427 * MM20_PROT_CFG: MM20 Protection
1428 */
1429 #define MM20_PROT_CFG 0x136c
1430 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1431 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1432 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1433 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1434 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1435 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1436 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1437 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1438 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1439 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1440 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1442 /*
1443 * MM40_PROT_CFG: MM40 Protection
1444 */
1445 #define MM40_PROT_CFG 0x1370
1446 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1447 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1448 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1449 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1450 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1451 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1452 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1453 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1454 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1455 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1456 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1458 /*
1459 * GF20_PROT_CFG: GF20 Protection
1460 */
1461 #define GF20_PROT_CFG 0x1374
1462 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1463 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1464 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1465 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1466 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1467 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1468 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1469 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1470 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1471 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1472 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1474 /*
1475 * GF40_PROT_CFG: GF40 Protection
1476 */
1477 #define GF40_PROT_CFG 0x1378
1478 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1479 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1480 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1481 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1482 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1483 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1484 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1485 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1486 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1487 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1488 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1490 /*
1491 * EXP_CTS_TIME:
1492 */
1493 #define EXP_CTS_TIME 0x137c
1495 /*
1496 * EXP_ACK_TIME:
1497 */
1498 #define EXP_ACK_TIME 0x1380
1500 /* TX_PWR_CFG_5 */
1501 #define TX_PWR_CFG_5 0x1384
1502 #define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
1503 #define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
1504 #define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
1505 #define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
1506 #define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
1507 #define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
1509 /* TX_PWR_CFG_6 */
1510 #define TX_PWR_CFG_6 0x1388
1511 #define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
1512 #define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
1513 #define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
1514 #define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
1515 #define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
1516 #define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
1518 /* TX_PWR_CFG_0_EXT */
1519 #define TX_PWR_CFG_0_EXT 0x1390
1520 #define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
1521 #define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
1522 #define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
1523 #define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
1525 /* TX_PWR_CFG_1_EXT */
1526 #define TX_PWR_CFG_1_EXT 0x1394
1527 #define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
1528 #define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
1529 #define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
1530 #define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
1532 /* TX_PWR_CFG_2_EXT */
1533 #define TX_PWR_CFG_2_EXT 0x1398
1534 #define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
1535 #define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
1536 #define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
1537 #define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
1539 /* TX_PWR_CFG_3_EXT */
1540 #define TX_PWR_CFG_3_EXT 0x139c
1541 #define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
1542 #define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
1543 #define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
1544 #define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
1546 /* TX_PWR_CFG_4_EXT */
1547 #define TX_PWR_CFG_4_EXT 0x13a0
1548 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
1549 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
1551 /* TX_PWR_CFG_7 */
1552 #define TX_PWR_CFG_7 0x13d4
1553 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
1554 #define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
1555 #define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
1556 #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
1557 #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
1558 #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
1560 /* TX_PWR_CFG_8 */
1561 #define TX_PWR_CFG_8 0x13d8
1562 #define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
1563 #define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
1564 #define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
1565 #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
1566 #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
1567 #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
1569 /* TX_PWR_CFG_9 */
1570 #define TX_PWR_CFG_9 0x13dc
1571 #define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
1572 #define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
1573 #define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
1575 /*
1576 * RX_FILTER_CFG: RX configuration register.
1577 */
1578 #define RX_FILTER_CFG 0x1400
1579 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1580 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1581 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1582 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1583 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1584 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1585 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1586 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1587 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1588 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1589 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1590 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1591 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1592 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1593 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1594 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1595 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1597 /*
1598 * AUTO_RSP_CFG:
1599 * AUTORESPONDER: 0: disable, 1: enable
1600 * BAC_ACK_POLICY: 0:long, 1:short preamble
1601 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1602 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1603 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1604 * DUAL_CTS_EN: Power bit value in control frame
1605 * ACK_CTS_PSM_BIT:Power bit value in control frame
1606 */
1607 #define AUTO_RSP_CFG 0x1404
1608 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1609 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1610 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1611 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1612 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1613 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1614 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1616 /*
1617 * LEGACY_BASIC_RATE:
1618 */
1619 #define LEGACY_BASIC_RATE 0x1408
1621 /*
1622 * HT_BASIC_RATE:
1623 */
1624 #define HT_BASIC_RATE 0x140c
1626 /*
1627 * HT_CTRL_CFG:
1628 */
1629 #define HT_CTRL_CFG 0x1410
1631 /*
1632 * SIFS_COST_CFG:
1633 */
1634 #define SIFS_COST_CFG 0x1414
1636 /*
1637 * RX_PARSER_CFG:
1638 * Set NAV for all received frames
1639 */
1640 #define RX_PARSER_CFG 0x1418
1642 /*
1643 * TX_SEC_CNT0:
1644 */
1645 #define TX_SEC_CNT0 0x1500
1647 /*
1648 * RX_SEC_CNT0:
1649 */
1650 #define RX_SEC_CNT0 0x1504
1652 /*
1653 * CCMP_FC_MUTE:
1654 */
1655 #define CCMP_FC_MUTE 0x1508
1657 /*
1658 * TXOP_HLDR_ADDR0:
1659 */
1660 #define TXOP_HLDR_ADDR0 0x1600
1662 /*
1663 * TXOP_HLDR_ADDR1:
1664 */
1665 #define TXOP_HLDR_ADDR1 0x1604
1667 /*
1668 * TXOP_HLDR_ET:
1669 */
1670 #define TXOP_HLDR_ET 0x1608
1672 /*
1673 * QOS_CFPOLL_RA_DW0:
1674 */
1675 #define QOS_CFPOLL_RA_DW0 0x160c
1677 /*
1678 * QOS_CFPOLL_RA_DW1:
1679 */
1680 #define QOS_CFPOLL_RA_DW1 0x1610
1682 /*
1683 * QOS_CFPOLL_QC:
1684 */
1685 #define QOS_CFPOLL_QC 0x1614
1687 /*
1688 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1689 */
1690 #define RX_STA_CNT0 0x1700
1691 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1692 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1694 /*
1695 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1696 */
1697 #define RX_STA_CNT1 0x1704
1698 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1699 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1701 /*
1702 * RX_STA_CNT2:
1703 */
1704 #define RX_STA_CNT2 0x1708
1705 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1706 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1708 /*
1709 * TX_STA_CNT0: TX Beacon count
1710 */
1711 #define TX_STA_CNT0 0x170c
1712 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1713 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1715 /*
1716 * TX_STA_CNT1: TX tx count
1717 */
1718 #define TX_STA_CNT1 0x1710
1719 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1720 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1722 /*
1723 * TX_STA_CNT2: TX tx count
1724 */
1725 #define TX_STA_CNT2 0x1714
1726 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1727 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1729 /*
1730 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1731 *
1732 * This register is implemented as FIFO with 16 entries in the HW. Each
1733 * register read fetches the next tx result. If the FIFO is full because
1734 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1735 * triggered, the hw seems to simply drop further tx results.
1736 *
1737 * VALID: 1: this tx result is valid
1738 * 0: no valid tx result -> driver should stop reading
1739 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1740 * to match a frame with its tx result (even though the PID is
1741 * only 4 bits wide).
1742 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1743 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1744 * This identification number is calculated by ((idx % 3) + 1).
1745 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1746 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1747 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1748 * WCID: The wireless client ID.
1749 * MCS: The tx rate used during the last transmission of this frame, be it
1750 * successful or not.
1751 * PHYMODE: The phymode used for the transmission.
1752 */
1753 #define TX_STA_FIFO 0x1718
1754 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1755 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1756 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1757 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1758 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1759 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1760 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1761 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1762 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1763 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1764 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1766 /*
1767 * TX_AGG_CNT: Debug counter
1768 */
1769 #define TX_AGG_CNT 0x171c
1770 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1771 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1773 /*
1774 * TX_AGG_CNT0:
1775 */
1776 #define TX_AGG_CNT0 0x1720
1777 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1778 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1780 /*
1781 * TX_AGG_CNT1:
1782 */
1783 #define TX_AGG_CNT1 0x1724
1784 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1785 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1787 /*
1788 * TX_AGG_CNT2:
1789 */
1790 #define TX_AGG_CNT2 0x1728
1791 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1792 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1794 /*
1795 * TX_AGG_CNT3:
1796 */
1797 #define TX_AGG_CNT3 0x172c
1798 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1799 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1801 /*
1802 * TX_AGG_CNT4:
1803 */
1804 #define TX_AGG_CNT4 0x1730
1805 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1806 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1808 /*
1809 * TX_AGG_CNT5:
1810 */
1811 #define TX_AGG_CNT5 0x1734
1812 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1813 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1815 /*
1816 * TX_AGG_CNT6:
1817 */
1818 #define TX_AGG_CNT6 0x1738
1819 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1820 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1822 /*
1823 * TX_AGG_CNT7:
1824 */
1825 #define TX_AGG_CNT7 0x173c
1826 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1827 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1829 /*
1830 * MPDU_DENSITY_CNT:
1831 * TX_ZERO_DEL: TX zero length delimiter count
1832 * RX_ZERO_DEL: RX zero length delimiter count
1833 */
1834 #define MPDU_DENSITY_CNT 0x1740
1835 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1836 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1838 /*
1839 * Security key table memory.
1840 *
1841 * The pairwise key table shares some memory with the beacon frame
1842 * buffers 6 and 7. That basically means that when beacon 6 & 7
1843 * are used we should only use the reduced pairwise key table which
1844 * has a maximum of 222 entries.
1845 *
1846 * ---------------------------------------------
1847 * |0x4000 | Pairwise Key | Reduced Pairwise |
1848 * | | Table | Key Table |
1849 * | | Size: 256 * 32 | Size: 222 * 32 |
1850 * |0x5BC0 | |-------------------
1851 * | | | Beacon 6 |
1852 * |0x5DC0 | |-------------------
1853 * | | | Beacon 7 |
1854 * |0x5FC0 | |-------------------
1855 * |0x5FFF | |
1856 * --------------------------
1857 *
1858 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1859 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1860 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1861 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1862 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1863 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1864 */
1865 #define MAC_WCID_BASE 0x1800
1866 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1867 #define MAC_IVEIV_TABLE_BASE 0x6000
1868 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1869 #define SHARED_KEY_TABLE_BASE 0x6c00
1870 #define SHARED_KEY_MODE_BASE 0x7000
1872 #define MAC_WCID_ENTRY(__idx) \
1873 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1874 #define PAIRWISE_KEY_ENTRY(__idx) \
1875 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1876 #define MAC_IVEIV_ENTRY(__idx) \
1877 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1878 #define MAC_WCID_ATTR_ENTRY(__idx) \
1879 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1880 #define SHARED_KEY_ENTRY(__idx) \
1881 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1882 #define SHARED_KEY_MODE_ENTRY(__idx) \
1883 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1900 /*
1901 * MAC_WCID_ATTRIBUTE:
1902 */
1903 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1904 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1905 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1906 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1907 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1908 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1909 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1910 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1912 /*
1913 * SHARED_KEY_MODE:
1914 */
1915 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1916 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1917 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1918 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1919 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1920 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1921 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1922 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1924 /*
1925 * HOST-MCU communication
1926 */
1928 /*
1929 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1930 * CMD_TOKEN: Command id, 0xff disable status reporting.
1931 */
1932 #define H2M_MAILBOX_CSR 0x7010
1933 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1934 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1935 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1936 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1938 /*
1939 * H2M_MAILBOX_CID:
1940 * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1941 * If all slots are occupied status will be dropped.
1942 */
1943 #define H2M_MAILBOX_CID 0x7014
1944 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1945 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1946 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1947 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1949 /*
1950 * H2M_MAILBOX_STATUS:
1951 * Command status will be saved to same slot as command id.
1952 */
1953 #define H2M_MAILBOX_STATUS 0x701c
1955 /*
1956 * H2M_INT_SRC:
1957 */
1958 #define H2M_INT_SRC 0x7024
1960 /*
1961 * H2M_BBP_AGENT:
1962 */
1963 #define H2M_BBP_AGENT 0x7028
1965 /*
1966 * MCU_LEDCS: LED control for MCU Mailbox.
1967 */
1968 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1969 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1971 /*
1972 * HW_CS_CTS_BASE:
1973 * Carrier-sense CTS frame base address.
1974 * It's where mac stores carrier-sense frame for carrier-sense function.
1975 */
1976 #define HW_CS_CTS_BASE 0x7700
1978 /*
1979 * HW_DFS_CTS_BASE:
1980 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1981 */
1982 #define HW_DFS_CTS_BASE 0x7780
1984 /*
1985 * TXRX control registers - base address 0x3000
1986 */
1988 /*
1989 * TXRX_CSR1:
1990 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1991 */
1992 #define TXRX_CSR1 0x77d0
1994 /*
1995 * HW_DEBUG_SETTING_BASE:
1996 * since NULL frame won't be that long (256 byte)
1997 * We steal 16 tail bytes to save debugging settings
1998 */
1999 #define HW_DEBUG_SETTING_BASE 0x77f0
2000 #define HW_DEBUG_SETTING_BASE2 0x7770
2002 /*
2003 * HW_BEACON_BASE
2004 * In order to support maximum 8 MBSS and its maximum length
2005 * is 512 bytes for each beacon
2006 * Three section discontinue memory segments will be used.
2007 * 1. The original region for BCN 0~3
2008 * 2. Extract memory from FCE table for BCN 4~5
2009 * 3. Extract memory from Pair-wise key table for BCN 6~7
2010 * It occupied those memory of wcid 238~253 for BCN 6
2011 * and wcid 222~237 for BCN 7 (see Security key table memory
2012 * for more info).
2013 *
2014 * IMPORTANT NOTE: Not sure why legacy driver does this,
2015 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
2016 */
2017 #define HW_BEACON_BASE0 0x7800
2018 #define HW_BEACON_BASE1 0x7a00
2019 #define HW_BEACON_BASE2 0x7c00
2020 #define HW_BEACON_BASE3 0x7e00
2021 #define HW_BEACON_BASE4 0x7200
2022 #define HW_BEACON_BASE5 0x7400
2023 #define HW_BEACON_BASE6 0x5dc0
2024 #define HW_BEACON_BASE7 0x5bc0
2026 #define HW_BEACON_BASE(__index) \
2027 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
2028 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
2029 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
2031 #define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64)
2033 /*
2034 * BBP registers.
2035 * The wordsize of the BBP is 8 bits.
2036 */
2038 /*
2039 * BBP 1: TX Antenna & Power Control
2040 * POWER_CTRL:
2041 * 0 - normal,
2042 * 1 - drop tx power by 6dBm,
2043 * 2 - drop tx power by 12dBm,
2044 * 3 - increase tx power by 6dBm
2045 */
2046 #define BBP1_TX_POWER_CTRL FIELD8(0x03)
2047 #define BBP1_TX_ANTENNA FIELD8(0x18)
2049 /*
2050 * BBP 3: RX Antenna
2051 */
2052 #define BBP3_RX_ADC FIELD8(0x03)
2053 #define BBP3_RX_ANTENNA FIELD8(0x18)
2054 #define BBP3_HT40_MINUS FIELD8(0x20)
2055 #define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
2056 #define BBP3_ADC_INIT_MODE FIELD8(0x80)
2058 /*
2059 * BBP 4: Bandwidth
2060 */
2061 #define BBP4_TX_BF FIELD8(0x01)
2062 #define BBP4_BANDWIDTH FIELD8(0x18)
2063 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
2065 /* BBP27 */
2066 #define BBP27_RX_CHAIN_SEL FIELD8(0x60)
2068 /*
2069 * BBP 47: Bandwidth
2070 */
2071 #define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
2072 #define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
2073 #define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
2074 #define BBP47_TSSI_ADC6 FIELD8(0x80)
2076 /*
2077 * BBP 49
2078 */
2079 #define BBP49_UPDATE_FLAG FIELD8(0x01)
2081 /*
2082 * BBP 105:
2083 * - bit0: detect SIG on primary channel only (on 40MHz bandwidth)
2084 * - bit1: FEQ (Feed Forward Compensation) for independend streams
2085 * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single
2086 * stream)
2087 * - bit4: channel estimation updates based on remodulation of
2088 * L-SIG and HT-SIG symbols
2089 */
2090 #define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01)
2091 #define BBP105_FEQ FIELD8(0x02)
2092 #define BBP105_MLD FIELD8(0x04)
2093 #define BBP105_SIG_REMODULATION FIELD8(0x08)
2095 /*
2096 * BBP 109
2097 */
2098 #define BBP109_TX0_POWER FIELD8(0x0f)
2099 #define BBP109_TX1_POWER FIELD8(0xf0)
2101 /* BBP 110 */
2102 #define BBP110_TX2_POWER FIELD8(0x0f)
2105 /*
2106 * BBP 138: Unknown
2107 */
2108 #define BBP138_RX_ADC1 FIELD8(0x02)
2109 #define BBP138_RX_ADC2 FIELD8(0x04)
2110 #define BBP138_TX_DAC1 FIELD8(0x20)
2111 #define BBP138_TX_DAC2 FIELD8(0x40)
2113 /*
2114 * BBP 152: Rx Ant
2115 */
2116 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
2118 /*
2119 * BBP 254: unknown
2120 */
2121 #define BBP254_BIT7 FIELD8(0x80)
2123 /*
2124 * RFCSR registers
2125 * The wordsize of the RFCSR is 8 bits.
2126 */
2128 /*
2129 * RFCSR 1:
2130 */
2131 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
2132 #define RFCSR1_PLL_PD FIELD8(0x02)
2133 #define RFCSR1_RX0_PD FIELD8(0x04)
2134 #define RFCSR1_TX0_PD FIELD8(0x08)
2135 #define RFCSR1_RX1_PD FIELD8(0x10)
2136 #define RFCSR1_TX1_PD FIELD8(0x20)
2137 #define RFCSR1_RX2_PD FIELD8(0x40)
2138 #define RFCSR1_TX2_PD FIELD8(0x80)
2140 /*
2141 * RFCSR 2:
2142 */
2143 #define RFCSR2_RESCAL_EN FIELD8(0x80)
2145 /*
2146 * RFCSR 3:
2147 */
2148 #define RFCSR3_K FIELD8(0x0f)
2149 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
2150 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70)
2151 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80)
2152 /* Bits for RF3290/RF5360/RF5362/RF5370/RF5372/RF5390/RF5392 */
2153 #define RFCSR3_VCOCAL_EN FIELD8(0x80)
2154 /* Bits for RF3050 */
2155 #define RFCSR3_BIT1 FIELD8(0x02)
2156 #define RFCSR3_BIT2 FIELD8(0x04)
2157 #define RFCSR3_BIT3 FIELD8(0x08)
2158 #define RFCSR3_BIT4 FIELD8(0x10)
2159 #define RFCSR3_BIT5 FIELD8(0x20)
2161 /*
2162 * FRCSR 5:
2163 */
2164 #define RFCSR5_R1 FIELD8(0x0c)
2166 /*
2167 * RFCSR 6:
2168 */
2169 #define RFCSR6_R1 FIELD8(0x03)
2170 #define RFCSR6_R2 FIELD8(0x40)
2171 #define RFCSR6_TXDIV FIELD8(0x0c)
2172 /* bits for RF3053 */
2173 #define RFCSR6_VCO_IC FIELD8(0xc0)
2175 /*
2176 * RFCSR 7:
2177 */
2178 #define RFCSR7_RF_TUNING FIELD8(0x01)
2179 #define RFCSR7_BIT1 FIELD8(0x02)
2180 #define RFCSR7_BIT2 FIELD8(0x04)
2181 #define RFCSR7_BIT3 FIELD8(0x08)
2182 #define RFCSR7_BIT4 FIELD8(0x10)
2183 #define RFCSR7_BIT5 FIELD8(0x20)
2184 #define RFCSR7_BITS67 FIELD8(0xc0)
2186 /*
2187 * RFCSR 9:
2188 */
2189 #define RFCSR9_K FIELD8(0x0f)
2190 #define RFCSR9_N FIELD8(0x10)
2191 #define RFCSR9_UNKNOWN FIELD8(0x60)
2192 #define RFCSR9_MOD FIELD8(0x80)
2194 /*
2195 * RFCSR 11:
2196 */
2197 #define RFCSR11_R FIELD8(0x03)
2198 #define RFCSR11_PLL_MOD FIELD8(0x0c)
2199 #define RFCSR11_MOD FIELD8(0xc0)
2200 /* bits for RF3053 */
2201 /* TODO: verify RFCSR11_MOD usage on other chips */
2202 #define RFCSR11_PLL_IDOH FIELD8(0x40)
2205 /*
2206 * RFCSR 12:
2207 */
2208 #define RFCSR12_TX_POWER FIELD8(0x1f)
2209 #define RFCSR12_DR0 FIELD8(0xe0)
2211 /*
2212 * RFCSR 13:
2213 */
2214 #define RFCSR13_TX_POWER FIELD8(0x1f)
2215 #define RFCSR13_DR0 FIELD8(0xe0)
2217 /*
2218 * RFCSR 15:
2219 */
2220 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
2222 /*
2223 * RFCSR 16:
2224 */
2225 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2227 /*
2228 * RFCSR 17:
2229 */
2230 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
2231 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
2232 #define RFCSR17_R FIELD8(0x20)
2233 #define RFCSR17_CODE FIELD8(0x7f)
2235 /* RFCSR 18 */
2236 #define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40)
2239 /*
2240 * RFCSR 20:
2241 */
2242 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
2244 /*
2245 * RFCSR 21:
2246 */
2247 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
2249 /*
2250 * RFCSR 22:
2251 */
2252 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2254 /*
2255 * RFCSR 23:
2256 */
2257 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
2259 /*
2260 * RFCSR 24:
2261 */
2262 #define RFCSR24_TX_AGC_FC FIELD8(0x1f)
2263 #define RFCSR24_TX_H20M FIELD8(0x20)
2264 #define RFCSR24_TX_CALIB FIELD8(0x7f)
2266 /*
2267 * RFCSR 27:
2268 */
2269 #define RFCSR27_R1 FIELD8(0x03)
2270 #define RFCSR27_R2 FIELD8(0x04)
2271 #define RFCSR27_R3 FIELD8(0x30)
2272 #define RFCSR27_R4 FIELD8(0x40)
2274 /*
2275 * RFCSR 29:
2276 */
2277 #define RFCSR29_ADC6_TEST FIELD8(0x01)
2278 #define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2279 #define RFCSR29_RSSI_RESET FIELD8(0x04)
2280 #define RFCSR29_RSSI_ON FIELD8(0x08)
2281 #define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2282 #define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2284 /*
2285 * RFCSR 30:
2286 */
2287 #define RFCSR30_TX_H20M FIELD8(0x02)
2288 #define RFCSR30_RX_H20M FIELD8(0x04)
2289 #define RFCSR30_RX_VCM FIELD8(0x18)
2290 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
2292 /*
2293 * RFCSR 31:
2294 */
2295 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
2296 #define RFCSR31_RX_H20M FIELD8(0x20)
2297 #define RFCSR31_RX_CALIB FIELD8(0x7f)
2299 /* RFCSR 32 bits for RF3053 */
2300 #define RFCSR32_TX_AGC_FC FIELD8(0xf8)
2302 /* RFCSR 36 bits for RF3053 */
2303 #define RFCSR36_RF_BS FIELD8(0x80)
2305 /*
2306 * RFCSR 38:
2307 */
2308 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
2310 /*
2311 * RFCSR 39:
2312 */
2313 #define RFCSR39_RX_DIV FIELD8(0x40)
2314 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
2316 /*
2317 * RFCSR 49:
2318 */
2319 #define RFCSR49_TX FIELD8(0x3f)
2320 #define RFCSR49_EP FIELD8(0xc0)
2321 /* bits for RT3593 */
2322 #define RFCSR49_TX_LO1_IC FIELD8(0x1c)
2323 #define RFCSR49_TX_DIV FIELD8(0x20)
2325 /*
2326 * RFCSR 50:
2327 */
2328 #define RFCSR50_TX FIELD8(0x3f)
2329 #define RFCSR50_EP FIELD8(0xc0)
2330 /* bits for RT3593 */
2331 #define RFCSR50_TX_LO1_EN FIELD8(0x20)
2332 #define RFCSR50_TX_LO2_EN FIELD8(0x10)
2334 /* RFCSR 51 */
2335 /* bits for RT3593 */
2336 #define RFCSR51_BITS01 FIELD8(0x03)
2337 #define RFCSR51_BITS24 FIELD8(0x1c)
2338 #define RFCSR51_BITS57 FIELD8(0xe0)
2340 #define RFCSR53_TX_POWER FIELD8(0x3f)
2341 #define RFCSR53_UNKNOWN FIELD8(0xc0)
2343 #define RFCSR54_TX_POWER FIELD8(0x3f)
2344 #define RFCSR54_UNKNOWN FIELD8(0xc0)
2346 #define RFCSR55_TX_POWER FIELD8(0x3f)
2347 #define RFCSR55_UNKNOWN FIELD8(0xc0)
2349 #define RFCSR57_DRV_CC FIELD8(0xfc)
2352 /*
2353 * RF registers
2354 */
2356 /*
2357 * RF 2
2358 */
2359 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2360 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2361 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2363 /*
2364 * RF 3
2365 */
2366 #define RF3_TXPOWER_G FIELD32(0x00003e00)
2367 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2368 #define RF3_TXPOWER_A FIELD32(0x00003c00)
2370 /*
2371 * RF 4
2372 */
2373 #define RF4_TXPOWER_G FIELD32(0x000007c0)
2374 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2375 #define RF4_TXPOWER_A FIELD32(0x00000780)
2376 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2377 #define RF4_HT40 FIELD32(0x00200000)
2379 /*
2380 * EEPROM content.
2381 * The wordsize of the EEPROM is 16 bits.
2382 */
2386 EEPROM_VERSION,
2387 EEPROM_MAC_ADDR_0,
2388 EEPROM_MAC_ADDR_1,
2389 EEPROM_MAC_ADDR_2,
2390 EEPROM_NIC_CONF0,
2391 EEPROM_NIC_CONF1,
2392 EEPROM_FREQ,
2393 EEPROM_LED_AG_CONF,
2394 EEPROM_LED_ACT_CONF,
2395 EEPROM_LED_POLARITY,
2396 EEPROM_NIC_CONF2,
2397 EEPROM_LNA,
2398 EEPROM_RSSI_BG,
2399 EEPROM_RSSI_BG2,
2400 EEPROM_TXMIXER_GAIN_BG,
2401 EEPROM_RSSI_A,
2402 EEPROM_RSSI_A2,
2403 EEPROM_TXMIXER_GAIN_A,
2404 EEPROM_EIRP_MAX_TX_POWER,
2405 EEPROM_TXPOWER_DELTA,
2406 EEPROM_TXPOWER_BG1,
2407 EEPROM_TXPOWER_BG2,
2408 EEPROM_TSSI_BOUND_BG1,
2409 EEPROM_TSSI_BOUND_BG2,
2410 EEPROM_TSSI_BOUND_BG3,
2411 EEPROM_TSSI_BOUND_BG4,
2412 EEPROM_TSSI_BOUND_BG5,
2413 EEPROM_TXPOWER_A1,
2414 EEPROM_TXPOWER_A2,
2415 EEPROM_TSSI_BOUND_A1,
2416 EEPROM_TSSI_BOUND_A2,
2417 EEPROM_TSSI_BOUND_A3,
2418 EEPROM_TSSI_BOUND_A4,
2419 EEPROM_TSSI_BOUND_A5,
2420 EEPROM_TXPOWER_BYRATE,
2421 EEPROM_BBP_START,
2423 /* IDs for extended EEPROM format used by three-chain devices */
2424 EEPROM_EXT_LNA2,
2425 EEPROM_EXT_TXPOWER_BG3,
2426 EEPROM_EXT_TXPOWER_A3,
2428 /* New values must be added before this */
2429 EEPROM_WORD_COUNT
2430 };
2432 /*
2433 * EEPROM Version
2434 */
2435 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
2436 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
2438 /*
2439 * HW MAC address.
2440 */
2441 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
2442 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
2443 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
2444 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
2445 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2446 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2448 /*
2449 * EEPROM NIC Configuration 0
2450 * RXPATH: 1: 1R, 2: 2R, 3: 3R
2451 * TXPATH: 1: 1T, 2: 2T, 3: 3T
2452 * RF_TYPE: RFIC type
2453 */
2454 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2455 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2456 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2458 /*
2459 * EEPROM NIC Configuration 1
2460 * HW_RADIO: 0: disable, 1: enable
2461 * EXTERNAL_TX_ALC: 0: disable, 1: enable
2462 * EXTERNAL_LNA_2G: 0: disable, 1: enable
2463 * EXTERNAL_LNA_5G: 0: disable, 1: enable
2464 * CARDBUS_ACCEL: 0: enable, 1: disable
2465 * BW40M_SB_2G: 0: disable, 1: enable
2466 * BW40M_SB_5G: 0: disable, 1: enable
2467 * WPS_PBC: 0: disable, 1: enable
2468 * BW40M_2G: 0: enable, 1: disable
2469 * BW40M_5G: 0: enable, 1: disable
2470 * BROADBAND_EXT_LNA: 0: disable, 1: enable
2471 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2472 * 10: Main antenna, 11: Aux antenna
2473 * INTERNAL_TX_ALC: 0: disable, 1: enable
2474 * BT_COEXIST: 0: disable, 1: enable
2475 * DAC_TEST: 0: disable, 1: enable
2476 */
2477 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2478 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2479 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2480 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2481 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2482 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2483 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2484 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2485 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2486 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2487 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2488 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2489 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2490 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2491 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2493 /*
2494 * EEPROM frequency
2495 */
2496 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2497 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2498 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2500 /*
2501 * EEPROM LED
2502 * POLARITY_RDY_G: Polarity RDY_G setting.
2503 * POLARITY_RDY_A: Polarity RDY_A setting.
2504 * POLARITY_ACT: Polarity ACT setting.
2505 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2506 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2507 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2508 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2509 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2510 * LED_MODE: Led mode.
2511 */
2512 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2513 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2514 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2515 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2516 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2517 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2518 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2519 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2520 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2522 /*
2523 * EEPROM NIC Configuration 2
2524 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2525 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2526 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2527 */
2528 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2529 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2530 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2532 /*
2533 * EEPROM LNA
2534 */
2535 #define EEPROM_LNA_BG FIELD16(0x00ff)
2536 #define EEPROM_LNA_A0 FIELD16(0xff00)
2538 /*
2539 * EEPROM RSSI BG offset
2540 */
2541 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2542 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2544 /*
2545 * EEPROM RSSI BG2 offset
2546 */
2547 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2548 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2550 /*
2551 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2552 */
2553 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2555 /*
2556 * EEPROM RSSI A offset
2557 */
2558 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2559 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2561 /*
2562 * EEPROM RSSI A2 offset
2563 */
2564 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2565 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2567 /*
2568 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2569 */
2570 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2572 /*
2573 * EEPROM EIRP Maximum TX power values(unit: dbm)
2574 */
2575 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2576 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2578 /*
2579 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2580 * This is delta in 40MHZ.
2581 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2582 * TYPE: 1: Plus the delta value, 0: minus the delta value
2583 * ENABLE: enable tx power compensation for 40BW
2584 */
2585 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2586 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2587 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2588 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2589 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2590 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2592 /*
2593 * EEPROM TXPOWER 802.11BG
2594 */
2595 #define EEPROM_TXPOWER_BG_SIZE 7
2596 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2597 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2599 /*
2600 * EEPROM temperature compensation boundaries 802.11BG
2601 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2602 * reduced by (agc_step * -4)
2603 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2604 * reduced by (agc_step * -3)
2605 */
2606 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2607 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2609 /*
2610 * EEPROM temperature compensation boundaries 802.11BG
2611 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2612 * reduced by (agc_step * -2)
2613 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2614 * reduced by (agc_step * -1)
2615 */
2616 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2617 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2619 /*
2620 * EEPROM temperature compensation boundaries 802.11BG
2621 * REF: Reference TSSI value, no tx power changes needed
2622 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2623 * increased by (agc_step * 1)
2624 */
2625 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2626 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2628 /*
2629 * EEPROM temperature compensation boundaries 802.11BG
2630 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2631 * increased by (agc_step * 2)
2632 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2633 * increased by (agc_step * 3)
2634 */
2635 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2636 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2638 /*
2639 * EEPROM temperature compensation boundaries 802.11BG
2640 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2641 * increased by (agc_step * 4)
2642 * AGC_STEP: Temperature compensation step.
2643 */
2644 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2645 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2647 /*
2648 * EEPROM TXPOWER 802.11A
2649 */
2650 #define EEPROM_TXPOWER_A_SIZE 6
2651 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2652 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2654 /* EEPROM_TXPOWER_{A,G} fields for RT3593 */
2655 #define EEPROM_TXPOWER_ALC FIELD8(0x1f)
2656 #define EEPROM_TXPOWER_FINE_CTRL FIELD8(0xe0)
2658 /*
2659 * EEPROM temperature compensation boundaries 802.11A
2660 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2661 * reduced by (agc_step * -4)
2662 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2663 * reduced by (agc_step * -3)
2664 */
2665 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2666 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2668 /*
2669 * EEPROM temperature compensation boundaries 802.11A
2670 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2671 * reduced by (agc_step * -2)
2672 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2673 * reduced by (agc_step * -1)
2674 */
2675 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2676 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2678 /*
2679 * EEPROM temperature compensation boundaries 802.11A
2680 * REF: Reference TSSI value, no tx power changes needed
2681 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2682 * increased by (agc_step * 1)
2683 */
2684 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2685 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2687 /*
2688 * EEPROM temperature compensation boundaries 802.11A
2689 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2690 * increased by (agc_step * 2)
2691 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2692 * increased by (agc_step * 3)
2693 */
2694 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2695 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2697 /*
2698 * EEPROM temperature compensation boundaries 802.11A
2699 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2700 * increased by (agc_step * 4)
2701 * AGC_STEP: Temperature compensation step.
2702 */
2703 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2704 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2706 /*
2707 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2708 */
2709 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2711 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2712 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2713 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2714 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2716 /*
2717 * EEPROM BBP.
2718 */
2719 #define EEPROM_BBP_SIZE 16
2720 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2721 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2723 /* EEPROM_EXT_LNA2 */
2724 #define EEPROM_EXT_LNA2_A1 FIELD16(0x00ff)
2725 #define EEPROM_EXT_LNA2_A2 FIELD16(0xff00)
2727 /*
2728 * EEPROM IQ Calibration, unlike other entries those are byte addresses.
2729 */
2731 #define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130
2732 #define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131
2733 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132
2734 #define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133
2735 #define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134
2736 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135
2737 #define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136
2738 #define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137
2739 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138
2740 #define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139
2741 #define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A
2742 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B
2743 #define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C
2744 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D
2745 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144
2746 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145
2747 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146
2748 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147
2749 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148
2750 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149
2751 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A
2752 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B
2753 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C
2754 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D
2755 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E
2756 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F
2757 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150
2758 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151
2759 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152
2760 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153
2761 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154
2762 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155
2763 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156
2764 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157
2765 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158
2766 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159
2767 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A
2768 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B
2769 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C
2770 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D
2771 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E
2772 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F
2773 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160
2774 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161
2775 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162
2776 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163
2777 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164
2778 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165
2779 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166
2780 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167
2782 /*
2783 * MCU mailbox commands.
2784 * MCU_SLEEP - go to power-save mode.
2785 * arg1: 1: save as much power as possible, 0: save less power.
2786 * status: 1: success, 2: already asleep,
2787 * 3: maybe MAC is busy so can't finish this task.
2788 * MCU_RADIO_OFF
2789 * arg0: 0: do power-saving, NOT turn off radio.
2790 */
2791 #define MCU_SLEEP 0x30
2792 #define MCU_WAKEUP 0x31
2793 #define MCU_RADIO_OFF 0x35
2794 #define MCU_CURRENT 0x36
2795 #define MCU_LED 0x50
2796 #define MCU_LED_STRENGTH 0x51
2797 #define MCU_LED_AG_CONF 0x52
2798 #define MCU_LED_ACT_CONF 0x53
2799 #define MCU_LED_LED_POLARITY 0x54
2800 #define MCU_RADAR 0x60
2801 #define MCU_BOOT_SIGNAL 0x72
2802 #define MCU_ANT_SELECT 0X73
2803 #define MCU_FREQ_OFFSET 0x74
2804 #define MCU_BBP_SIGNAL 0x80
2805 #define MCU_POWER_SAVE 0x83
2806 #define MCU_BAND_SELECT 0x91
2808 /*
2809 * MCU mailbox tokens
2810 */
2811 #define TOKEN_SLEEP 1
2812 #define TOKEN_RADIO_OFF 2
2813 #define TOKEN_WAKEUP 3
2816 /*
2817 * DMA descriptor defines.
2818 */
2820 #define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2821 #define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
2823 #define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2824 #define RXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
2825 #define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32))
2827 /*
2828 * TX WI structure
2829 */
2831 /*
2832 * Word0
2833 * FRAG: 1 To inform TKIP engine this is a fragment.
2834 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2835 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2836 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2837 * duplicate the frame to both channels).
2838 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2839 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2840 * aggregate consecutive frames with the same RA and QoS TID. If
2841 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2842 * directly after a frame B with AMPDU=1, frame A might still
2843 * get aggregated into the AMPDU started by frame B. So, setting
2844 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2845 * MPDU, it can still end up in an AMPDU if the previous frame
2846 * was tagged as AMPDU.
2847 */
2848 #define TXWI_W0_FRAG FIELD32(0x00000001)
2849 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2850 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2851 #define TXWI_W0_TS FIELD32(0x00000008)
2852 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2853 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2854 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2855 #define TXWI_W0_MCS FIELD32(0x007f0000)
2856 #define TXWI_W0_BW FIELD32(0x00800000)
2857 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2858 #define TXWI_W0_STBC FIELD32(0x06000000)
2859 #define TXWI_W0_IFS FIELD32(0x08000000)
2860 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2862 /*
2863 * Word1
2864 * ACK: 0: No Ack needed, 1: Ack needed
2865 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2866 * BW_WIN_SIZE: BA windows size of the recipient
2867 * WIRELESS_CLI_ID: Client ID for WCID table access
2868 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2869 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2870 * frame was processed. If multiple frames are aggregated together
2871 * (AMPDU==1) the reported tx status will always contain the packet
2872 * id of the first frame. 0: Don't report tx status for this frame.
2873 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2874 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2875 * This identification number is calculated by ((idx % 3) + 1).
2876 * The (+1) is required to prevent PACKETID to become 0.
2877 */
2878 #define TXWI_W1_ACK FIELD32(0x00000001)
2879 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2880 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2881 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2882 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2883 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2884 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2885 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2887 /*
2888 * Word2
2889 */
2890 #define TXWI_W2_IV FIELD32(0xffffffff)
2892 /*
2893 * Word3
2894 */
2895 #define TXWI_W3_EIV FIELD32(0xffffffff)
2897 /*
2898 * RX WI structure
2899 */
2901 /*
2902 * Word0
2903 */
2904 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2905 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2906 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2907 #define RXWI_W0_UDF FIELD32(0x0000e000)
2908 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2909 #define RXWI_W0_TID FIELD32(0xf0000000)
2911 /*
2912 * Word1
2913 */
2914 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2915 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2916 #define RXWI_W1_MCS FIELD32(0x007f0000)
2917 #define RXWI_W1_BW FIELD32(0x00800000)
2918 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2919 #define RXWI_W1_STBC FIELD32(0x06000000)
2920 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2922 /*
2923 * Word2
2924 */
2925 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2926 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2927 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2929 /*
2930 * Word3
2931 */
2932 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2933 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2935 /*
2936 * Macros for converting txpower from EEPROM to mac80211 value
2937 * and from mac80211 value to register value.
2938 */
2939 #define MIN_G_TXPOWER 0
2940 #define MIN_A_TXPOWER -7
2941 #define MAX_G_TXPOWER 31
2942 #define MAX_A_TXPOWER 15
2943 #define DEFAULT_TXPOWER 5
2945 #define MIN_A_TXPOWER_3593 0
2946 #define MAX_A_TXPOWER_3593 31
2948 #define TXPOWER_G_FROM_DEV(__txpower) \
2949 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2951 #define TXPOWER_A_FROM_DEV(__txpower) \
2952 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2954 /*
2955 * Board's maximun TX power limitation
2956 */
2957 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2959 /*
2960 * Number of TBTT intervals after which we have to adjust
2961 * the hw beacon timer.
2962 */
2963 #define BCN_TBTT_OFFSET 64
2965 /*
2966 * RT2800 driver data structure
2967 */
2969 u8 calibration_bw20;
2970 u8 calibration_bw40;
2971 u8 bbp25;
2972 u8 bbp26;
2973 u8 txmixer_gain_24g;
2974 u8 txmixer_gain_5g;
2976 };