1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * Tmis program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * Tmis program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * tmis program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * Tme full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *****************************************************************************/
29 #ifndef __RTL_DEBUG_H__
30 #define __RTL_DEBUG_H__
32 /*--------------------------------------------------------------
34 --------------------------------------------------------------*/
37 *For example, Tx/Rx/IO locked up,
38 *memory access violation,
39 *resource allocation failed,
40 *unexpected HW behavior, HW BUG
46 *Abnormal, rare, or unexpeted cases.
47 *For example, Packet/IO Ctl canceled,
48 *device suprisely unremoved and so on.
53 *Normal case driver developer should
54 *open, we can see link status like
55 *assoc/AddBA/DHCP/adapter start and
56 *so on basic and useful infromations.
61 *Normal case with useful information
62 *about current SW or HW state.
63 *For example, Tx/Rx descriptor to fill,
64 *Tx/Rx descriptor completed status,
65 *SW protocol state change, dynamic
66 *mechanism state change and so on.
71 *Normal case with detail execution
76 /*--------------------------------------------------------------
77 Define the rt_trace components
78 --------------------------------------------------------------*/
79 #define COMP_ERR BIT(0)
80 #define COMP_FW BIT(1)
81 #define COMP_INIT BIT(2) /*For init/deinit */
82 #define COMP_RECV BIT(3) /*For Rx. */
83 #define COMP_SEND BIT(4) /*For Tx. */
84 #define COMP_MLME BIT(5) /*For MLME. */
85 #define COMP_SCAN BIT(6) /*For Scan. */
86 #define COMP_INTR BIT(7) /*For interrupt Related. */
87 #define COMP_LED BIT(8) /*For LED. */
88 #define COMP_SEC BIT(9) /*For sec. */
89 #define COMP_BEACON BIT(10) /*For beacon. */
90 #define COMP_RATE BIT(11) /*For rate. */
91 #define COMP_RXDESC BIT(12) /*For rx desc. */
92 #define COMP_DIG BIT(13) /*For DIG */
93 #define COMP_TXAGC BIT(14) /*For Tx power */
94 #define COMP_HIPWR BIT(15) /*For High Power Mechanism */
95 #define COMP_POWER BIT(16) /*For lps/ips/aspm. */
96 #define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
97 #define COMP_BB_POWERSAVING BIT(18)
98 #define COMP_SWAS BIT(19) /*For SW Antenna Switch */
99 #define COMP_RF BIT(20) /*For RF. */
100 #define COMP_TURBO BIT(21) /*For EDCA TURBO. */
101 #define COMP_RATR BIT(22)
102 #define COMP_CMD BIT(23)
103 #define COMP_EFUSE BIT(24)
104 #define COMP_QOS BIT(25)
105 #define COMP_MAC80211 BIT(26)
106 #define COMP_REGD BIT(27)
107 #define COMP_CHAN BIT(28)
108 #define COMP_USB BIT(29)
109 #define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */
110 #define COMP_BT_COEXIST BIT(30)
112 /*--------------------------------------------------------------
113 Define the rt_print components
114 --------------------------------------------------------------*/
115 /* Define EEPROM and EFUSE check module bit*/
116 #define EEPROM_W BIT(0)
117 #define EFUSE_PG BIT(1)
118 #define EFUSE_READ_ALL BIT(2)
120 /* Define init check for module bit*/
121 #define INIT_EEPROM BIT(0)
122 #define INIT_TXPOWER BIT(1)
123 #define INIT_IQK BIT(2)
124 #define INIT_RF BIT(3)
126 /* Define PHY-BB/RF/MAC check module bit */
127 #define PHY_BBR BIT(0)
128 #define PHY_BBW BIT(1)
129 #define PHY_RFR BIT(2)
130 #define PHY_RFW BIT(3)
131 #define PHY_MACR BIT(4)
132 #define PHY_MACW BIT(5)
133 #define PHY_ALLR BIT(6)
134 #define PHY_ALLW BIT(7)
135 #define PHY_TXPWR BIT(8)
136 #define PHY_PWRDIFF BIT(9)
138 /* Define Dynamic Mechanism check module bit --> FDM */
139 #define WA_IOT BIT(0)
140 #define DM_PWDB BIT(1)
141 #define DM_MONITOR BIT(2)
142 #define DM_DIG BIT(3)
143 #define DM_EDCA_TURBO BIT(4)
145 #define DM_PWDB BIT(1)
170 #ifdef CONFIG_RTLWIFI_DEBUG
172 #define RT_ASSERT(_exp, fmt, ...) \
175 printk(KERN_DEBUG KBUILD_MODNAME ":%s(): " fmt, \
176 __func__, ##__VA_ARGS__); \
180 #define RT_TRACE(rtlpriv, comp, level, fmt, ...) \
182 if (unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
183 ((level) <= rtlpriv->dbg.global_debuglevel))) { \
184 printk(KERN_DEBUG KBUILD_MODNAME ":%s():<%lx-%x> " fmt, \
185 __func__, in_interrupt(), in_atomic(), \
190 #define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...) \
192 if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
193 printk(KERN_DEBUG KBUILD_MODNAME ": " fmt, \
198 #define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
201 if (unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents) && \
202 (_level <= rtlpriv->dbg.global_debuglevel))) { \
203 printk(KERN_DEBUG "%s: In process \"%s\" (pid %i): %s\n", \
204 KBUILD_MODNAME, current->comm, current->pid, \
206 print_hex_dump_bytes("", DUMP_PREFIX_NONE, \
207 _hexdata, _hexdatalen); \
216 static inline void RT_ASSERT(int exp
, const char *fmt
, ...)
221 static inline void RT_TRACE(struct rtl_priv
*rtlpriv
,
223 const char *fmt
, ...)
228 static inline void RTPRINT(struct rtl_priv
*rtlpriv
,
229 int dbgtype
, int dbgflag
,
230 const char *fmt
, ...)
234 static inline void RT_PRINT_DATA(struct rtl_priv
*rtlpriv
,
236 const char *titlestring
,
237 const void *hexdata
, size_t hexdatalen
)
243 void rtl_dbgp_flag_init(struct ieee80211_hw
*hw
);