drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL8723E_PWRSEQ_H__
  31 #define __RTL8723E_PWRSEQ_H__
  32
  33 #include "pwrseqcmd.h"
  34 /*
  35         Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
  36         There are 6 HW Power States:
  37         0: POFF--Power Off
  38         1: PDN--Power Down
  39         2: CARDEMU--Card Emulation
  40         3: ACT--Active Mode
  41         4: LPS--Low Power State
  42         5: SUS--Suspend
  43
  44         The transision from different states are defined below
  45         TRANS_CARDEMU_TO_ACT
  46         TRANS_ACT_TO_CARDEMU
  47         TRANS_CARDEMU_TO_SUS
  48         TRANS_SUS_TO_CARDEMU
  49         TRANS_CARDEMU_TO_PDN
  50         TRANS_ACT_TO_LPS
  51         TRANS_LPS_TO_ACT
  52
  53         TRANS_END
  54         PWR SEQ Version: rtl8188e_PwrSeq_V09.h
  55 */
  56
  57 #define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS     10
  58 #define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS     10
  59 #define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS     10
  60 #define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS     10
  61 #define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS     10
  62 #define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS     10
  63 #define RTL8188E_TRANS_ACT_TO_LPS_STEPS         15
  64 #define RTL8188E_TRANS_LPS_TO_ACT_STEPS         15
  65 #define RTL8188E_TRANS_END_STEPS                1
  66
  67
  68 #define RTL8188E_TRANS_CARDEMU_TO_ACT                                   \
  69         /* format */                                                    \
  70         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
  71         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  72         /* wait till 0x04[17] = 1    power ready*/                      \
  73         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},             \
  74         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  75         /* 0x02[1:0] = 0        reset BB*/                              \
  76         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0},             \
  77         {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  78         /*0x24[23] = 2b'01 schmit trigger */                            \
  79         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
  80         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  81         /* 0x04[15] = 0 disable HWPDN (control by DRV)*/                \
  82         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},                    \
  83         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  84         /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
  85         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0},             \
  86         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  87         /*0x04[8] = 1 polling until return 0*/                          \
  88         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},               \
  89         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  90         /*wait till 0x04[8] = 0*/                                       \
  91         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},                  \
  92         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
  93         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*LDO normal mode*/\
  94         {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
  95         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO Driving*/\
  96
  97 #define RTL8188E_TRANS_ACT_TO_CARDEMU                                   \
  98         /* format */                                                    \
  99         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 100         {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 101         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\
 102         {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 103         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*LDO Sleep mode*/\
 104         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 105         /*0x04[9] = 1 turn off MAC by HW state machine*/                \
 106         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
 107         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 108         /*wait till 0x04[9] = 0 polling until return 0 to disable*/     \
 109         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},                  \
 110
 111
 112 #define RTL8188E_TRANS_CARDEMU_TO_SUS                                   \
 113         /* format */                                                    \
 114         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 115         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 116         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 117         /*0x04[12:11] = 2b'01enable WL suspend*/                        \
 118         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},        \
 119         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 120         /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/               \
 121         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)},\
 122         {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 123         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 124         /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
 125         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)},                 \
 126         {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 127         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 128         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
 129         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
 130         {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 131         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 132         /*Set USB suspend enable local register  0xfe10[4]= 1 */        \
 133         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
 134         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 135         /*Set SDIO suspend local register*/                             \
 136         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
 137         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 138         /*wait power state to suspend*/                                 \
 139         PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
 140
 141 #define RTL8188E_TRANS_SUS_TO_CARDEMU                                   \
 142         /* format */                                                    \
 143         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 144         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 145         /*Set SDIO suspend local register*/                             \
 146         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},                   \
 147         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 148         /*wait power state to suspend*/                                 \
 149         PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},            \
 150         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 151         /*0x04[12:11] = 2b'01enable WL suspend*/                        \
 152         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
 153
 154 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS                               \
 155         /* format */                                                    \
 156         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 157         {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 158         /*0x24[23] = 2b'01 schmit trigger */                            \
 159         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
 160         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 161         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 162         /*0x04[12:11] = 2b'01 enable WL suspend*/                       \
 163         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},        \
 164         {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 165         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 166         /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
 167         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},                      \
 168         {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 169         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,                             \
 170         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
 171         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
 172         {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 173         /*Set USB suspend enable local register  0xfe10[4]= 1 */        \
 174         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
 175         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 176         /*Set SDIO suspend local register*/                             \
 177         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
 178         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 179         PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
 180
 181 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU                               \
 182         /* format */                                                    \
 183         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 184         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 185         PWR_BASEADDR_SDIO,\
 186         PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/  \
 187         {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 188         PWR_BASEADDR_SDIO,\
 189         PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
 190         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 191         PWR_BASEADDR_MAC,                                               \
 192         PWR_CMD_WRITE, BIT(3)|BIT(4), 0},                               \
 193         /*0x04[12:11] = 2b'01enable WL suspend*/
 194
 195
 196 #define RTL8188E_TRANS_CARDEMU_TO_PDN                                   \
 197         /* format */                                                    \
 198         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 199         {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 200         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/   \
 201         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 202         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
 203
 204
 205 #define RTL8188E_TRANS_PDN_TO_CARDEMU                                   \
 206         /* format */                                                    \
 207         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 208         {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 209         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
 210
 211
 212 #define RTL8188E_TRANS_ACT_TO_LPS                                       \
 213         /* format */                                                    \
 214         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 215         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 216         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/       \
 217         {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 218         /*zero if no pkt is tx*/\
 219         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 220         {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 221         /*Should be zero if no packet is transmitting*/ \
 222         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 223         {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 224         /*Should be zero if no packet is transmitting*/                 \
 225         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 226         {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 227         /*Should be zero if no packet is transmitting*/                 \
 228         PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
 229         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 230         /*CCK and OFDM are disabled, and clock are gated*/              \
 231         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                    \
 232         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 233         PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
 234         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 235         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/  \
 236         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 237         /*check if removed later*/                                      \
 238         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},                    \
 239         {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 240         /*Respond TxOK to scheduler*/                                   \
 241         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},               \
 242
 243
 244 #define RTL8188E_TRANS_LPS_TO_ACT                                       \
 245         /* format */                                                    \
 246         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
 247         {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
 248         PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/    \
 249         {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
 250         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/      \
 251         {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
 252         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/     \
 253         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 254         PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
 255         {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 256         /*.     0x08[4] = 0              switch TSF to 40M*/            \
 257         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
 258         {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 259         /*Polling 0x109[7]= 0  TSF in 40M*/                             \
 260         PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},                  \
 261         {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 262         /*. 0x29[7:6] = 2b'00    enable BB clock*/                      \
 263         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0},             \
 264         {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 265         /*.     0x101[1] = 1*/\
 266         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
 267         {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 268         /*.     0x100[7:0] = 0xFF        enable WMAC TRX*/\
 269         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},                   \
 270         {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
 271         /*. 0x02[1:0] = 2b'11  enable BB macro*/\
 272         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, \
 273         {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 274         PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.  0x522 = 0*/
 275
 276
 277 #define RTL8188E_TRANS_END                                              \
 278         /* format */                                                    \
 279         /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
 280         {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 281         0, PWR_CMD_END, 0, 0}
 282
 283 extern struct wlan_pwr_cfg rtl8188e_power_on_flow
 284                 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
 285                 RTL8188E_TRANS_END_STEPS];
 286 extern struct wlan_pwr_cfg rtl8188e_radio_off_flow
 287                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 288                 RTL8188E_TRANS_END_STEPS];
 289 extern struct wlan_pwr_cfg rtl8188e_card_disable_flow
 290                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 291                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 292                 RTL8188E_TRANS_END_STEPS];
 293 extern struct wlan_pwr_cfg rtl8188e_card_enable_flow
 294                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 295                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 296                 RTL8188E_TRANS_END_STEPS];
 297 extern struct wlan_pwr_cfg rtl8188e_suspend_flow
 298                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 299                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 300                 RTL8188E_TRANS_END_STEPS];
 301 extern struct wlan_pwr_cfg rtl8188e_resume_flow
 302                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 303                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 304                 RTL8188E_TRANS_END_STEPS];
 305 extern struct wlan_pwr_cfg rtl8188e_hwpdn_flow
 306                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 307                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 308                 RTL8188E_TRANS_END_STEPS];
 309 extern struct wlan_pwr_cfg rtl8188e_enter_lps_flow
 310                 [RTL8188E_TRANS_ACT_TO_LPS_STEPS +
 311                 RTL8188E_TRANS_END_STEPS];
 312 extern struct wlan_pwr_cfg rtl8188e_leave_lps_flow
 313                 [RTL8188E_TRANS_LPS_TO_ACT_STEPS +
 314                 RTL8188E_TRANS_END_STEPS];
 315
 316 /* RTL8723 Power Configuration CMDs for PCIe interface */
 317 #define Rtl8188E_NIC_PWR_ON_FLOW        rtl8188e_power_on_flow
 318 #define Rtl8188E_NIC_RF_OFF_FLOW        rtl8188e_radio_off_flow
 319 #define Rtl8188E_NIC_DISABLE_FLOW       rtl8188e_card_disable_flow
 320 #define Rtl8188E_NIC_ENABLE_FLOW        rtl8188e_card_enable_flow
 321 #define Rtl8188E_NIC_SUSPEND_FLOW       rtl8188e_suspend_flow
 322 #define Rtl8188E_NIC_RESUME_FLOW        rtl8188e_resume_flow
 323 #define Rtl8188E_NIC_PDN_FLOW           rtl8188e_hwpdn_flow
 324 #define Rtl8188E_NIC_LPS_ENTER_FLOW     rtl8188e_enter_lps_flow
 325 #define Rtl8188E_NIC_LPS_LEAVE_FLOW     rtl8188e_leave_lps_flow
 326
 327 #endif