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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / rtl8192c / dm_common.c
blob06cb94cf50851da06bed6fd0bcad4a3f974504a0
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include <linux/export.h>
31 #include "dm_common.h"
32 #include "phy_common.h"
33 #include "../pci.h"
34 #include "../base.h"
35
36 #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
37 #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
38 #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
39 #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
40 #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
41
42 #define RTLPRIV (struct rtl_priv *)
43 #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
44 ((RTLPRIV(_priv))->mac80211.opmode == \
45 NL80211_IFTYPE_ADHOC) ? \
46 ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \
47 ((RTLPRIV(_priv))->dm.undec_sm_pwdb)
48
49 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
50 0x7f8001fe,
51 0x788001e2,
52 0x71c001c7,
53 0x6b8001ae,
54 0x65400195,
55 0x5fc0017f,
56 0x5a400169,
57 0x55400155,
58 0x50800142,
59 0x4c000130,
60 0x47c0011f,
61 0x43c0010f,
62 0x40000100,
63 0x3c8000f2,
64 0x390000e4,
65 0x35c000d7,
66 0x32c000cb,
67 0x300000c0,
68 0x2d4000b5,
69 0x2ac000ab,
70 0x288000a2,
71 0x26000098,
72 0x24000090,
73 0x22000088,
74 0x20000080,
75 0x1e400079,
76 0x1c800072,
77 0x1b00006c,
78 0x19800066,
79 0x18000060,
80 0x16c0005b,
81 0x15800056,
82 0x14400051,
83 0x1300004c,
84 0x12000048,
85 0x11000044,
86 0x10000040,
87 };
88
89 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
90 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
91 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
92 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
93 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
94 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
95 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
96 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
97 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
98 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
99 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
100 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
101 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
102 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
103 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
104 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
105 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
106 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
107 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
108 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
109 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
110 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
111 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
112 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
113 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
114 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
115 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
116 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
117 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
118 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
119 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
120 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
121 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
122 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
123 };
124
125 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
126 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
127 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
128 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
129 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
130 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
131 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
132 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
133 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
134 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
135 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
136 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
137 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
138 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
139 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
140 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
141 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
142 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
143 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
144 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
145 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
146 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
147 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
148 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
149 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
150 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
151 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
152 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
153 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
154 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
155 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
156 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
157 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
158 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
159 };
160
161 static u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
162
163 void dm_restorepowerindex(struct ieee80211_hw *hw)
164 {
165 struct rtl_priv *rtlpriv = rtl_priv(hw);
166 u8 index;
167
168 for (index = 0; index < 6; index++)
169 rtl_write_byte(rtlpriv, power_index_reg[index],
170 rtlpriv->dm.powerindex_backup[index]);
171 }
172 EXPORT_SYMBOL_GPL(dm_restorepowerindex);
173
174 void dm_writepowerindex(struct ieee80211_hw *hw, u8 value)
175 {
176 struct rtl_priv *rtlpriv = rtl_priv(hw);
177 u8 index;
178
179 for (index = 0; index < 6; index++)
180 rtl_write_byte(rtlpriv, power_index_reg[index], value);
181 }
182 EXPORT_SYMBOL_GPL(dm_writepowerindex);
183
184 void dm_savepowerindex(struct ieee80211_hw *hw)
185 {
186 struct rtl_priv *rtlpriv = rtl_priv(hw);
187 u8 index;
188 u8 tmp;
189
190 for (index = 0; index < 6; index++) {
191 tmp = rtl_read_byte(rtlpriv, power_index_reg[index]);
192 rtlpriv->dm.powerindex_backup[index] = tmp;
193 }
194 }
195 EXPORT_SYMBOL_GPL(dm_savepowerindex);
196
197 static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
198 {
199 struct rtl_priv *rtlpriv = rtl_priv(hw);
200 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
201
202 dm_digtable->dig_enable_flag = true;
203 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
204 dm_digtable->cur_igvalue = 0x20;
205 dm_digtable->pre_igvalue = 0x0;
206 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
207 dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
208 dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
209 dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
210 dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
211 dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
212 dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
213 dm_digtable->rx_gain_max = DM_DIG_MAX;
214 dm_digtable->rx_gain_min = DM_DIG_MIN;
215 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
216 dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
217 dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
218 dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
219 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
220 }
221
222 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
223 {
224 struct rtl_priv *rtlpriv = rtl_priv(hw);
225 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
226 long rssi_val_min = 0;
227
228 if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
229 (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
230 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
231 rssi_val_min =
232 (rtlpriv->dm.entry_min_undec_sm_pwdb >
233 rtlpriv->dm.undec_sm_pwdb) ?
234 rtlpriv->dm.undec_sm_pwdb :
235 rtlpriv->dm.entry_min_undec_sm_pwdb;
236 else
237 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
238 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
239 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
240 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
241 } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
242 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
243 }
244
245 return (u8) rssi_val_min;
246 }
247
248 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
249 {
250 u32 ret_value;
251 struct rtl_priv *rtlpriv = rtl_priv(hw);
252 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
253
254 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
255 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
256
257 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
258 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
259 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
260
261 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
262 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
263 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
264 falsealm_cnt->cnt_rate_illegal +
265 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
266
267 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
268 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
269 falsealm_cnt->cnt_cck_fail = ret_value;
270
271 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
272 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
273 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
274 falsealm_cnt->cnt_rate_illegal +
275 falsealm_cnt->cnt_crc8_fail +
276 falsealm_cnt->cnt_mcs_fail +
277 falsealm_cnt->cnt_cck_fail);
278
279 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
280 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
281 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
282 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
283
284 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
285 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
286 falsealm_cnt->cnt_parity_fail,
287 falsealm_cnt->cnt_rate_illegal,
288 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
289
290 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
291 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
292 falsealm_cnt->cnt_ofdm_fail,
293 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
294 }
295
296 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
297 {
298 struct rtl_priv *rtlpriv = rtl_priv(hw);
299 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
300 u8 value_igi = dm_digtable->cur_igvalue;
301
302 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
303 value_igi--;
304 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
305 value_igi += 0;
306 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
307 value_igi++;
308 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
309 value_igi += 2;
310 if (value_igi > DM_DIG_FA_UPPER)
311 value_igi = DM_DIG_FA_UPPER;
312 else if (value_igi < DM_DIG_FA_LOWER)
313 value_igi = DM_DIG_FA_LOWER;
314 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
315 value_igi = 0x32;
316
317 dm_digtable->cur_igvalue = value_igi;
318 rtl92c_dm_write_dig(hw);
319 }
320
321 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
322 {
323 struct rtl_priv *rtlpriv = rtl_priv(hw);
324 struct dig_t *digtable = &rtlpriv->dm_digtable;
325
326 if (rtlpriv->falsealm_cnt.cnt_all > digtable->fa_highthresh) {
327 if ((digtable->back_val - 2) < digtable->back_range_min)
328 digtable->back_val = digtable->back_range_min;
329 else
330 digtable->back_val -= 2;
331 } else if (rtlpriv->falsealm_cnt.cnt_all < digtable->fa_lowthresh) {
332 if ((digtable->back_val + 2) > digtable->back_range_max)
333 digtable->back_val = digtable->back_range_max;
334 else
335 digtable->back_val += 2;
336 }
337
338 if ((digtable->rssi_val_min + 10 - digtable->back_val) >
339 digtable->rx_gain_max)
340 digtable->cur_igvalue = digtable->rx_gain_max;
341 else if ((digtable->rssi_val_min + 10 -
342 digtable->back_val) < digtable->rx_gain_min)
343 digtable->cur_igvalue = digtable->rx_gain_min;
344 else
345 digtable->cur_igvalue = digtable->rssi_val_min + 10 -
346 digtable->back_val;
347
348 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
349 "rssi_val_min = %x back_val %x\n",
350 digtable->rssi_val_min, digtable->back_val);
351
352 rtl92c_dm_write_dig(hw);
353 }
354
355 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
356 {
357 static u8 initialized; /* initialized to false */
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
360 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
361 long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
362 bool multi_sta = false;
363
364 if (mac->opmode == NL80211_IFTYPE_ADHOC)
365 multi_sta = true;
366
367 if (!multi_sta ||
368 dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
369 initialized = false;
370 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
371 return;
372 } else if (initialized == false) {
373 initialized = true;
374 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
375 dm_digtable->cur_igvalue = 0x20;
376 rtl92c_dm_write_dig(hw);
377 }
378
379 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
380 if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
381 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
382
383 if (dm_digtable->dig_ext_port_stage ==
384 DIG_EXT_PORT_STAGE_2) {
385 dm_digtable->cur_igvalue = 0x20;
386 rtl92c_dm_write_dig(hw);
387 }
388
389 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
390 } else if (rssi_strength > dm_digtable->rssi_highthresh) {
391 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
392 rtl92c_dm_ctrl_initgain_by_fa(hw);
393 }
394 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
395 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
396 dm_digtable->cur_igvalue = 0x20;
397 rtl92c_dm_write_dig(hw);
398 }
399
400 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
401 "curmultista_cstate = %x dig_ext_port_stage %x\n",
402 dm_digtable->curmultista_cstate,
403 dm_digtable->dig_ext_port_stage);
404 }
405
406 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
407 {
408 struct rtl_priv *rtlpriv = rtl_priv(hw);
409 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
410
411 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
412 "presta_cstate = %x, cursta_cstate = %x\n",
413 dm_digtable->presta_cstate, dm_digtable->cursta_cstate);
414
415 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
416 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
417 dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
418
419 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
420 dm_digtable->rssi_val_min =
421 rtl92c_dm_initial_gain_min_pwdb(hw);
422 rtl92c_dm_ctrl_initgain_by_rssi(hw);
423 }
424 } else {
425 dm_digtable->rssi_val_min = 0;
426 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
427 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
428 dm_digtable->cur_igvalue = 0x20;
429 dm_digtable->pre_igvalue = 0;
430 rtl92c_dm_write_dig(hw);
431 }
432 }
433
434 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
435 {
436 struct rtl_priv *rtlpriv = rtl_priv(hw);
437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
438 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
439
440 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
441 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
442
443 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
444 if (dm_digtable->rssi_val_min <= 25)
445 dm_digtable->cur_cck_pd_state =
446 CCK_PD_STAGE_LowRssi;
447 else
448 dm_digtable->cur_cck_pd_state =
449 CCK_PD_STAGE_HighRssi;
450 } else {
451 if (dm_digtable->rssi_val_min <= 20)
452 dm_digtable->cur_cck_pd_state =
453 CCK_PD_STAGE_LowRssi;
454 else
455 dm_digtable->cur_cck_pd_state =
456 CCK_PD_STAGE_HighRssi;
457 }
458 } else {
459 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
460 }
461
462 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
463 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
464 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
465 dm_digtable->cur_cck_fa_state =
466 CCK_FA_STAGE_High;
467 else
468 dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low;
469
470 if (dm_digtable->pre_cck_fa_state !=
471 dm_digtable->cur_cck_fa_state) {
472 if (dm_digtable->cur_cck_fa_state ==
473 CCK_FA_STAGE_Low)
474 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
475 0x83);
476 else
477 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
478 0xcd);
479
480 dm_digtable->pre_cck_fa_state =
481 dm_digtable->cur_cck_fa_state;
482 }
483
484 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
485
486 if (IS_92C_SERIAL(rtlhal->version))
487 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
488 MASKBYTE2, 0xd7);
489 } else {
490 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
491 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
492
493 if (IS_92C_SERIAL(rtlhal->version))
494 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
495 MASKBYTE2, 0xd3);
496 }
497 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
498 }
499
500 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
501 dm_digtable->cur_cck_pd_state);
502
503 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
504 IS_92C_SERIAL(rtlhal->version));
505 }
506
507 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
508 {
509 struct rtl_priv *rtlpriv = rtl_priv(hw);
510 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
511 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
512
513 if (mac->act_scanning)
514 return;
515
516 if (mac->link_state >= MAC80211_LINKED)
517 dm_digtable->cursta_cstate = DIG_STA_CONNECT;
518 else
519 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
520
521 rtl92c_dm_initial_gain_sta(hw);
522 rtl92c_dm_initial_gain_multi_sta(hw);
523 rtl92c_dm_cck_packet_detection_thresh(hw);
524
525 dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
526
527 }
528
529 static void rtl92c_dm_dig(struct ieee80211_hw *hw)
530 {
531 struct rtl_priv *rtlpriv = rtl_priv(hw);
532 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
533
534 if (rtlpriv->dm.dm_initialgain_enable == false)
535 return;
536 if (dm_digtable->dig_enable_flag == false)
537 return;
538
539 rtl92c_dm_ctrl_initgain_by_twoport(hw);
540
541 }
542
543 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
544 {
545 struct rtl_priv *rtlpriv = rtl_priv(hw);
546
547 rtlpriv->dm.dynamic_txpower_enable = false;
548
549 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
550 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
551 }
552
553 void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
554 {
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
556 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
557
558 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
559 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
560 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
561 dm_digtable->back_val);
562
563 dm_digtable->cur_igvalue += 2;
564 if (dm_digtable->cur_igvalue > 0x3f)
565 dm_digtable->cur_igvalue = 0x3f;
566
567 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
568 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
569 dm_digtable->cur_igvalue);
570 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
571 dm_digtable->cur_igvalue);
572
573 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
574 }
575 }
576 EXPORT_SYMBOL(rtl92c_dm_write_dig);
577
578 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
579 {
580 struct rtl_priv *rtlpriv = rtl_priv(hw);
581 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
582
583 u8 h2c_parameter[3] = { 0 };
584
585 return;
586
587 if (tmpentry_max_pwdb != 0) {
588 rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb;
589 } else {
590 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
591 }
592
593 if (tmpentry_min_pwdb != 0xff) {
594 rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb;
595 } else {
596 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
597 }
598
599 h2c_parameter[2] = (u8) (rtlpriv->dm.undec_sm_pwdb & 0xFF);
600 h2c_parameter[0] = 0;
601
602 rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
603 }
604
605 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
606 {
607 struct rtl_priv *rtlpriv = rtl_priv(hw);
608 rtlpriv->dm.current_turbo_edca = false;
609 rtlpriv->dm.is_any_nonbepkts = false;
610 rtlpriv->dm.is_cur_rdlstate = false;
611 }
612 EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
613
614 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
615 {
616 struct rtl_priv *rtlpriv = rtl_priv(hw);
617 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
618 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
619
620 static u64 last_txok_cnt;
621 static u64 last_rxok_cnt;
622 static u32 last_bt_edca_ul;
623 static u32 last_bt_edca_dl;
624 u64 cur_txok_cnt = 0;
625 u64 cur_rxok_cnt = 0;
626 u32 edca_be_ul = 0x5ea42b;
627 u32 edca_be_dl = 0x5ea42b;
628 bool bt_change_edca = false;
629
630 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
631 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
632 rtlpriv->dm.current_turbo_edca = false;
633 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
634 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
635 }
636
637 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
638 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
639 bt_change_edca = true;
640 }
641
642 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
643 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
644 bt_change_edca = true;
645 }
646
647 if (mac->link_state != MAC80211_LINKED) {
648 rtlpriv->dm.current_turbo_edca = false;
649 return;
650 }
651
652 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
653 if (!(edca_be_ul & 0xffff0000))
654 edca_be_ul |= 0x005e0000;
655
656 if (!(edca_be_dl & 0xffff0000))
657 edca_be_dl |= 0x005e0000;
658 }
659
660 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
661 (!rtlpriv->dm.disable_framebursting))) {
662
663 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
664 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
665
666 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
667 if (!rtlpriv->dm.is_cur_rdlstate ||
668 !rtlpriv->dm.current_turbo_edca) {
669 rtl_write_dword(rtlpriv,
670 REG_EDCA_BE_PARAM,
671 edca_be_dl);
672 rtlpriv->dm.is_cur_rdlstate = true;
673 }
674 } else {
675 if (rtlpriv->dm.is_cur_rdlstate ||
676 !rtlpriv->dm.current_turbo_edca) {
677 rtl_write_dword(rtlpriv,
678 REG_EDCA_BE_PARAM,
679 edca_be_ul);
680 rtlpriv->dm.is_cur_rdlstate = false;
681 }
682 }
683 rtlpriv->dm.current_turbo_edca = true;
684 } else {
685 if (rtlpriv->dm.current_turbo_edca) {
686 u8 tmp = AC0_BE;
687 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
688 &tmp);
689 rtlpriv->dm.current_turbo_edca = false;
690 }
691 }
692
693 rtlpriv->dm.is_any_nonbepkts = false;
694 last_txok_cnt = rtlpriv->stats.txbytesunicast;
695 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
696 }
697
698 static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
699 *hw)
700 {
701 struct rtl_priv *rtlpriv = rtl_priv(hw);
702 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
703 struct rtl_phy *rtlphy = &(rtlpriv->phy);
704 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
705 u8 thermalvalue, delta, delta_lck, delta_iqk;
706 long ele_a, ele_d, temp_cck, val_x, value32;
707 long val_y, ele_c = 0;
708 u8 ofdm_index[2], ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
709 s8 cck_index = 0;
710 int i;
711 bool is2t = IS_92C_SERIAL(rtlhal->version);
712 s8 txpwr_level[2] = {0, 0};
713 u8 ofdm_min_index = 6, rf;
714
715 rtlpriv->dm.txpower_trackinginit = true;
716 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
717 "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
718
719 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
720
721 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
722 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
723 thermalvalue, rtlpriv->dm.thermalvalue,
724 rtlefuse->eeprom_thermalmeter);
725
726 rtl92c_phy_ap_calibrate(hw, (thermalvalue -
727 rtlefuse->eeprom_thermalmeter));
728 if (is2t)
729 rf = 2;
730 else
731 rf = 1;
732
733 if (thermalvalue) {
734 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
735 MASKDWORD) & MASKOFDM_D;
736
737 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
738 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
739 ofdm_index_old[0] = (u8) i;
740
741 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
742 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
743 ROFDM0_XATXIQIMBALANCE,
744 ele_d, ofdm_index_old[0]);
745 break;
746 }
747 }
748
749 if (is2t) {
750 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
751 MASKDWORD) & MASKOFDM_D;
752
753 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
754 if (ele_d == (ofdmswing_table[i] &
755 MASKOFDM_D)) {
756 ofdm_index_old[1] = (u8) i;
757 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
758 DBG_LOUD,
759 "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
760 ROFDM0_XBTXIQIMBALANCE, ele_d,
761 ofdm_index_old[1]);
762 break;
763 }
764 }
765 }
766
767 temp_cck =
768 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
769
770 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
771 if (rtlpriv->dm.cck_inch14) {
772 if (memcmp((void *)&temp_cck,
773 (void *)&cckswing_table_ch14[i][2],
774 4) == 0) {
775 cck_index_old = (u8) i;
776
777 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
778 DBG_LOUD,
779 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
780 RCCK0_TXFILTER2, temp_cck,
781 cck_index_old,
782 rtlpriv->dm.cck_inch14);
783 break;
784 }
785 } else {
786 if (memcmp((void *)&temp_cck,
787 (void *)
788 &cckswing_table_ch1ch13[i][2],
789 4) == 0) {
790 cck_index_old = (u8) i;
791
792 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
793 DBG_LOUD,
794 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
795 RCCK0_TXFILTER2, temp_cck,
796 cck_index_old,
797 rtlpriv->dm.cck_inch14);
798 break;
799 }
800 }
801 }
802
803 if (!rtlpriv->dm.thermalvalue) {
804 rtlpriv->dm.thermalvalue =
805 rtlefuse->eeprom_thermalmeter;
806 rtlpriv->dm.thermalvalue_lck = thermalvalue;
807 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
808 for (i = 0; i < rf; i++)
809 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
810 rtlpriv->dm.cck_index = cck_index_old;
811 }
812
813 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
814 (thermalvalue - rtlpriv->dm.thermalvalue) :
815 (rtlpriv->dm.thermalvalue - thermalvalue);
816
817 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
818 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
819 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
820
821 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
822 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
823 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
824
825 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
826 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
827 thermalvalue, rtlpriv->dm.thermalvalue,
828 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
829 delta_iqk);
830
831 if (delta_lck > 1) {
832 rtlpriv->dm.thermalvalue_lck = thermalvalue;
833 rtl92c_phy_lc_calibrate(hw);
834 }
835
836 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
837 if (thermalvalue > rtlpriv->dm.thermalvalue) {
838 for (i = 0; i < rf; i++)
839 rtlpriv->dm.ofdm_index[i] -= delta;
840 rtlpriv->dm.cck_index -= delta;
841 } else {
842 for (i = 0; i < rf; i++)
843 rtlpriv->dm.ofdm_index[i] += delta;
844 rtlpriv->dm.cck_index += delta;
845 }
846
847 if (is2t) {
848 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
849 "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
850 rtlpriv->dm.ofdm_index[0],
851 rtlpriv->dm.ofdm_index[1],
852 rtlpriv->dm.cck_index);
853 } else {
854 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
855 "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
856 rtlpriv->dm.ofdm_index[0],
857 rtlpriv->dm.cck_index);
858 }
859
860 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
861 for (i = 0; i < rf; i++)
862 ofdm_index[i] =
863 rtlpriv->dm.ofdm_index[i]
864 + 1;
865 cck_index = rtlpriv->dm.cck_index + 1;
866 } else {
867 for (i = 0; i < rf; i++)
868 ofdm_index[i] =
869 rtlpriv->dm.ofdm_index[i];
870 cck_index = rtlpriv->dm.cck_index;
871 }
872
873 for (i = 0; i < rf; i++) {
874 if (txpwr_level[i] >= 0 &&
875 txpwr_level[i] <= 26) {
876 if (thermalvalue >
877 rtlefuse->eeprom_thermalmeter) {
878 if (delta < 5)
879 ofdm_index[i] -= 1;
880
881 else
882 ofdm_index[i] -= 2;
883 } else if (delta > 5 && thermalvalue <
884 rtlefuse->
885 eeprom_thermalmeter) {
886 ofdm_index[i] += 1;
887 }
888 } else if (txpwr_level[i] >= 27 &&
889 txpwr_level[i] <= 32
890 && thermalvalue >
891 rtlefuse->eeprom_thermalmeter) {
892 if (delta < 5)
893 ofdm_index[i] -= 1;
894
895 else
896 ofdm_index[i] -= 2;
897 } else if (txpwr_level[i] >= 32 &&
898 txpwr_level[i] <= 38 &&
899 thermalvalue >
900 rtlefuse->eeprom_thermalmeter
901 && delta > 5) {
902 ofdm_index[i] -= 1;
903 }
904 }
905
906 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
907 if (thermalvalue >
908 rtlefuse->eeprom_thermalmeter) {
909 if (delta < 5)
910 cck_index -= 1;
911
912 else
913 cck_index -= 2;
914 } else if (delta > 5 && thermalvalue <
915 rtlefuse->eeprom_thermalmeter) {
916 cck_index += 1;
917 }
918 } else if (txpwr_level[i] >= 27 &&
919 txpwr_level[i] <= 32 &&
920 thermalvalue >
921 rtlefuse->eeprom_thermalmeter) {
922 if (delta < 5)
923 cck_index -= 1;
924
925 else
926 cck_index -= 2;
927 } else if (txpwr_level[i] >= 32 &&
928 txpwr_level[i] <= 38 &&
929 thermalvalue > rtlefuse->eeprom_thermalmeter
930 && delta > 5) {
931 cck_index -= 1;
932 }
933
934 for (i = 0; i < rf; i++) {
935 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
936 ofdm_index[i] = OFDM_TABLE_SIZE - 1;
937
938 else if (ofdm_index[i] < ofdm_min_index)
939 ofdm_index[i] = ofdm_min_index;
940 }
941
942 if (cck_index > CCK_TABLE_SIZE - 1)
943 cck_index = CCK_TABLE_SIZE - 1;
944 else if (cck_index < 0)
945 cck_index = 0;
946
947 if (is2t) {
948 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
949 "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
950 ofdm_index[0], ofdm_index[1],
951 cck_index);
952 } else {
953 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
954 "new OFDM_A_index=0x%x, cck_index=0x%x\n",
955 ofdm_index[0], cck_index);
956 }
957 }
958
959 if (rtlpriv->dm.txpower_track_control && delta != 0) {
960 ele_d =
961 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
962 val_x = rtlphy->reg_e94;
963 val_y = rtlphy->reg_e9c;
964
965 if (val_x != 0) {
966 if ((val_x & 0x00000200) != 0)
967 val_x = val_x | 0xFFFFFC00;
968 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
969
970 if ((val_y & 0x00000200) != 0)
971 val_y = val_y | 0xFFFFFC00;
972 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
973
974 value32 = (ele_d << 22) |
975 ((ele_c & 0x3F) << 16) | ele_a;
976
977 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
978 MASKDWORD, value32);
979
980 value32 = (ele_c & 0x000003C0) >> 6;
981 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
982 value32);
983
984 value32 = ((val_x * ele_d) >> 7) & 0x01;
985 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
986 BIT(31), value32);
987
988 value32 = ((val_y * ele_d) >> 7) & 0x01;
989 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
990 BIT(29), value32);
991 } else {
992 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
993 MASKDWORD,
994 ofdmswing_table[ofdm_index[0]]);
995
996 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
997 0x00);
998 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
999 BIT(31) | BIT(29), 0x00);
1000 }
1001
1002 if (!rtlpriv->dm.cck_inch14) {
1003 rtl_write_byte(rtlpriv, 0xa22,
1004 cckswing_table_ch1ch13[cck_index]
1005 [0]);
1006 rtl_write_byte(rtlpriv, 0xa23,
1007 cckswing_table_ch1ch13[cck_index]
1008 [1]);
1009 rtl_write_byte(rtlpriv, 0xa24,
1010 cckswing_table_ch1ch13[cck_index]
1011 [2]);
1012 rtl_write_byte(rtlpriv, 0xa25,
1013 cckswing_table_ch1ch13[cck_index]
1014 [3]);
1015 rtl_write_byte(rtlpriv, 0xa26,
1016 cckswing_table_ch1ch13[cck_index]
1017 [4]);
1018 rtl_write_byte(rtlpriv, 0xa27,
1019 cckswing_table_ch1ch13[cck_index]
1020 [5]);
1021 rtl_write_byte(rtlpriv, 0xa28,
1022 cckswing_table_ch1ch13[cck_index]
1023 [6]);
1024 rtl_write_byte(rtlpriv, 0xa29,
1025 cckswing_table_ch1ch13[cck_index]
1026 [7]);
1027 } else {
1028 rtl_write_byte(rtlpriv, 0xa22,
1029 cckswing_table_ch14[cck_index]
1030 [0]);
1031 rtl_write_byte(rtlpriv, 0xa23,
1032 cckswing_table_ch14[cck_index]
1033 [1]);
1034 rtl_write_byte(rtlpriv, 0xa24,
1035 cckswing_table_ch14[cck_index]
1036 [2]);
1037 rtl_write_byte(rtlpriv, 0xa25,
1038 cckswing_table_ch14[cck_index]
1039 [3]);
1040 rtl_write_byte(rtlpriv, 0xa26,
1041 cckswing_table_ch14[cck_index]
1042 [4]);
1043 rtl_write_byte(rtlpriv, 0xa27,
1044 cckswing_table_ch14[cck_index]
1045 [5]);
1046 rtl_write_byte(rtlpriv, 0xa28,
1047 cckswing_table_ch14[cck_index]
1048 [6]);
1049 rtl_write_byte(rtlpriv, 0xa29,
1050 cckswing_table_ch14[cck_index]
1051 [7]);
1052 }
1053
1054 if (is2t) {
1055 ele_d = (ofdmswing_table[ofdm_index[1]] &
1056 0xFFC00000) >> 22;
1057
1058 val_x = rtlphy->reg_eb4;
1059 val_y = rtlphy->reg_ebc;
1060
1061 if (val_x != 0) {
1062 if ((val_x & 0x00000200) != 0)
1063 val_x = val_x | 0xFFFFFC00;
1064 ele_a = ((val_x * ele_d) >> 8) &
1065 0x000003FF;
1066
1067 if ((val_y & 0x00000200) != 0)
1068 val_y = val_y | 0xFFFFFC00;
1069 ele_c = ((val_y * ele_d) >> 8) &
1070 0x00003FF;
1071
1072 value32 = (ele_d << 22) |
1073 ((ele_c & 0x3F) << 16) | ele_a;
1074 rtl_set_bbreg(hw,
1075 ROFDM0_XBTXIQIMBALANCE,
1076 MASKDWORD, value32);
1077
1078 value32 = (ele_c & 0x000003C0) >> 6;
1079 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1080 MASKH4BITS, value32);
1081
1082 value32 = ((val_x * ele_d) >> 7) & 0x01;
1083 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1084 BIT(27), value32);
1085
1086 value32 = ((val_y * ele_d) >> 7) & 0x01;
1087 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1088 BIT(25), value32);
1089 } else {
1090 rtl_set_bbreg(hw,
1091 ROFDM0_XBTXIQIMBALANCE,
1092 MASKDWORD,
1093 ofdmswing_table[ofdm_index
1094 [1]]);
1095 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1096 MASKH4BITS, 0x00);
1097 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1098 BIT(27) | BIT(25), 0x00);
1099 }
1100
1101 }
1102 }
1103
1104 if (delta_iqk > 3) {
1105 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1106 rtl92c_phy_iq_calibrate(hw, false);
1107 }
1108
1109 if (rtlpriv->dm.txpower_track_control)
1110 rtlpriv->dm.thermalvalue = thermalvalue;
1111 }
1112
1113 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
1114
1115 }
1116
1117 static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1118 struct ieee80211_hw *hw)
1119 {
1120 struct rtl_priv *rtlpriv = rtl_priv(hw);
1121
1122 rtlpriv->dm.txpower_tracking = true;
1123 rtlpriv->dm.txpower_trackinginit = false;
1124
1125 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1126 "pMgntInfo->txpower_tracking = %d\n",
1127 rtlpriv->dm.txpower_tracking);
1128 }
1129
1130 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1131 {
1132 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1133 }
1134
1135 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1136 {
1137 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1138 }
1139
1140 static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1141 struct ieee80211_hw *hw)
1142 {
1143 struct rtl_priv *rtlpriv = rtl_priv(hw);
1144 static u8 tm_trigger;
1145
1146 if (!rtlpriv->dm.txpower_tracking)
1147 return;
1148
1149 if (!tm_trigger) {
1150 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1151 0x60);
1152 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1153 "Trigger 92S Thermal Meter!!\n");
1154 tm_trigger = 1;
1155 return;
1156 } else {
1157 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1158 "Schedule TxPowerTracking direct call!!\n");
1159 rtl92c_dm_txpower_tracking_directcall(hw);
1160 tm_trigger = 0;
1161 }
1162 }
1163
1164 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1165 {
1166 rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1167 }
1168 EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
1169
1170 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1171 {
1172 struct rtl_priv *rtlpriv = rtl_priv(hw);
1173 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1174
1175 p_ra->ratr_state = DM_RATR_STA_INIT;
1176 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1177
1178 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1179 rtlpriv->dm.useramask = true;
1180 else
1181 rtlpriv->dm.useramask = false;
1182
1183 }
1184 EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
1185
1186 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1187 {
1188 struct rtl_priv *rtlpriv = rtl_priv(hw);
1189 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1190
1191 dm_pstable->pre_ccastate = CCA_MAX;
1192 dm_pstable->cur_ccasate = CCA_MAX;
1193 dm_pstable->pre_rfstate = RF_MAX;
1194 dm_pstable->cur_rfstate = RF_MAX;
1195 dm_pstable->rssi_val_min = 0;
1196 }
1197
1198 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1199 {
1200 struct rtl_priv *rtlpriv = rtl_priv(hw);
1201 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1202 static u8 initialize;
1203 static u32 reg_874, reg_c70, reg_85c, reg_a74;
1204
1205 if (initialize == 0) {
1206 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1207 MASKDWORD) & 0x1CC000) >> 14;
1208
1209 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1210 MASKDWORD) & BIT(3)) >> 3;
1211
1212 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1213 MASKDWORD) & 0xFF000000) >> 24;
1214
1215 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1216
1217 initialize = 1;
1218 }
1219
1220 if (!bforce_in_normal) {
1221 if (dm_pstable->rssi_val_min != 0) {
1222 if (dm_pstable->pre_rfstate == RF_NORMAL) {
1223 if (dm_pstable->rssi_val_min >= 30)
1224 dm_pstable->cur_rfstate = RF_SAVE;
1225 else
1226 dm_pstable->cur_rfstate = RF_NORMAL;
1227 } else {
1228 if (dm_pstable->rssi_val_min <= 25)
1229 dm_pstable->cur_rfstate = RF_NORMAL;
1230 else
1231 dm_pstable->cur_rfstate = RF_SAVE;
1232 }
1233 } else {
1234 dm_pstable->cur_rfstate = RF_MAX;
1235 }
1236 } else {
1237 dm_pstable->cur_rfstate = RF_NORMAL;
1238 }
1239
1240 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
1241 if (dm_pstable->cur_rfstate == RF_SAVE) {
1242 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1243 0x1C0000, 0x2);
1244 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1245 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1246 0xFF000000, 0x63);
1247 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1248 0xC000, 0x2);
1249 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1250 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1251 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1252 } else {
1253 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1254 0x1CC000, reg_874);
1255 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1256 reg_c70);
1257 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1258 reg_85c);
1259 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1260 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1261 }
1262
1263 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
1264 }
1265 }
1266 EXPORT_SYMBOL(rtl92c_dm_rf_saving);
1267
1268 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1269 {
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1272 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1274
1275 if (((mac->link_state == MAC80211_NOLINK)) &&
1276 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1277 dm_pstable->rssi_val_min = 0;
1278 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
1279 }
1280
1281 if (mac->link_state == MAC80211_LINKED) {
1282 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1283 dm_pstable->rssi_val_min =
1284 rtlpriv->dm.entry_min_undec_sm_pwdb;
1285 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1286 "AP Client PWDB = 0x%lx\n",
1287 dm_pstable->rssi_val_min);
1288 } else {
1289 dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
1290 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1291 "STA Default Port PWDB = 0x%lx\n",
1292 dm_pstable->rssi_val_min);
1293 }
1294 } else {
1295 dm_pstable->rssi_val_min =
1296 rtlpriv->dm.entry_min_undec_sm_pwdb;
1297
1298 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1299 "AP Ext Port PWDB = 0x%lx\n",
1300 dm_pstable->rssi_val_min);
1301 }
1302
1303 if (IS_92C_SERIAL(rtlhal->version))
1304 ;/* rtl92c_dm_1r_cca(hw); */
1305 else
1306 rtl92c_dm_rf_saving(hw, false);
1307 }
1308
1309 void rtl92c_dm_init(struct ieee80211_hw *hw)
1310 {
1311 struct rtl_priv *rtlpriv = rtl_priv(hw);
1312
1313 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1314 rtl92c_dm_diginit(hw);
1315 rtl92c_dm_init_dynamic_txpower(hw);
1316 rtl92c_dm_init_edca_turbo(hw);
1317 rtl92c_dm_init_rate_adaptive_mask(hw);
1318 rtl92c_dm_initialize_txpower_tracking(hw);
1319 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1320 }
1321 EXPORT_SYMBOL(rtl92c_dm_init);
1322
1323 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
1324 {
1325 struct rtl_priv *rtlpriv = rtl_priv(hw);
1326 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1327 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1328 long undec_sm_pwdb;
1329
1330 if (!rtlpriv->dm.dynamic_txpower_enable)
1331 return;
1332
1333 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
1334 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1335 return;
1336 }
1337
1338 if ((mac->link_state < MAC80211_LINKED) &&
1339 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1340 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1341 "Not connected to any\n");
1342
1343 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1344
1345 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
1346 return;
1347 }
1348
1349 if (mac->link_state >= MAC80211_LINKED) {
1350 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1351 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1352 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1353 "AP Client PWDB = 0x%lx\n",
1354 undec_sm_pwdb);
1355 } else {
1356 undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
1357 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1358 "STA Default Port PWDB = 0x%lx\n",
1359 undec_sm_pwdb);
1360 }
1361 } else {
1362 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1363
1364 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1365 "AP Ext Port PWDB = 0x%lx\n",
1366 undec_sm_pwdb);
1367 }
1368
1369 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
1370 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1371 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1372 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
1373 } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
1374 (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
1375
1376 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1377 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1378 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
1379 } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
1380 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1381 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1382 "TXHIGHPWRLEVEL_NORMAL\n");
1383 }
1384
1385 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
1386 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1387 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
1388 rtlphy->current_channel);
1389 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1390 }
1391
1392 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
1393 }
1394
1395 void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1396 {
1397 struct rtl_priv *rtlpriv = rtl_priv(hw);
1398 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1399 bool fw_current_inpsmode = false;
1400 bool fw_ps_awake = true;
1401
1402 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1403 (u8 *) (&fw_current_inpsmode));
1404 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1405 (u8 *) (&fw_ps_awake));
1406
1407 if (ppsc->p2p_ps_info.p2p_ps_mode)
1408 fw_ps_awake = false;
1409
1410 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1411 fw_ps_awake)
1412 && (!ppsc->rfchange_inprogress)) {
1413 rtl92c_dm_pwdb_monitor(hw);
1414 rtl92c_dm_dig(hw);
1415 rtl92c_dm_false_alarm_counter_statistics(hw);
1416 rtl92c_dm_dynamic_bb_powersaving(hw);
1417 rtl92c_dm_dynamic_txpower(hw);
1418 rtl92c_dm_check_txpower_tracking(hw);
1419 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
1420 rtl92c_dm_bt_coexist(hw);
1421 rtl92c_dm_check_edca_turbo(hw);
1422 }
1423 }
1424 EXPORT_SYMBOL(rtl92c_dm_watchdog);
1425
1426 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
1427 {
1428 struct rtl_priv *rtlpriv = rtl_priv(hw);
1429 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1430 long undec_sm_pwdb;
1431 u8 curr_bt_rssi_state = 0x00;
1432
1433 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1434 undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
1435 } else {
1436 if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)
1437 undec_sm_pwdb = 100;
1438 else
1439 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1440 }
1441
1442 /* Check RSSI to determine HighPower/NormalPower state for
1443 * BT coexistence. */
1444 if (undec_sm_pwdb >= 67)
1445 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
1446 else if (undec_sm_pwdb < 62)
1447 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
1448
1449 /* Check RSSI to determine AMPDU setting for BT coexistence. */
1450 if (undec_sm_pwdb >= 40)
1451 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
1452 else if (undec_sm_pwdb <= 32)
1453 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
1454
1455 /* Marked RSSI state. It will be used to determine BT coexistence
1456 * setting later. */
1457 if (undec_sm_pwdb < 35)
1458 curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
1459 else
1460 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
1461
1462 /* Set Tx Power according to BT status. */
1463 if (undec_sm_pwdb >= 30)
1464 curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
1465 else if (undec_sm_pwdb < 25)
1466 curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
1467
1468 /* Check BT state related to BT_Idle in B/G mode. */
1469 if (undec_sm_pwdb < 15)
1470 curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
1471 else
1472 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
1473
1474 if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
1475 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
1476 return true;
1477 } else {
1478 return false;
1479 }
1480 }
1481 EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
1482
1483 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
1484 {
1485 struct rtl_priv *rtlpriv = rtl_priv(hw);
1486 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1487
1488 u32 polling, ratio_tx, ratio_pri;
1489 u32 bt_tx, bt_pri;
1490 u8 bt_state;
1491 u8 cur_service_type;
1492
1493 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1494 return false;
1495
1496 bt_state = rtl_read_byte(rtlpriv, 0x4fd);
1497 bt_tx = rtl_read_dword(rtlpriv, 0x488);
1498 bt_tx = bt_tx & 0x00ffffff;
1499 bt_pri = rtl_read_dword(rtlpriv, 0x48c);
1500 bt_pri = bt_pri & 0x00ffffff;
1501 polling = rtl_read_dword(rtlpriv, 0x490);
1502
1503 if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
1504 polling == 0xffffffff && bt_state == 0xff)
1505 return false;
1506
1507 bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
1508 if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
1509 rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
1510
1511 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1512 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
1513
1514 bt_state = bt_state |
1515 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1516 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1517 BIT_OFFSET_LEN_MASK_32(2, 1);
1518 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1519 }
1520 return true;
1521 }
1522
1523 ratio_tx = bt_tx * 1000 / polling;
1524 ratio_pri = bt_pri * 1000 / polling;
1525 rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
1526 rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
1527
1528 if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1529
1530 if ((ratio_tx < 30) && (ratio_pri < 30))
1531 cur_service_type = BT_IDLE;
1532 else if ((ratio_pri > 110) && (ratio_pri < 250))
1533 cur_service_type = BT_SCO;
1534 else if ((ratio_tx >= 200) && (ratio_pri >= 200))
1535 cur_service_type = BT_BUSY;
1536 else if ((ratio_tx >= 350) && (ratio_tx < 500))
1537 cur_service_type = BT_OTHERBUSY;
1538 else if (ratio_tx >= 500)
1539 cur_service_type = BT_PAN;
1540 else
1541 cur_service_type = BT_OTHER_ACTION;
1542
1543 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
1544 rtlpcipriv->bt_coexist.bt_service = cur_service_type;
1545 bt_state = bt_state |
1546 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1547 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1548 ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
1549 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
1550
1551 /* Add interrupt migration when bt is not ini
1552 * idle state (no traffic). */
1553 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1554 rtl_write_word(rtlpriv, 0x504, 0x0ccc);
1555 rtl_write_byte(rtlpriv, 0x506, 0x54);
1556 rtl_write_byte(rtlpriv, 0x507, 0x54);
1557 } else {
1558 rtl_write_byte(rtlpriv, 0x506, 0x00);
1559 rtl_write_byte(rtlpriv, 0x507, 0x00);
1560 }
1561
1562 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1563 return true;
1564 }
1565 }
1566
1567 return false;
1568
1569 }
1570
1571 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
1572 {
1573 struct rtl_priv *rtlpriv = rtl_priv(hw);
1574 static bool media_connect;
1575
1576 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1577 media_connect = false;
1578 } else {
1579 if (!media_connect) {
1580 media_connect = true;
1581 return true;
1582 }
1583 media_connect = true;
1584 }
1585
1586 return false;
1587 }
1588
1589 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
1590 {
1591 struct rtl_priv *rtlpriv = rtl_priv(hw);
1592 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1593
1594
1595 if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
1596 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
1597 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
1598 } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
1599 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
1600 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
1601 } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
1602 if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
1603 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
1604 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
1605 } else {
1606 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
1607 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
1608 }
1609 } else {
1610 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1611 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1612 }
1613
1614 if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
1615 (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
1616 (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
1617 (rtlpcipriv->bt_coexist.bt_rssi_state &
1618 BT_RSSI_STATE_BG_EDCA_LOW)) {
1619 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
1620 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
1621 }
1622 }
1623
1624 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte)
1625 {
1626 struct rtl_priv *rtlpriv = rtl_priv(hw);
1627 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1628
1629
1630 /* Only enable HW BT coexist when BT in "Busy" state. */
1631 if (rtlpriv->mac80211.vendor == PEER_CISCO &&
1632 rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
1633 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1634 } else {
1635 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
1636 (rtlpcipriv->bt_coexist.bt_rssi_state &
1637 BT_RSSI_STATE_NORMAL_POWER)) {
1638 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1639 } else if ((rtlpcipriv->bt_coexist.bt_service ==
1640 BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
1641 WIRELESS_MODE_N_24G) &&
1642 (rtlpcipriv->bt_coexist.bt_rssi_state &
1643 BT_RSSI_STATE_SPECIAL_LOW)) {
1644 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1645 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
1646 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1647 } else {
1648 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1649 }
1650 }
1651
1652 if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
1653 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
1654 else
1655 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
1656
1657 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1658 BT_RSSI_STATE_NORMAL_POWER) {
1659 rtl92c_bt_set_normal(hw);
1660 } else {
1661 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1662 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1663 }
1664
1665 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1666 rtlpriv->cfg->ops->set_rfreg(hw,
1667 RF90_PATH_A,
1668 0x1e,
1669 0xf0, 0xf);
1670 } else {
1671 rtlpriv->cfg->ops->set_rfreg(hw,
1672 RF90_PATH_A, 0x1e, 0xf0,
1673 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1674 }
1675
1676 if (!rtlpriv->dm.dynamic_txpower_enable) {
1677 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1678 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1679 BT_RSSI_STATE_TXPOWER_LOW) {
1680 rtlpriv->dm.dynamic_txhighpower_lvl =
1681 TXHIGHPWRLEVEL_BT2;
1682 } else {
1683 rtlpriv->dm.dynamic_txhighpower_lvl =
1684 TXHIGHPWRLEVEL_BT1;
1685 }
1686 } else {
1687 rtlpriv->dm.dynamic_txhighpower_lvl =
1688 TXHIGHPWRLEVEL_NORMAL;
1689 }
1690 rtl92c_phy_set_txpower_level(hw,
1691 rtlpriv->phy.current_channel);
1692 }
1693 }
1694
1695 static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
1696 {
1697 struct rtl_priv *rtlpriv = rtl_priv(hw);
1698 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1699 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1700 u8 tmp1byte = 0;
1701
1702 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version) &&
1703 rtlpcipriv->bt_coexist.bt_coexistence)
1704 tmp1byte |= BIT(5);
1705 if (rtlpcipriv->bt_coexist.bt_cur_state) {
1706 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
1707 rtl92c_bt_ant_isolation(hw, tmp1byte);
1708 } else {
1709 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1710 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
1711 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1712
1713 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1714 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1715 }
1716 }
1717
1718 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
1719 {
1720 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1721
1722 bool wifi_connect_change;
1723 bool bt_state_change;
1724 bool rssi_state_change;
1725
1726 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1727 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
1728
1729 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
1730 bt_state_change = rtl92c_bt_state_change(hw);
1731 rssi_state_change = rtl92c_bt_rssi_state_change(hw);
1732
1733 if (wifi_connect_change || bt_state_change || rssi_state_change)
1734 rtl92c_check_bt_change(hw);
1735 }
1736 }
1737 EXPORT_SYMBOL(rtl92c_dm_bt_coexist);
Linux with added FPC-III support