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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / rtl8192cu / hw.c
blobc3f2b55501aeeb065ab8ed956343af6acc656e8f
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../cam.h"
34 #include "../ps.h"
35 #include "../usb.h"
36 #include "reg.h"
37 #include "def.h"
38 #include "phy.h"
39 #include "mac.h"
40 #include "dm.h"
41 #include "hw.h"
42 #include "../rtl8192ce/hw.h"
43 #include "trx.h"
44 #include "led.h"
45 #include "table.h"
46
47 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
48 {
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 struct rtl_phy *rtlphy = &(rtlpriv->phy);
51 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
52
53 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
54 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
55 if (IS_HIGHT_PA(rtlefuse->board_type)) {
56 rtlphy->hwparam_tables[PHY_REG_PG].length =
57 RTL8192CUPHY_REG_Array_PG_HPLength;
58 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
59 RTL8192CUPHY_REG_Array_PG_HP;
60 } else {
61 rtlphy->hwparam_tables[PHY_REG_PG].length =
62 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
63 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
64 RTL8192CUPHY_REG_ARRAY_PG;
65 }
66 /* 2T */
67 rtlphy->hwparam_tables[PHY_REG_2T].length =
68 RTL8192CUPHY_REG_2TARRAY_LENGTH;
69 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
70 RTL8192CUPHY_REG_2TARRAY;
71 rtlphy->hwparam_tables[RADIOA_2T].length =
72 RTL8192CURADIOA_2TARRAYLENGTH;
73 rtlphy->hwparam_tables[RADIOA_2T].pdata =
74 RTL8192CURADIOA_2TARRAY;
75 rtlphy->hwparam_tables[RADIOB_2T].length =
76 RTL8192CURADIOB_2TARRAYLENGTH;
77 rtlphy->hwparam_tables[RADIOB_2T].pdata =
78 RTL8192CU_RADIOB_2TARRAY;
79 rtlphy->hwparam_tables[AGCTAB_2T].length =
80 RTL8192CUAGCTAB_2TARRAYLENGTH;
81 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
82 RTL8192CUAGCTAB_2TARRAY;
83 /* 1T */
84 if (IS_HIGHT_PA(rtlefuse->board_type)) {
85 rtlphy->hwparam_tables[PHY_REG_1T].length =
86 RTL8192CUPHY_REG_1T_HPArrayLength;
87 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
88 RTL8192CUPHY_REG_1T_HPArray;
89 rtlphy->hwparam_tables[RADIOA_1T].length =
90 RTL8192CURadioA_1T_HPArrayLength;
91 rtlphy->hwparam_tables[RADIOA_1T].pdata =
92 RTL8192CURadioA_1T_HPArray;
93 rtlphy->hwparam_tables[RADIOB_1T].length =
94 RTL8192CURADIOB_1TARRAYLENGTH;
95 rtlphy->hwparam_tables[RADIOB_1T].pdata =
96 RTL8192CU_RADIOB_1TARRAY;
97 rtlphy->hwparam_tables[AGCTAB_1T].length =
98 RTL8192CUAGCTAB_1T_HPArrayLength;
99 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
100 Rtl8192CUAGCTAB_1T_HPArray;
101 } else {
102 rtlphy->hwparam_tables[PHY_REG_1T].length =
103 RTL8192CUPHY_REG_1TARRAY_LENGTH;
104 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
105 RTL8192CUPHY_REG_1TARRAY;
106 rtlphy->hwparam_tables[RADIOA_1T].length =
107 RTL8192CURADIOA_1TARRAYLENGTH;
108 rtlphy->hwparam_tables[RADIOA_1T].pdata =
109 RTL8192CU_RADIOA_1TARRAY;
110 rtlphy->hwparam_tables[RADIOB_1T].length =
111 RTL8192CURADIOB_1TARRAYLENGTH;
112 rtlphy->hwparam_tables[RADIOB_1T].pdata =
113 RTL8192CU_RADIOB_1TARRAY;
114 rtlphy->hwparam_tables[AGCTAB_1T].length =
115 RTL8192CUAGCTAB_1TARRAYLENGTH;
116 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
117 RTL8192CUAGCTAB_1TARRAY;
118 }
119 }
120
121 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
122 bool autoload_fail,
123 u8 *hwinfo)
124 {
125 struct rtl_priv *rtlpriv = rtl_priv(hw);
126 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
127 u8 rf_path, index, tempval;
128 u16 i;
129
130 for (rf_path = 0; rf_path < 2; rf_path++) {
131 for (i = 0; i < 3; i++) {
132 if (!autoload_fail) {
133 rtlefuse->
134 eeprom_chnlarea_txpwr_cck[rf_path][i] =
135 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
136 rtlefuse->
137 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
139 i];
140 } else {
141 rtlefuse->
142 eeprom_chnlarea_txpwr_cck[rf_path][i] =
143 EEPROM_DEFAULT_TXPOWERLEVEL;
144 rtlefuse->
145 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
147 }
148 }
149 }
150 for (i = 0; i < 3; i++) {
151 if (!autoload_fail)
152 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
153 else
154 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
155 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
156 (tempval & 0xf);
157 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
158 ((tempval & 0xf0) >> 4);
159 }
160 for (rf_path = 0; rf_path < 2; rf_path++)
161 for (i = 0; i < 3; i++)
162 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
163 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
164 rf_path, i,
165 rtlefuse->
166 eeprom_chnlarea_txpwr_cck[rf_path][i]);
167 for (rf_path = 0; rf_path < 2; rf_path++)
168 for (i = 0; i < 3; i++)
169 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
170 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
171 rf_path, i,
172 rtlefuse->
173 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
174 for (rf_path = 0; rf_path < 2; rf_path++)
175 for (i = 0; i < 3; i++)
176 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
177 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
178 rf_path, i,
179 rtlefuse->
180 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
181 for (rf_path = 0; rf_path < 2; rf_path++) {
182 for (i = 0; i < 14; i++) {
183 index = _rtl92c_get_chnl_group((u8) i);
184 rtlefuse->txpwrlevel_cck[rf_path][i] =
185 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
186 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
187 rtlefuse->
188 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
189 if ((rtlefuse->
190 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
191 rtlefuse->
192 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
193 > 0) {
194 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
195 rtlefuse->
196 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
197 [index] - rtlefuse->
198 eprom_chnl_txpwr_ht40_2sdf[rf_path]
199 [index];
200 } else {
201 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
202 }
203 }
204 for (i = 0; i < 14; i++) {
205 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
206 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
207 rtlefuse->txpwrlevel_cck[rf_path][i],
208 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
209 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
210 }
211 }
212 for (i = 0; i < 3; i++) {
213 if (!autoload_fail) {
214 rtlefuse->eeprom_pwrlimit_ht40[i] =
215 hwinfo[EEPROM_TXPWR_GROUP + i];
216 rtlefuse->eeprom_pwrlimit_ht20[i] =
217 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
218 } else {
219 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
220 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
221 }
222 }
223 for (rf_path = 0; rf_path < 2; rf_path++) {
224 for (i = 0; i < 14; i++) {
225 index = _rtl92c_get_chnl_group((u8) i);
226 if (rf_path == RF90_PATH_A) {
227 rtlefuse->pwrgroup_ht20[rf_path][i] =
228 (rtlefuse->eeprom_pwrlimit_ht20[index]
229 & 0xf);
230 rtlefuse->pwrgroup_ht40[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht40[index]
232 & 0xf);
233 } else if (rf_path == RF90_PATH_B) {
234 rtlefuse->pwrgroup_ht20[rf_path][i] =
235 ((rtlefuse->eeprom_pwrlimit_ht20[index]
236 & 0xf0) >> 4);
237 rtlefuse->pwrgroup_ht40[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht40[index]
239 & 0xf0) >> 4);
240 }
241 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
242 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
243 rf_path, i,
244 rtlefuse->pwrgroup_ht20[rf_path][i]);
245 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
246 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
247 rf_path, i,
248 rtlefuse->pwrgroup_ht40[rf_path][i]);
249 }
250 }
251 for (i = 0; i < 14; i++) {
252 index = _rtl92c_get_chnl_group((u8) i);
253 if (!autoload_fail)
254 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
255 else
256 tempval = EEPROM_DEFAULT_HT20_DIFF;
257 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
258 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
259 ((tempval >> 4) & 0xF);
260 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
261 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
262 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
263 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
264 index = _rtl92c_get_chnl_group((u8) i);
265 if (!autoload_fail)
266 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
267 else
268 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
270 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
271 ((tempval >> 4) & 0xF);
272 }
273 rtlefuse->legacy_ht_txpowerdiff =
274 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
275 for (i = 0; i < 14; i++)
276 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
277 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
278 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
279 for (i = 0; i < 14; i++)
280 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
281 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
282 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
283 for (i = 0; i < 14; i++)
284 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
285 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
286 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
287 for (i = 0; i < 14; i++)
288 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
289 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
290 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
291 if (!autoload_fail)
292 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
293 else
294 rtlefuse->eeprom_regulatory = 0;
295 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
296 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
297 if (!autoload_fail) {
298 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
299 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
300 } else {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
303 }
304 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
305 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
306 rtlefuse->eeprom_tssi[RF90_PATH_A],
307 rtlefuse->eeprom_tssi[RF90_PATH_B]);
308 if (!autoload_fail)
309 tempval = hwinfo[EEPROM_THERMAL_METER];
310 else
311 tempval = EEPROM_DEFAULT_THERMALMETER;
312 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
313 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
314 rtlefuse->eeprom_thermalmeter > 0x1c)
315 rtlefuse->eeprom_thermalmeter = 0x12;
316 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
317 rtlefuse->apk_thermalmeterignore = true;
318 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
319 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
320 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
321 }
322
323 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
324 {
325 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
326 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
327 u8 boardType;
328
329 if (IS_NORMAL_CHIP(rtlhal->version)) {
330 boardType = ((contents[EEPROM_RF_OPT1]) &
331 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
332 } else {
333 boardType = contents[EEPROM_RF_OPT4];
334 boardType &= BOARD_TYPE_TEST_MASK;
335 }
336 rtlefuse->board_type = boardType;
337 if (IS_HIGHT_PA(rtlefuse->board_type))
338 rtlefuse->external_pa = 1;
339 pr_info("Board Type %x\n", rtlefuse->board_type);
340 }
341
342 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
343 {
344 struct rtl_priv *rtlpriv = rtl_priv(hw);
345 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
346 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
347 u16 i, usvalue;
348 u8 hwinfo[HWSET_MAX_SIZE] = {0};
349 u16 eeprom_id;
350
351 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
352 rtl_efuse_shadow_map_update(hw);
353 memcpy((void *)hwinfo,
354 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
355 HWSET_MAX_SIZE);
356 } else if (rtlefuse->epromtype == EEPROM_93C46) {
357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
358 "RTL819X Not boot from eeprom, check it !!\n");
359 }
360 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
361 hwinfo, HWSET_MAX_SIZE);
362 eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
363 if (eeprom_id != RTL8190_EEPROM_ID) {
364 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
365 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
366 rtlefuse->autoload_failflag = true;
367 } else {
368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
369 rtlefuse->autoload_failflag = false;
370 }
371 if (rtlefuse->autoload_failflag)
372 return;
373 for (i = 0; i < 6; i += 2) {
374 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
375 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
376 }
377 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
378 _rtl92cu_read_txpower_info_from_hwpg(hw,
379 rtlefuse->autoload_failflag, hwinfo);
380 rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
381 rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
382 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
383 rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
384 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
385 rtlefuse->eeprom_version =
386 le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
387 rtlefuse->txpwr_fromeprom = true;
388 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
390 rtlefuse->eeprom_oemid);
391 if (rtlhal->oem_id == RT_CID_DEFAULT) {
392 switch (rtlefuse->eeprom_oemid) {
393 case EEPROM_CID_DEFAULT:
394 if (rtlefuse->eeprom_did == 0x8176) {
395 if ((rtlefuse->eeprom_svid == 0x103C &&
396 rtlefuse->eeprom_smid == 0x1629))
397 rtlhal->oem_id = RT_CID_819x_HP;
398 else
399 rtlhal->oem_id = RT_CID_DEFAULT;
400 } else {
401 rtlhal->oem_id = RT_CID_DEFAULT;
402 }
403 break;
404 case EEPROM_CID_TOSHIBA:
405 rtlhal->oem_id = RT_CID_TOSHIBA;
406 break;
407 case EEPROM_CID_QMI:
408 rtlhal->oem_id = RT_CID_819x_QMI;
409 break;
410 case EEPROM_CID_WHQL:
411 default:
412 rtlhal->oem_id = RT_CID_DEFAULT;
413 break;
414 }
415 }
416 _rtl92cu_read_board_type(hw, hwinfo);
417 }
418
419 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
420 {
421 struct rtl_priv *rtlpriv = rtl_priv(hw);
422 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
423 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
424
425 switch (rtlhal->oem_id) {
426 case RT_CID_819x_HP:
427 usb_priv->ledctl.led_opendrain = true;
428 break;
429 case RT_CID_819x_Lenovo:
430 case RT_CID_DEFAULT:
431 case RT_CID_TOSHIBA:
432 case RT_CID_CCX:
433 case RT_CID_819x_Acer:
434 case RT_CID_WHQL:
435 default:
436 break;
437 }
438 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
439 rtlhal->oem_id);
440 }
441
442 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
443 {
444
445 struct rtl_priv *rtlpriv = rtl_priv(hw);
446 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
447 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
448 u8 tmp_u1b;
449
450 if (!IS_NORMAL_CHIP(rtlhal->version))
451 return;
452 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
453 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
454 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
455 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
456 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
457 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
458 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
459 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
460 _rtl92cu_read_adapter_info(hw);
461 _rtl92cu_hal_customized_behavior(hw);
462 return;
463 }
464
465 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
466 {
467 struct rtl_priv *rtlpriv = rtl_priv(hw);
468 int status = 0;
469 u16 value16;
470 u8 value8;
471 /* polling autoload done. */
472 u32 pollingCount = 0;
473
474 do {
475 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
476 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
477 "Autoload Done!\n");
478 break;
479 }
480 if (pollingCount++ > 100) {
481 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
482 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
483 return -ENODEV;
484 }
485 } while (true);
486 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
487 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
488 /* Power on when re-enter from IPS/Radio off/card disable */
489 /* enable SPS into PWM mode */
490 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
491 udelay(100);
492 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
493 if (0 == (value8 & LDV12_EN)) {
494 value8 |= LDV12_EN;
495 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
496 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
497 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
498 value8);
499 udelay(100);
500 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
501 value8 &= ~ISO_MD2PP;
502 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
503 }
504 /* auto enable WLAN */
505 pollingCount = 0;
506 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
507 value16 |= APFM_ONMAC;
508 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
509 do {
510 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
511 pr_info("MAC auto ON okay!\n");
512 break;
513 }
514 if (pollingCount++ > 100) {
515 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
516 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
517 return -ENODEV;
518 }
519 } while (true);
520 /* Enable Radio ,GPIO ,and LED function */
521 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
522 /* release RF digital isolation */
523 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
524 value16 &= ~ISO_DIOR;
525 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
526 /* Reconsider when to do this operation after asking HWSD. */
527 pollingCount = 0;
528 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
529 REG_APSD_CTRL) & ~BIT(6)));
530 do {
531 pollingCount++;
532 } while ((pollingCount < 200) &&
533 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
534 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
535 value16 = rtl_read_word(rtlpriv, REG_CR);
536 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
537 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
538 rtl_write_word(rtlpriv, REG_CR, value16);
539 return status;
540 }
541
542 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
543 bool wmm_enable,
544 u8 out_ep_num,
545 u8 queue_sel)
546 {
547 struct rtl_priv *rtlpriv = rtl_priv(hw);
548 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
549 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
550 u32 outEPNum = (u32)out_ep_num;
551 u32 numHQ = 0;
552 u32 numLQ = 0;
553 u32 numNQ = 0;
554 u32 numPubQ;
555 u32 value32;
556 u8 value8;
557 u32 txQPageNum, txQPageUnit, txQRemainPage;
558
559 if (!wmm_enable) {
560 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
561 CHIP_A_PAGE_NUM_PUBQ;
562 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
563
564 txQPageUnit = txQPageNum/outEPNum;
565 txQRemainPage = txQPageNum % outEPNum;
566 if (queue_sel & TX_SELE_HQ)
567 numHQ = txQPageUnit;
568 if (queue_sel & TX_SELE_LQ)
569 numLQ = txQPageUnit;
570 /* HIGH priority queue always present in the configuration of
571 * 2 out-ep. Remainder pages have assigned to High queue */
572 if ((outEPNum > 1) && (txQRemainPage))
573 numHQ += txQRemainPage;
574 /* NOTE: This step done before writting REG_RQPN. */
575 if (isChipN) {
576 if (queue_sel & TX_SELE_NQ)
577 numNQ = txQPageUnit;
578 value8 = (u8)_NPQ(numNQ);
579 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
580 }
581 } else {
582 /* for WMM ,number of out-ep must more than or equal to 2! */
583 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
584 WMM_CHIP_A_PAGE_NUM_PUBQ;
585 if (queue_sel & TX_SELE_HQ) {
586 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
587 WMM_CHIP_A_PAGE_NUM_HPQ;
588 }
589 if (queue_sel & TX_SELE_LQ) {
590 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
591 WMM_CHIP_A_PAGE_NUM_LPQ;
592 }
593 /* NOTE: This step done before writting REG_RQPN. */
594 if (isChipN) {
595 if (queue_sel & TX_SELE_NQ)
596 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
597 value8 = (u8)_NPQ(numNQ);
598 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
599 }
600 }
601 /* TX DMA */
602 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
603 rtl_write_dword(rtlpriv, REG_RQPN, value32);
604 }
605
606 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
607 {
608 struct rtl_priv *rtlpriv = rtl_priv(hw);
609 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
610 u8 txpktbuf_bndy;
611 u8 value8;
612
613 if (!wmm_enable)
614 txpktbuf_bndy = TX_PAGE_BOUNDARY;
615 else /* for WMM */
616 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
617 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
618 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
619 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
620 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
621 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
622 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
623 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
624 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
625 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
626 rtl_write_byte(rtlpriv, REG_PBP, value8);
627 }
628
629 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
630 u16 bkQ, u16 viQ, u16 voQ,
631 u16 mgtQ, u16 hiQ)
632 {
633 struct rtl_priv *rtlpriv = rtl_priv(hw);
634 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
635
636 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
637 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
638 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
639 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
640 }
641
642 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
643 bool wmm_enable,
644 u8 queue_sel)
645 {
646 u16 uninitialized_var(value);
647
648 switch (queue_sel) {
649 case TX_SELE_HQ:
650 value = QUEUE_HIGH;
651 break;
652 case TX_SELE_LQ:
653 value = QUEUE_LOW;
654 break;
655 case TX_SELE_NQ:
656 value = QUEUE_NORMAL;
657 break;
658 default:
659 WARN_ON(1); /* Shall not reach here! */
660 break;
661 }
662 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
663 value, value);
664 pr_info("Tx queue select: 0x%02x\n", queue_sel);
665 }
666
667 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
668 bool wmm_enable,
669 u8 queue_sel)
670 {
671 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
672 u16 uninitialized_var(valueHi);
673 u16 uninitialized_var(valueLow);
674
675 switch (queue_sel) {
676 case (TX_SELE_HQ | TX_SELE_LQ):
677 valueHi = QUEUE_HIGH;
678 valueLow = QUEUE_LOW;
679 break;
680 case (TX_SELE_NQ | TX_SELE_LQ):
681 valueHi = QUEUE_NORMAL;
682 valueLow = QUEUE_LOW;
683 break;
684 case (TX_SELE_HQ | TX_SELE_NQ):
685 valueHi = QUEUE_HIGH;
686 valueLow = QUEUE_NORMAL;
687 break;
688 default:
689 WARN_ON(1);
690 break;
691 }
692 if (!wmm_enable) {
693 beQ = valueLow;
694 bkQ = valueLow;
695 viQ = valueHi;
696 voQ = valueHi;
697 mgtQ = valueHi;
698 hiQ = valueHi;
699 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
700 beQ = valueHi;
701 bkQ = valueLow;
702 viQ = valueLow;
703 voQ = valueHi;
704 mgtQ = valueHi;
705 hiQ = valueHi;
706 }
707 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
708 pr_info("Tx queue select: 0x%02x\n", queue_sel);
709 }
710
711 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
712 bool wmm_enable,
713 u8 queue_sel)
714 {
715 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
716 struct rtl_priv *rtlpriv = rtl_priv(hw);
717
718 if (!wmm_enable) { /* typical setting */
719 beQ = QUEUE_LOW;
720 bkQ = QUEUE_LOW;
721 viQ = QUEUE_NORMAL;
722 voQ = QUEUE_HIGH;
723 mgtQ = QUEUE_HIGH;
724 hiQ = QUEUE_HIGH;
725 } else { /* for WMM */
726 beQ = QUEUE_LOW;
727 bkQ = QUEUE_NORMAL;
728 viQ = QUEUE_NORMAL;
729 voQ = QUEUE_HIGH;
730 mgtQ = QUEUE_HIGH;
731 hiQ = QUEUE_HIGH;
732 }
733 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
734 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
735 queue_sel);
736 }
737
738 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
739 bool wmm_enable,
740 u8 out_ep_num,
741 u8 queue_sel)
742 {
743 switch (out_ep_num) {
744 case 1:
745 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
746 queue_sel);
747 break;
748 case 2:
749 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
750 queue_sel);
751 break;
752 case 3:
753 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
754 queue_sel);
755 break;
756 default:
757 WARN_ON(1); /* Shall not reach here! */
758 break;
759 }
760 }
761
762 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
763 bool wmm_enable,
764 u8 out_ep_num,
765 u8 queue_sel)
766 {
767 u8 hq_sele = 0;
768 struct rtl_priv *rtlpriv = rtl_priv(hw);
769
770 switch (out_ep_num) {
771 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
772 if (!wmm_enable) /* typical setting */
773 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
774 HQSEL_HIQ;
775 else /* for WMM */
776 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
777 HQSEL_HIQ;
778 break;
779 case 1:
780 if (TX_SELE_LQ == queue_sel) {
781 /* map all endpoint to Low queue */
782 hq_sele = 0;
783 } else if (TX_SELE_HQ == queue_sel) {
784 /* map all endpoint to High queue */
785 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
786 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
787 }
788 break;
789 default:
790 WARN_ON(1); /* Shall not reach here! */
791 break;
792 }
793 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
795 hq_sele);
796 }
797
798 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
799 bool wmm_enable,
800 u8 out_ep_num,
801 u8 queue_sel)
802 {
803 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
804 if (IS_NORMAL_CHIP(rtlhal->version))
805 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
806 queue_sel);
807 else
808 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
809 queue_sel);
810 }
811
812 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
813 {
814 }
815
816 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
817 {
818 u16 value16;
819
820 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
822
823 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
824 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
825 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
826 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
827 /* Accept all multicast address */
828 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
829 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
830 /* Accept all management frames */
831 value16 = 0xFFFF;
832 rtl92c_set_mgt_filter(hw, value16);
833 /* Reject all control frame - default value is 0 */
834 rtl92c_set_ctrl_filter(hw, 0x0);
835 /* Accept all data frames */
836 value16 = 0xFFFF;
837 rtl92c_set_data_filter(hw, value16);
838 }
839
840 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
841 {
842 struct rtl_priv *rtlpriv = rtl_priv(hw);
843 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
844 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
845 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
846 int err = 0;
847 u32 boundary = 0;
848 u8 wmm_enable = false; /* TODO */
849 u8 out_ep_nums = rtlusb->out_ep_nums;
850 u8 queue_sel = rtlusb->out_queue_sel;
851 err = _rtl92cu_init_power_on(hw);
852
853 if (err) {
854 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
855 "Failed to init power on!\n");
856 return err;
857 }
858 if (!wmm_enable) {
859 boundary = TX_PAGE_BOUNDARY;
860 } else { /* for WMM */
861 boundary = (IS_NORMAL_CHIP(rtlhal->version))
862 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
863 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
864 }
865 if (false == rtl92c_init_llt_table(hw, boundary)) {
866 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
867 "Failed to init LLT Table!\n");
868 return -EINVAL;
869 }
870 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
871 queue_sel);
872 _rtl92c_init_trx_buffer(hw, wmm_enable);
873 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
874 queue_sel);
875 /* Get Rx PHY status in order to report RSSI and others. */
876 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
877 rtl92c_init_interrupt(hw);
878 rtl92c_init_network_type(hw);
879 _rtl92cu_init_wmac_setting(hw);
880 rtl92c_init_adaptive_ctrl(hw);
881 rtl92c_init_edca(hw);
882 rtl92c_init_rate_fallback(hw);
883 rtl92c_init_retry_function(hw);
884 _rtl92cu_init_usb_aggregation(hw);
885 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
886 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
887 rtl92c_init_beacon_parameters(hw, rtlhal->version);
888 rtl92c_init_ampdu_aggregation(hw);
889 rtl92c_init_beacon_max_error(hw, true);
890 return err;
891 }
892
893 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
894 {
895 struct rtl_priv *rtlpriv = rtl_priv(hw);
896 u8 sec_reg_value = 0x0;
897 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
898
899 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
900 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
901 rtlpriv->sec.pairwise_enc_algorithm,
902 rtlpriv->sec.group_enc_algorithm);
903 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
904 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
905 "not open sw encryption\n");
906 return;
907 }
908 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
909 if (rtlpriv->sec.use_defaultkey) {
910 sec_reg_value |= SCR_TxUseDK;
911 sec_reg_value |= SCR_RxUseDK;
912 }
913 if (IS_NORMAL_CHIP(rtlhal->version))
914 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
915 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
916 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
917 sec_reg_value);
918 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
919 }
920
921 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
922 {
923 struct rtl_priv *rtlpriv = rtl_priv(hw);
924 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
925
926 /* To Fix MAC loopback mode fail. */
927 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
928 rtl_write_byte(rtlpriv, 0x15, 0xe9);
929 /* HW SEQ CTRL */
930 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
931 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
932 /* fixed USB interface interference issue */
933 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
934 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
935 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
936 rtlusb->reg_bcn_ctrl_val = 0x18;
937 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
938 }
939
940 static void _InitPABias(struct ieee80211_hw *hw)
941 {
942 struct rtl_priv *rtlpriv = rtl_priv(hw);
943 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
944 u8 pa_setting;
945
946 /* FIXED PA current issue */
947 pa_setting = efuse_read_1byte(hw, 0x1FA);
948 if (!(pa_setting & BIT(0))) {
949 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
950 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
951 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
952 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
953 }
954 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
955 IS_92C_SERIAL(rtlhal->version)) {
956 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
957 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
958 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
959 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
960 }
961 if (!(pa_setting & BIT(4))) {
962 pa_setting = rtl_read_byte(rtlpriv, 0x16);
963 pa_setting &= 0x0F;
964 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
965 }
966 }
967
968 static void _update_mac_setting(struct ieee80211_hw *hw)
969 {
970 struct rtl_priv *rtlpriv = rtl_priv(hw);
971 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
972
973 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
974 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
975 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
976 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
977 }
978
979 int rtl92cu_hw_init(struct ieee80211_hw *hw)
980 {
981 struct rtl_priv *rtlpriv = rtl_priv(hw);
982 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
983 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
984 struct rtl_phy *rtlphy = &(rtlpriv->phy);
985 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
986 int err = 0;
987 static bool iqk_initialized;
988 unsigned long flags;
989
990 /* As this function can take a very long time (up to 350 ms)
991 * and can be called with irqs disabled, reenable the irqs
992 * to let the other devices continue being serviced.
993 *
994 * It is safe doing so since our own interrupts will only be enabled
995 * in a subsequent step.
996 */
997 local_save_flags(flags);
998 local_irq_enable();
999
1000 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1001 err = _rtl92cu_init_mac(hw);
1002 if (err) {
1003 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
1004 goto exit;
1005 }
1006 err = rtl92c_download_fw(hw);
1007 if (err) {
1008 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1009 "Failed to download FW. Init HW without FW now..\n");
1010 err = 1;
1011 goto exit;
1012 }
1013 rtlhal->last_hmeboxnum = 0; /* h2c */
1014 _rtl92cu_phy_param_tab_init(hw);
1015 rtl92cu_phy_mac_config(hw);
1016 rtl92cu_phy_bb_config(hw);
1017 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1018 rtl92c_phy_rf_config(hw);
1019 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1020 !IS_92C_SERIAL(rtlhal->version)) {
1021 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1022 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1023 }
1024 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1025 RF_CHNLBW, RFREG_OFFSET_MASK);
1026 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1027 RF_CHNLBW, RFREG_OFFSET_MASK);
1028 rtl92cu_bb_block_on(hw);
1029 rtl_cam_reset_all_entry(hw);
1030 rtl92cu_enable_hw_security_config(hw);
1031 ppsc->rfpwr_state = ERFON;
1032 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1033 if (ppsc->rfpwr_state == ERFON) {
1034 rtl92c_phy_set_rfpath_switch(hw, 1);
1035 if (iqk_initialized) {
1036 rtl92c_phy_iq_calibrate(hw, false);
1037 } else {
1038 rtl92c_phy_iq_calibrate(hw, false);
1039 iqk_initialized = true;
1040 }
1041 rtl92c_dm_check_txpower_tracking(hw);
1042 rtl92c_phy_lc_calibrate(hw);
1043 }
1044 _rtl92cu_hw_configure(hw);
1045 _InitPABias(hw);
1046 _update_mac_setting(hw);
1047 rtl92c_dm_init(hw);
1048 exit:
1049 local_irq_restore(flags);
1050 return err;
1051 }
1052
1053 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1054 {
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056 /**************************************
1057 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1058 b. RF path 0 offset 0x00 = 0x00 disable RF
1059 c. APSD_CTRL 0x600[7:0] = 0x40
1060 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1061 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1062 ***************************************/
1063 u8 eRFPath = 0, value8 = 0;
1064 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1065 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1066
1067 value8 |= APSDOFF;
1068 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1069 value8 = 0;
1070 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1071 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1072 value8 &= (~FEN_BB_GLB_RSTn);
1073 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1074 }
1075
1076 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1077 {
1078 struct rtl_priv *rtlpriv = rtl_priv(hw);
1079 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1080
1081 if (rtlhal->fw_version <= 0x20) {
1082 /*****************************
1083 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1084 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1085 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1086 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1087 ******************************/
1088 u16 valu16 = 0;
1089
1090 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1091 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1092 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1093 (~FEN_CPUEN))); /* reset MCU ,8051 */
1094 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1095 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1096 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1097 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1098 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1099 FEN_CPUEN)); /* enable MCU ,8051 */
1100 } else {
1101 u8 retry_cnts = 0;
1102
1103 /* IF fw in RAM code, do reset */
1104 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1105 /* reset MCU ready status */
1106 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1107 /* 8051 reset by self */
1108 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1109 while ((retry_cnts++ < 100) &&
1110 (FEN_CPUEN & rtl_read_word(rtlpriv,
1111 REG_SYS_FUNC_EN))) {
1112 udelay(50);
1113 }
1114 if (retry_cnts >= 100) {
1115 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1116 "#####=> 8051 reset failed!.........................\n");
1117 /* if 8051 reset fail, reset MAC. */
1118 rtl_write_byte(rtlpriv,
1119 REG_SYS_FUNC_EN + 1,
1120 0x50);
1121 udelay(100);
1122 }
1123 }
1124 /* Reset MAC and Enable 8051 */
1125 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1126 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1127 }
1128 if (bWithoutHWSM) {
1129 /*****************************
1130 Without HW auto state machine
1131 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1132 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1133 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1134 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1135 ******************************/
1136 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1137 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1138 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1139 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1140 }
1141 }
1142
1143 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1144 {
1145 struct rtl_priv *rtlpriv = rtl_priv(hw);
1146 /*****************************
1147 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1148 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1149 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1150 ******************************/
1151 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1152 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1153 }
1154
1155 static void _DisableGPIO(struct ieee80211_hw *hw)
1156 {
1157 struct rtl_priv *rtlpriv = rtl_priv(hw);
1158 /***************************************
1159 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1160 k. Value = GPIO_PIN_CTRL[7:0]
1161 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1162 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1163 n. LEDCFG 0x4C[15:0] = 0x8080
1164 ***************************************/
1165 u8 value8;
1166 u16 value16;
1167 u32 value32;
1168
1169 /* 1. Disable GPIO[7:0] */
1170 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1171 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1172 value8 = (u8) (value32&0x000000FF);
1173 value32 |= ((value8<<8) | 0x00FF0000);
1174 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1175 /* 2. Disable GPIO[10:8] */
1176 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1177 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1178 value8 = (u8) (value16&0x000F);
1179 value16 |= ((value8<<4) | 0x0780);
1180 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1181 /* 3. Disable LED0 & 1 */
1182 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1183 }
1184
1185 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1186 {
1187 struct rtl_priv *rtlpriv = rtl_priv(hw);
1188 u16 value16 = 0;
1189 u8 value8 = 0;
1190
1191 if (bWithoutHWSM) {
1192 /*****************************
1193 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1194 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1195 r. When driver call disable, the ASIC will turn off remaining
1196 clock automatically
1197 ******************************/
1198 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1199 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1200 value8 &= (~LDV12_EN);
1201 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1202 }
1203
1204 /*****************************
1205 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1206 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1207 ******************************/
1208 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1209 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1210 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1211 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1212 }
1213
1214 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1215 {
1216 /* ==== RF Off Sequence ==== */
1217 _DisableRFAFEAndResetBB(hw);
1218 /* ==== Reset digital sequence ====== */
1219 _ResetDigitalProcedure1(hw, false);
1220 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1221 _DisableGPIO(hw);
1222 /* ==== Disable analog sequence === */
1223 _DisableAnalog(hw, false);
1224 }
1225
1226 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1227 {
1228 /*==== RF Off Sequence ==== */
1229 _DisableRFAFEAndResetBB(hw);
1230 /* ==== Reset digital sequence ====== */
1231 _ResetDigitalProcedure1(hw, true);
1232 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1233 _DisableGPIO(hw);
1234 /* ==== Reset digital sequence ====== */
1235 _ResetDigitalProcedure2(hw);
1236 /* ==== Disable analog sequence === */
1237 _DisableAnalog(hw, true);
1238 }
1239
1240 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1241 u8 set_bits, u8 clear_bits)
1242 {
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1245
1246 rtlusb->reg_bcn_ctrl_val |= set_bits;
1247 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1248 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1249 }
1250
1251 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1252 {
1253 struct rtl_priv *rtlpriv = rtl_priv(hw);
1254 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1255 u8 tmp1byte = 0;
1256 if (IS_NORMAL_CHIP(rtlhal->version)) {
1257 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1258 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1259 tmp1byte & (~BIT(6)));
1260 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1261 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1262 tmp1byte &= ~(BIT(0));
1263 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1264 } else {
1265 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1266 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1267 }
1268 }
1269
1270 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1271 {
1272 struct rtl_priv *rtlpriv = rtl_priv(hw);
1273 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1274 u8 tmp1byte = 0;
1275
1276 if (IS_NORMAL_CHIP(rtlhal->version)) {
1277 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1278 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1279 tmp1byte | BIT(6));
1280 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1281 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1282 tmp1byte |= BIT(0);
1283 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1284 } else {
1285 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1286 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1287 }
1288 }
1289
1290 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1291 {
1292 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1294
1295 if (IS_NORMAL_CHIP(rtlhal->version))
1296 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1297 else
1298 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1299 }
1300
1301 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1302 {
1303 struct rtl_priv *rtlpriv = rtl_priv(hw);
1304 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1305
1306 if (IS_NORMAL_CHIP(rtlhal->version))
1307 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1308 else
1309 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1310 }
1311
1312 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1313 enum nl80211_iftype type)
1314 {
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1317 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1318
1319 bt_msr &= 0xfc;
1320 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1321 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1322 NL80211_IFTYPE_STATION) {
1323 _rtl92cu_stop_tx_beacon(hw);
1324 _rtl92cu_enable_bcn_sub_func(hw);
1325 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1326 _rtl92cu_resume_tx_beacon(hw);
1327 _rtl92cu_disable_bcn_sub_func(hw);
1328 } else {
1329 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1330 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1331 type);
1332 }
1333 switch (type) {
1334 case NL80211_IFTYPE_UNSPECIFIED:
1335 bt_msr |= MSR_NOLINK;
1336 ledaction = LED_CTL_LINK;
1337 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1338 "Set Network type to NO LINK!\n");
1339 break;
1340 case NL80211_IFTYPE_ADHOC:
1341 bt_msr |= MSR_ADHOC;
1342 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1343 "Set Network type to Ad Hoc!\n");
1344 break;
1345 case NL80211_IFTYPE_STATION:
1346 bt_msr |= MSR_INFRA;
1347 ledaction = LED_CTL_LINK;
1348 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1349 "Set Network type to STA!\n");
1350 break;
1351 case NL80211_IFTYPE_AP:
1352 bt_msr |= MSR_AP;
1353 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1354 "Set Network type to AP!\n");
1355 break;
1356 default:
1357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1358 "Network type %d not supported!\n", type);
1359 goto error_out;
1360 }
1361 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1362 rtlpriv->cfg->ops->led_control(hw, ledaction);
1363 if ((bt_msr & 0xfc) == MSR_AP)
1364 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1365 else
1366 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1367 return 0;
1368 error_out:
1369 return 1;
1370 }
1371
1372 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1373 {
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1376 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1377 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1378 enum nl80211_iftype opmode;
1379
1380 mac->link_state = MAC80211_NOLINK;
1381 opmode = NL80211_IFTYPE_UNSPECIFIED;
1382 _rtl92cu_set_media_status(hw, opmode);
1383 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1384 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1385 if (rtlusb->disableHWSM)
1386 _CardDisableHWSM(hw);
1387 else
1388 _CardDisableWithoutHWSM(hw);
1389 }
1390
1391 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1392 {
1393 struct rtl_priv *rtlpriv = rtl_priv(hw);
1394 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1395 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1396
1397 if (rtlpriv->psc.rfpwr_state != ERFON)
1398 return;
1399
1400 if (check_bssid) {
1401 u8 tmp;
1402 if (IS_NORMAL_CHIP(rtlhal->version)) {
1403 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1404 tmp = BIT(4);
1405 } else {
1406 reg_rcr |= RCR_CBSSID;
1407 tmp = BIT(4) | BIT(5);
1408 }
1409 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1410 (u8 *) (&reg_rcr));
1411 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1412 } else {
1413 u8 tmp;
1414 if (IS_NORMAL_CHIP(rtlhal->version)) {
1415 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1416 tmp = BIT(4);
1417 } else {
1418 reg_rcr &= ~RCR_CBSSID;
1419 tmp = BIT(4) | BIT(5);
1420 }
1421 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1422 rtlpriv->cfg->ops->set_hw_reg(hw,
1423 HW_VAR_RCR, (u8 *) (&reg_rcr));
1424 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1425 }
1426 }
1427
1428 /*========================================================================== */
1429
1430 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1431 {
1432 struct rtl_priv *rtlpriv = rtl_priv(hw);
1433
1434 if (_rtl92cu_set_media_status(hw, type))
1435 return -EOPNOTSUPP;
1436
1437 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1438 if (type != NL80211_IFTYPE_AP)
1439 rtl92cu_set_check_bssid(hw, true);
1440 } else {
1441 rtl92cu_set_check_bssid(hw, false);
1442 }
1443
1444 return 0;
1445 }
1446
1447 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1448 {
1449 struct rtl_priv *rtlpriv = rtl_priv(hw);
1450 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1451
1452 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1453
1454 /* TODO: Remove these magic number */
1455 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1456 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1457 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1458 /* Change beacon AIFS to the largest number
1459 * beacause test chip does not contension before sending beacon. */
1460 if (IS_NORMAL_CHIP(rtlhal->version))
1461 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1462 else
1463 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1464 }
1465
1466 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1467 bool Linked)
1468 {
1469 struct rtl_priv *rtlpriv = rtl_priv(hw);
1470
1471 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1472 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1473 }
1474
1475 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1476 {
1477
1478 struct rtl_priv *rtlpriv = rtl_priv(hw);
1479 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1480 u16 bcn_interval, atim_window;
1481 u32 value32;
1482
1483 bcn_interval = mac->beacon_interval;
1484 atim_window = 2; /*FIX MERGE */
1485 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1486 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1487 _InitBeaconParameters(hw);
1488 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1489 /*
1490 * Force beacon frame transmission even after receiving beacon frame
1491 * from other ad hoc STA
1492 *
1493 *
1494 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1495 */
1496 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1497 value32 &= ~TSFRST;
1498 rtl_write_dword(rtlpriv, REG_TCR, value32);
1499 value32 |= TSFRST;
1500 rtl_write_dword(rtlpriv, REG_TCR, value32);
1501 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1502 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1503 value32);
1504 /* TODO: Modify later (Find the right parameters)
1505 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1506 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1507 (mac->opmode == NL80211_IFTYPE_AP)) {
1508 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1509 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1510 }
1511 _beacon_function_enable(hw, true, true);
1512 }
1513
1514 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1515 {
1516 struct rtl_priv *rtlpriv = rtl_priv(hw);
1517 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1518 u16 bcn_interval = mac->beacon_interval;
1519
1520 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1521 bcn_interval);
1522 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1523 }
1524
1525 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1526 u32 add_msr, u32 rm_msr)
1527 {
1528 }
1529
1530 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1531 {
1532 struct rtl_priv *rtlpriv = rtl_priv(hw);
1533 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1534 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1535
1536 switch (variable) {
1537 case HW_VAR_RCR:
1538 *((u32 *)(val)) = mac->rx_conf;
1539 break;
1540 case HW_VAR_RF_STATE:
1541 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1542 break;
1543 case HW_VAR_FWLPS_RF_ON:{
1544 enum rf_pwrstate rfState;
1545 u32 val_rcr;
1546
1547 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1548 (u8 *)(&rfState));
1549 if (rfState == ERFOFF) {
1550 *((bool *) (val)) = true;
1551 } else {
1552 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1553 val_rcr &= 0x00070000;
1554 if (val_rcr)
1555 *((bool *) (val)) = false;
1556 else
1557 *((bool *) (val)) = true;
1558 }
1559 break;
1560 }
1561 case HW_VAR_FW_PSMODE_STATUS:
1562 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1563 break;
1564 case HW_VAR_CORRECT_TSF:{
1565 u64 tsf;
1566 u32 *ptsf_low = (u32 *)&tsf;
1567 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1568
1569 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1570 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1571 *((u64 *)(val)) = tsf;
1572 break;
1573 }
1574 case HW_VAR_MGT_FILTER:
1575 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1576 break;
1577 case HW_VAR_CTRL_FILTER:
1578 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1579 break;
1580 case HW_VAR_DATA_FILTER:
1581 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1582 break;
1583 default:
1584 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1585 "switch case not processed\n");
1586 break;
1587 }
1588 }
1589
1590 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1591 {
1592 struct rtl_priv *rtlpriv = rtl_priv(hw);
1593 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1594 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1595 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1596 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1597 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1598 enum wireless_mode wirelessmode = mac->mode;
1599 u8 idx = 0;
1600
1601 switch (variable) {
1602 case HW_VAR_ETHER_ADDR:{
1603 for (idx = 0; idx < ETH_ALEN; idx++) {
1604 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1605 val[idx]);
1606 }
1607 break;
1608 }
1609 case HW_VAR_BASIC_RATE:{
1610 u16 rate_cfg = ((u16 *) val)[0];
1611 u8 rate_index = 0;
1612
1613 rate_cfg &= 0x15f;
1614 /* TODO */
1615 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1616 * && ((rate_cfg & 0x150) == 0)) {
1617 * rate_cfg |= 0x010;
1618 * } */
1619 rate_cfg |= 0x01;
1620 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1621 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1622 (rate_cfg >> 8) & 0xff);
1623 while (rate_cfg > 0x1) {
1624 rate_cfg >>= 1;
1625 rate_index++;
1626 }
1627 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1628 rate_index);
1629 break;
1630 }
1631 case HW_VAR_BSSID:{
1632 for (idx = 0; idx < ETH_ALEN; idx++) {
1633 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1634 val[idx]);
1635 }
1636 break;
1637 }
1638 case HW_VAR_SIFS:{
1639 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1640 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1641 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1642 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1643 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1644 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1645 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1646 break;
1647 }
1648 case HW_VAR_SLOT_TIME:{
1649 u8 e_aci;
1650 u8 QOS_MODE = 1;
1651
1652 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1653 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1654 "HW_VAR_SLOT_TIME %x\n", val[0]);
1655 if (QOS_MODE) {
1656 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1657 rtlpriv->cfg->ops->set_hw_reg(hw,
1658 HW_VAR_AC_PARAM,
1659 &e_aci);
1660 } else {
1661 u8 sifstime = 0;
1662 u8 u1bAIFS;
1663
1664 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1665 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1666 IS_WIRELESS_MODE_N_5G(wirelessmode))
1667 sifstime = 16;
1668 else
1669 sifstime = 10;
1670 u1bAIFS = sifstime + (2 * val[0]);
1671 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1672 u1bAIFS);
1673 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1674 u1bAIFS);
1675 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1676 u1bAIFS);
1677 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1678 u1bAIFS);
1679 }
1680 break;
1681 }
1682 case HW_VAR_ACK_PREAMBLE:{
1683 u8 reg_tmp;
1684 u8 short_preamble = (bool)*val;
1685 reg_tmp = 0;
1686 if (short_preamble)
1687 reg_tmp |= 0x80;
1688 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1689 break;
1690 }
1691 case HW_VAR_AMPDU_MIN_SPACE:{
1692 u8 min_spacing_to_set;
1693 u8 sec_min_space;
1694
1695 min_spacing_to_set = *val;
1696 if (min_spacing_to_set <= 7) {
1697 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1698 case NO_ENCRYPTION:
1699 case AESCCMP_ENCRYPTION:
1700 sec_min_space = 0;
1701 break;
1702 case WEP40_ENCRYPTION:
1703 case WEP104_ENCRYPTION:
1704 case TKIP_ENCRYPTION:
1705 sec_min_space = 6;
1706 break;
1707 default:
1708 sec_min_space = 7;
1709 break;
1710 }
1711 if (min_spacing_to_set < sec_min_space)
1712 min_spacing_to_set = sec_min_space;
1713 mac->min_space_cfg = ((mac->min_space_cfg &
1714 0xf8) |
1715 min_spacing_to_set);
1716 *val = min_spacing_to_set;
1717 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1718 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1719 mac->min_space_cfg);
1720 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1721 mac->min_space_cfg);
1722 }
1723 break;
1724 }
1725 case HW_VAR_SHORTGI_DENSITY:{
1726 u8 density_to_set;
1727
1728 density_to_set = *val;
1729 density_to_set &= 0x1f;
1730 mac->min_space_cfg &= 0x07;
1731 mac->min_space_cfg |= (density_to_set << 3);
1732 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1733 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1734 mac->min_space_cfg);
1735 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1736 mac->min_space_cfg);
1737 break;
1738 }
1739 case HW_VAR_AMPDU_FACTOR:{
1740 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1741 u8 factor_toset;
1742 u8 *p_regtoset = NULL;
1743 u8 index = 0;
1744
1745 p_regtoset = regtoset_normal;
1746 factor_toset = *val;
1747 if (factor_toset <= 3) {
1748 factor_toset = (1 << (factor_toset + 2));
1749 if (factor_toset > 0xf)
1750 factor_toset = 0xf;
1751 for (index = 0; index < 4; index++) {
1752 if ((p_regtoset[index] & 0xf0) >
1753 (factor_toset << 4))
1754 p_regtoset[index] =
1755 (p_regtoset[index] & 0x0f)
1756 | (factor_toset << 4);
1757 if ((p_regtoset[index] & 0x0f) >
1758 factor_toset)
1759 p_regtoset[index] =
1760 (p_regtoset[index] & 0xf0)
1761 | (factor_toset);
1762 rtl_write_byte(rtlpriv,
1763 (REG_AGGLEN_LMT + index),
1764 p_regtoset[index]);
1765 }
1766 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1767 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1768 factor_toset);
1769 }
1770 break;
1771 }
1772 case HW_VAR_AC_PARAM:{
1773 u8 e_aci = *val;
1774 u32 u4b_ac_param;
1775 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1776 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1777 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1778
1779 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1780 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1781 AC_PARAM_ECW_MIN_OFFSET);
1782 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1783 AC_PARAM_ECW_MAX_OFFSET);
1784 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1785 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1786 "queue:%x, ac_param:%x\n",
1787 e_aci, u4b_ac_param);
1788 switch (e_aci) {
1789 case AC1_BK:
1790 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1791 u4b_ac_param);
1792 break;
1793 case AC0_BE:
1794 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1795 u4b_ac_param);
1796 break;
1797 case AC2_VI:
1798 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1799 u4b_ac_param);
1800 break;
1801 case AC3_VO:
1802 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1803 u4b_ac_param);
1804 break;
1805 default:
1806 RT_ASSERT(false,
1807 "SetHwReg8185(): invalid aci: %d !\n",
1808 e_aci);
1809 break;
1810 }
1811 if (rtlusb->acm_method != eAcmWay2_SW)
1812 rtlpriv->cfg->ops->set_hw_reg(hw,
1813 HW_VAR_ACM_CTRL, &e_aci);
1814 break;
1815 }
1816 case HW_VAR_ACM_CTRL:{
1817 u8 e_aci = *val;
1818 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
1819 (&(mac->ac[0].aifs));
1820 u8 acm = p_aci_aifsn->f.acm;
1821 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
1822
1823 acm_ctrl =
1824 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
1825 if (acm) {
1826 switch (e_aci) {
1827 case AC0_BE:
1828 acm_ctrl |= AcmHw_BeqEn;
1829 break;
1830 case AC2_VI:
1831 acm_ctrl |= AcmHw_ViqEn;
1832 break;
1833 case AC3_VO:
1834 acm_ctrl |= AcmHw_VoqEn;
1835 break;
1836 default:
1837 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1838 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
1839 acm);
1840 break;
1841 }
1842 } else {
1843 switch (e_aci) {
1844 case AC0_BE:
1845 acm_ctrl &= (~AcmHw_BeqEn);
1846 break;
1847 case AC2_VI:
1848 acm_ctrl &= (~AcmHw_ViqEn);
1849 break;
1850 case AC3_VO:
1851 acm_ctrl &= (~AcmHw_BeqEn);
1852 break;
1853 default:
1854 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1855 "switch case not processed\n");
1856 break;
1857 }
1858 }
1859 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
1860 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
1861 acm_ctrl);
1862 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
1863 break;
1864 }
1865 case HW_VAR_RCR:{
1866 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1867 mac->rx_conf = ((u32 *) (val))[0];
1868 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1869 "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1870 break;
1871 }
1872 case HW_VAR_RETRY_LIMIT:{
1873 u8 retry_limit = val[0];
1874
1875 rtl_write_word(rtlpriv, REG_RL,
1876 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1877 retry_limit << RETRY_LIMIT_LONG_SHIFT);
1878 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1879 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1880 retry_limit);
1881 break;
1882 }
1883 case HW_VAR_DUAL_TSF_RST:
1884 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1885 break;
1886 case HW_VAR_EFUSE_BYTES:
1887 rtlefuse->efuse_usedbytes = *((u16 *) val);
1888 break;
1889 case HW_VAR_EFUSE_USAGE:
1890 rtlefuse->efuse_usedpercentage = *val;
1891 break;
1892 case HW_VAR_IO_CMD:
1893 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1894 break;
1895 case HW_VAR_WPA_CONFIG:
1896 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1897 break;
1898 case HW_VAR_SET_RPWM:{
1899 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1900
1901 if (rpwm_val & BIT(7))
1902 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1903 else
1904 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1905 *val | BIT(7));
1906 break;
1907 }
1908 case HW_VAR_H2C_FW_PWRMODE:{
1909 u8 psmode = *val;
1910
1911 if ((psmode != FW_PS_ACTIVE_MODE) &&
1912 (!IS_92C_SERIAL(rtlhal->version)))
1913 rtl92c_dm_rf_saving(hw, true);
1914 rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1915 break;
1916 }
1917 case HW_VAR_FW_PSMODE_STATUS:
1918 ppsc->fw_current_inpsmode = *((bool *) val);
1919 break;
1920 case HW_VAR_H2C_FW_JOINBSSRPT:{
1921 u8 mstatus = *val;
1922 u8 tmp_reg422;
1923 bool recover = false;
1924
1925 if (mstatus == RT_MEDIA_CONNECT) {
1926 rtlpriv->cfg->ops->set_hw_reg(hw,
1927 HW_VAR_AID, NULL);
1928 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1929 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1930 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1931 tmp_reg422 = rtl_read_byte(rtlpriv,
1932 REG_FWHW_TXQ_CTRL + 2);
1933 if (tmp_reg422 & BIT(6))
1934 recover = true;
1935 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1936 tmp_reg422 & (~BIT(6)));
1937 rtl92c_set_fw_rsvdpagepkt(hw, 0);
1938 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1939 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1940 if (recover)
1941 rtl_write_byte(rtlpriv,
1942 REG_FWHW_TXQ_CTRL + 2,
1943 tmp_reg422 | BIT(6));
1944 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1945 }
1946 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1947 break;
1948 }
1949 case HW_VAR_AID:{
1950 u16 u2btmp;
1951
1952 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1953 u2btmp &= 0xC000;
1954 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1955 (u2btmp | mac->assoc_id));
1956 break;
1957 }
1958 case HW_VAR_CORRECT_TSF:{
1959 u8 btype_ibss = val[0];
1960
1961 if (btype_ibss)
1962 _rtl92cu_stop_tx_beacon(hw);
1963 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1964 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1965 0xffffffff));
1966 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1967 (u32)((mac->tsf >> 32) & 0xffffffff));
1968 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1969 if (btype_ibss)
1970 _rtl92cu_resume_tx_beacon(hw);
1971 break;
1972 }
1973 case HW_VAR_MGT_FILTER:
1974 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1975 break;
1976 case HW_VAR_CTRL_FILTER:
1977 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1978 break;
1979 case HW_VAR_DATA_FILTER:
1980 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1981 break;
1982 default:
1983 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1984 "switch case not processed\n");
1985 break;
1986 }
1987 }
1988
1989 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1990 struct ieee80211_sta *sta)
1991 {
1992 struct rtl_priv *rtlpriv = rtl_priv(hw);
1993 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1994 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1995 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1996 u32 ratr_value;
1997 u8 ratr_index = 0;
1998 u8 nmode = mac->ht_enable;
1999 u8 mimo_ps = IEEE80211_SMPS_OFF;
2000 u16 shortgi_rate;
2001 u32 tmp_ratr_value;
2002 u8 curtxbw_40mhz = mac->bw_40;
2003 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2004 1 : 0;
2005 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2006 1 : 0;
2007 enum wireless_mode wirelessmode = mac->mode;
2008
2009 if (rtlhal->current_bandtype == BAND_ON_5G)
2010 ratr_value = sta->supp_rates[1] << 4;
2011 else
2012 ratr_value = sta->supp_rates[0];
2013 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2014 ratr_value = 0xfff;
2015
2016 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2017 sta->ht_cap.mcs.rx_mask[0] << 12);
2018 switch (wirelessmode) {
2019 case WIRELESS_MODE_B:
2020 if (ratr_value & 0x0000000c)
2021 ratr_value &= 0x0000000d;
2022 else
2023 ratr_value &= 0x0000000f;
2024 break;
2025 case WIRELESS_MODE_G:
2026 ratr_value &= 0x00000FF5;
2027 break;
2028 case WIRELESS_MODE_N_24G:
2029 case WIRELESS_MODE_N_5G:
2030 nmode = 1;
2031 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2032 ratr_value &= 0x0007F005;
2033 } else {
2034 u32 ratr_mask;
2035
2036 if (get_rf_type(rtlphy) == RF_1T2R ||
2037 get_rf_type(rtlphy) == RF_1T1R)
2038 ratr_mask = 0x000ff005;
2039 else
2040 ratr_mask = 0x0f0ff005;
2041
2042 ratr_value &= ratr_mask;
2043 }
2044 break;
2045 default:
2046 if (rtlphy->rf_type == RF_1T2R)
2047 ratr_value &= 0x000ff0ff;
2048 else
2049 ratr_value &= 0x0f0ff0ff;
2050
2051 break;
2052 }
2053
2054 ratr_value &= 0x0FFFFFFF;
2055
2056 if (nmode && ((curtxbw_40mhz &&
2057 curshortgi_40mhz) || (!curtxbw_40mhz &&
2058 curshortgi_20mhz))) {
2059
2060 ratr_value |= 0x10000000;
2061 tmp_ratr_value = (ratr_value >> 12);
2062
2063 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2064 if ((1 << shortgi_rate) & tmp_ratr_value)
2065 break;
2066 }
2067
2068 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2069 (shortgi_rate << 4) | (shortgi_rate);
2070 }
2071
2072 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2073
2074 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2075 rtl_read_dword(rtlpriv, REG_ARFR0));
2076 }
2077
2078 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2079 struct ieee80211_sta *sta,
2080 u8 rssi_level)
2081 {
2082 struct rtl_priv *rtlpriv = rtl_priv(hw);
2083 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2084 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2085 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2086 struct rtl_sta_info *sta_entry = NULL;
2087 u32 ratr_bitmap;
2088 u8 ratr_index;
2089 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2090 u8 curshortgi_40mhz = curtxbw_40mhz &&
2091 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2092 1 : 0;
2093 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2094 1 : 0;
2095 enum wireless_mode wirelessmode = 0;
2096 bool shortgi = false;
2097 u8 rate_mask[5];
2098 u8 macid = 0;
2099 u8 mimo_ps = IEEE80211_SMPS_OFF;
2100
2101 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2102 wirelessmode = sta_entry->wireless_mode;
2103 if (mac->opmode == NL80211_IFTYPE_STATION ||
2104 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2105 curtxbw_40mhz = mac->bw_40;
2106 else if (mac->opmode == NL80211_IFTYPE_AP ||
2107 mac->opmode == NL80211_IFTYPE_ADHOC)
2108 macid = sta->aid + 1;
2109
2110 if (rtlhal->current_bandtype == BAND_ON_5G)
2111 ratr_bitmap = sta->supp_rates[1] << 4;
2112 else
2113 ratr_bitmap = sta->supp_rates[0];
2114 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2115 ratr_bitmap = 0xfff;
2116 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2117 sta->ht_cap.mcs.rx_mask[0] << 12);
2118 switch (wirelessmode) {
2119 case WIRELESS_MODE_B:
2120 ratr_index = RATR_INX_WIRELESS_B;
2121 if (ratr_bitmap & 0x0000000c)
2122 ratr_bitmap &= 0x0000000d;
2123 else
2124 ratr_bitmap &= 0x0000000f;
2125 break;
2126 case WIRELESS_MODE_G:
2127 ratr_index = RATR_INX_WIRELESS_GB;
2128
2129 if (rssi_level == 1)
2130 ratr_bitmap &= 0x00000f00;
2131 else if (rssi_level == 2)
2132 ratr_bitmap &= 0x00000ff0;
2133 else
2134 ratr_bitmap &= 0x00000ff5;
2135 break;
2136 case WIRELESS_MODE_A:
2137 ratr_index = RATR_INX_WIRELESS_A;
2138 ratr_bitmap &= 0x00000ff0;
2139 break;
2140 case WIRELESS_MODE_N_24G:
2141 case WIRELESS_MODE_N_5G:
2142 ratr_index = RATR_INX_WIRELESS_NGB;
2143
2144 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2145 if (rssi_level == 1)
2146 ratr_bitmap &= 0x00070000;
2147 else if (rssi_level == 2)
2148 ratr_bitmap &= 0x0007f000;
2149 else
2150 ratr_bitmap &= 0x0007f005;
2151 } else {
2152 if (rtlphy->rf_type == RF_1T2R ||
2153 rtlphy->rf_type == RF_1T1R) {
2154 if (curtxbw_40mhz) {
2155 if (rssi_level == 1)
2156 ratr_bitmap &= 0x000f0000;
2157 else if (rssi_level == 2)
2158 ratr_bitmap &= 0x000ff000;
2159 else
2160 ratr_bitmap &= 0x000ff015;
2161 } else {
2162 if (rssi_level == 1)
2163 ratr_bitmap &= 0x000f0000;
2164 else if (rssi_level == 2)
2165 ratr_bitmap &= 0x000ff000;
2166 else
2167 ratr_bitmap &= 0x000ff005;
2168 }
2169 } else {
2170 if (curtxbw_40mhz) {
2171 if (rssi_level == 1)
2172 ratr_bitmap &= 0x0f0f0000;
2173 else if (rssi_level == 2)
2174 ratr_bitmap &= 0x0f0ff000;
2175 else
2176 ratr_bitmap &= 0x0f0ff015;
2177 } else {
2178 if (rssi_level == 1)
2179 ratr_bitmap &= 0x0f0f0000;
2180 else if (rssi_level == 2)
2181 ratr_bitmap &= 0x0f0ff000;
2182 else
2183 ratr_bitmap &= 0x0f0ff005;
2184 }
2185 }
2186 }
2187
2188 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2189 (!curtxbw_40mhz && curshortgi_20mhz)) {
2190
2191 if (macid == 0)
2192 shortgi = true;
2193 else if (macid == 1)
2194 shortgi = false;
2195 }
2196 break;
2197 default:
2198 ratr_index = RATR_INX_WIRELESS_NGB;
2199
2200 if (rtlphy->rf_type == RF_1T2R)
2201 ratr_bitmap &= 0x000ff0ff;
2202 else
2203 ratr_bitmap &= 0x0f0ff0ff;
2204 break;
2205 }
2206 sta_entry->ratr_index = ratr_index;
2207
2208 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2209 "ratr_bitmap :%x\n", ratr_bitmap);
2210 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2211 (ratr_index << 28);
2212 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2213 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2214 "Rate_index:%x, ratr_val:%x, %5phC\n",
2215 ratr_index, ratr_bitmap, rate_mask);
2216 memcpy(rtlpriv->rate_mask, rate_mask, 5);
2217 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2218 * "scheduled while atomic" if called directly */
2219 schedule_work(&rtlpriv->works.fill_h2c_cmd);
2220
2221 if (macid != 0)
2222 sta_entry->ratr_index = ratr_index;
2223 }
2224
2225 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2226 struct ieee80211_sta *sta,
2227 u8 rssi_level)
2228 {
2229 struct rtl_priv *rtlpriv = rtl_priv(hw);
2230
2231 if (rtlpriv->dm.useramask)
2232 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2233 else
2234 rtl92cu_update_hal_rate_table(hw, sta);
2235 }
2236
2237 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2238 {
2239 struct rtl_priv *rtlpriv = rtl_priv(hw);
2240 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2241 u16 sifs_timer;
2242
2243 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2244 &mac->slot_time);
2245 if (!mac->ht_enable)
2246 sifs_timer = 0x0a0a;
2247 else
2248 sifs_timer = 0x0e0e;
2249 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2250 }
2251
2252 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2253 {
2254 struct rtl_priv *rtlpriv = rtl_priv(hw);
2255 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2256 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2257 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2258 u8 u1tmp = 0;
2259 bool actuallyset = false;
2260 unsigned long flag = 0;
2261 /* to do - usb autosuspend */
2262 u8 usb_autosuspend = 0;
2263
2264 if (ppsc->swrf_processing)
2265 return false;
2266 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2267 if (ppsc->rfchange_inprogress) {
2268 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2269 return false;
2270 } else {
2271 ppsc->rfchange_inprogress = true;
2272 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2273 }
2274 cur_rfstate = ppsc->rfpwr_state;
2275 if (usb_autosuspend) {
2276 /* to do................... */
2277 } else {
2278 if (ppsc->pwrdown_mode) {
2279 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2280 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2281 ERFOFF : ERFON;
2282 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2283 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2284 } else {
2285 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2286 rtl_read_byte(rtlpriv,
2287 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2288 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2289 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2290 ERFON : ERFOFF;
2291 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2292 "GPIO_IN=%02x\n", u1tmp);
2293 }
2294 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2295 e_rfpowerstate_toset);
2296 }
2297 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2298 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2299 "GPIOChangeRF - HW Radio ON, RF ON\n");
2300 ppsc->hwradiooff = false;
2301 actuallyset = true;
2302 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2303 ERFOFF)) {
2304 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2305 "GPIOChangeRF - HW Radio OFF\n");
2306 ppsc->hwradiooff = true;
2307 actuallyset = true;
2308 } else {
2309 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2310 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2311 ppsc->hwradiooff, e_rfpowerstate_toset);
2312 }
2313 if (actuallyset) {
2314 ppsc->hwradiooff = true;
2315 if (e_rfpowerstate_toset == ERFON) {
2316 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2317 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2318 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2319 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2320 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2321 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2322 }
2323 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2324 ppsc->rfchange_inprogress = false;
2325 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2326 /* For power down module, we need to enable register block
2327 * contrl reg at 0x1c. Then enable power down control bit
2328 * of register 0x04 BIT4 and BIT15 as 1.
2329 */
2330 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2331 /* Enable register area 0x0-0xc. */
2332 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2333 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2334 /*
2335 * We should configure HW PDn source for WiFi
2336 * ONLY, and then our HW will be set in
2337 * power-down mode if PDn source from all
2338 * functions are configured.
2339 */
2340 u1tmp = rtl_read_byte(rtlpriv,
2341 REG_MULTI_FUNC_CTRL);
2342 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2343 (u1tmp|WL_HWPDN_EN));
2344 } else {
2345 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2346 }
2347 }
2348 if (e_rfpowerstate_toset == ERFOFF) {
2349 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2350 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2351 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2352 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2353 }
2354 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2355 /* Enter D3 or ASPM after GPIO had been done. */
2356 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2357 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2358 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2359 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2360 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2361 ppsc->rfchange_inprogress = false;
2362 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2363 } else {
2364 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2365 ppsc->rfchange_inprogress = false;
2366 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2367 }
2368 *valid = 1;
2369 return !ppsc->hwradiooff;
2370 }
Linux with added FPC-III support