?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / rtl8723ae / hw.c
blob99f6bc5fa986b457c3c01f42b3dff83d2bbb105d
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "dm.h"
41 #include "fw.h"
42 #include "led.h"
43 #include "hw.h"
44 #include "pwrseqcmd.h"
45 #include "pwrseq.h"
46 #include "btc.h"
47
48 static void _rtl8723ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
49 u8 set_bits, u8 clear_bits)
50 {
51 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
52 struct rtl_priv *rtlpriv = rtl_priv(hw);
53
54 rtlpci->reg_bcn_ctrl_val |= set_bits;
55 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
56
57 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
58 }
59
60 static void _rtl8723ae_stop_tx_beacon(struct ieee80211_hw *hw)
61 {
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 u8 tmp1byte;
64
65 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
66 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
68 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
69 tmp1byte &= ~(BIT(0));
70 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
71 }
72
73 static void _rtl8723ae_resume_tx_beacon(struct ieee80211_hw *hw)
74 {
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
76 u8 tmp1byte;
77
78 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
79 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
81 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
82 tmp1byte |= BIT(1);
83 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
84 }
85
86 static void _rtl8723ae_enable_bcn_sufunc(struct ieee80211_hw *hw)
87 {
88 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
89 }
90
91 static void _rtl8723ae_disable_bcn_sufunc(struct ieee80211_hw *hw)
92 {
93 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
94 }
95
96 void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
97 {
98 struct rtl_priv *rtlpriv = rtl_priv(hw);
99 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
100 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
101
102 switch (variable) {
103 case HW_VAR_RCR:
104 *((u32 *) (val)) = rtlpci->receive_config;
105 break;
106 case HW_VAR_RF_STATE:
107 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
108 break;
109 case HW_VAR_FWLPS_RF_ON:{
110 enum rf_pwrstate rfState;
111 u32 val_rcr;
112
113 rtlpriv->cfg->ops->get_hw_reg(hw,
114 HW_VAR_RF_STATE,
115 (u8 *) (&rfState));
116 if (rfState == ERFOFF) {
117 *((bool *) (val)) = true;
118 } else {
119 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
120 val_rcr &= 0x00070000;
121 if (val_rcr)
122 *((bool *) (val)) = false;
123 else
124 *((bool *) (val)) = true;
125 }
126 break; }
127 case HW_VAR_FW_PSMODE_STATUS:
128 *((bool *) (val)) = ppsc->fw_current_inpsmode;
129 break;
130 case HW_VAR_CORRECT_TSF:{
131 u64 tsf;
132 u32 *ptsf_low = (u32 *)&tsf;
133 u32 *ptsf_high = ((u32 *)&tsf) + 1;
134
135 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
136 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
137
138 *((u64 *) (val)) = tsf;
139
140 break; }
141 default:
142 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
143 "switch case not process\n");
144 break;
145 }
146 }
147
148 void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
149 {
150 struct rtl_priv *rtlpriv = rtl_priv(hw);
151 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
152 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
153 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
154 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
155 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
156 u8 idx;
157
158 switch (variable) {
159 case HW_VAR_ETHER_ADDR:
160 for (idx = 0; idx < ETH_ALEN; idx++) {
161 rtl_write_byte(rtlpriv, (REG_MACID + idx),
162 val[idx]);
163 }
164 break;
165 case HW_VAR_BASIC_RATE:{
166 u16 rate_cfg = ((u16 *) val)[0];
167 u8 rate_index = 0;
168 rate_cfg = rate_cfg & 0x15f;
169 rate_cfg |= 0x01;
170 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
171 rtl_write_byte(rtlpriv, REG_RRSR + 1,
172 (rate_cfg >> 8) & 0xff);
173 while (rate_cfg > 0x1) {
174 rate_cfg = (rate_cfg >> 1);
175 rate_index++;
176 }
177 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
178 rate_index);
179 break; }
180 case HW_VAR_BSSID:
181 for (idx = 0; idx < ETH_ALEN; idx++) {
182 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
183 val[idx]);
184 }
185 break;
186 case HW_VAR_SIFS:
187 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
188 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
189
190 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
191 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
192
193 if (!mac->ht_enable)
194 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
195 0x0e0e);
196 else
197 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
198 *((u16 *) val));
199 break;
200 case HW_VAR_SLOT_TIME:{
201 u8 e_aci;
202
203 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
204 "HW_VAR_SLOT_TIME %x\n", val[0]);
205
206 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
207
208 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
209 rtlpriv->cfg->ops->set_hw_reg(hw,
210 HW_VAR_AC_PARAM,
211 (u8 *) (&e_aci));
212 }
213 break; }
214 case HW_VAR_ACK_PREAMBLE:{
215 u8 reg_tmp;
216 u8 short_preamble = (bool) (*(u8 *) val);
217 reg_tmp = (mac->cur_40_prime_sc) << 5;
218 if (short_preamble)
219 reg_tmp |= 0x80;
220
221 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
222 break; }
223 case HW_VAR_AMPDU_MIN_SPACE:{
224 u8 min_spacing_to_set;
225 u8 sec_min_space;
226
227 min_spacing_to_set = *((u8 *) val);
228 if (min_spacing_to_set <= 7) {
229 sec_min_space = 0;
230
231 if (min_spacing_to_set < sec_min_space)
232 min_spacing_to_set = sec_min_space;
233
234 mac->min_space_cfg = ((mac->min_space_cfg &
235 0xf8) |
236 min_spacing_to_set);
237
238 *val = min_spacing_to_set;
239
240 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
241 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
242 mac->min_space_cfg);
243
244 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
245 mac->min_space_cfg);
246 }
247 break; }
248 case HW_VAR_SHORTGI_DENSITY:{
249 u8 density_to_set;
250
251 density_to_set = *((u8 *) val);
252 mac->min_space_cfg |= (density_to_set << 3);
253
254 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
255 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
256 mac->min_space_cfg);
257
258 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
259 mac->min_space_cfg);
260
261 break; }
262 case HW_VAR_AMPDU_FACTOR:{
263 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
264 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
265 u8 factor_toset;
266 u8 *p_regtoset = NULL;
267 u8 index;
268
269 if ((pcipriv->bt_coexist.bt_coexistence) &&
270 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
271 p_regtoset = regtoset_bt;
272 else
273 p_regtoset = regtoset_normal;
274
275 factor_toset = *((u8 *) val);
276 if (factor_toset <= 3) {
277 factor_toset = (1 << (factor_toset + 2));
278 if (factor_toset > 0xf)
279 factor_toset = 0xf;
280
281 for (index = 0; index < 4; index++) {
282 if ((p_regtoset[index] & 0xf0) >
283 (factor_toset << 4))
284 p_regtoset[index] =
285 (p_regtoset[index] & 0x0f) |
286 (factor_toset << 4);
287
288 if ((p_regtoset[index] & 0x0f) >
289 factor_toset)
290 p_regtoset[index] =
291 (p_regtoset[index] & 0xf0) |
292 (factor_toset);
293
294 rtl_write_byte(rtlpriv,
295 (REG_AGGLEN_LMT + index),
296 p_regtoset[index]);
297
298 }
299
300 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
301 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
302 factor_toset);
303 }
304 break; }
305 case HW_VAR_AC_PARAM:{
306 u8 e_aci = *((u8 *) val);
307 rtl8723ae_dm_init_edca_turbo(hw);
308
309 if (rtlpci->acm_method != eAcmWay2_SW)
310 rtlpriv->cfg->ops->set_hw_reg(hw,
311 HW_VAR_ACM_CTRL,
312 (u8 *) (&e_aci));
313 break; }
314 case HW_VAR_ACM_CTRL:{
315 u8 e_aci = *((u8 *) val);
316 union aci_aifsn *p_aci_aifsn =
317 (union aci_aifsn *)(&(mac->ac[0].aifs));
318 u8 acm = p_aci_aifsn->f.acm;
319 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
320
321 acm_ctrl |= ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
322
323 if (acm) {
324 switch (e_aci) {
325 case AC0_BE:
326 acm_ctrl |= AcmHw_BeqEn;
327 break;
328 case AC2_VI:
329 acm_ctrl |= AcmHw_ViqEn;
330 break;
331 case AC3_VO:
332 acm_ctrl |= AcmHw_VoqEn;
333 break;
334 default:
335 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
336 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
337 acm);
338 break;
339 }
340 } else {
341 switch (e_aci) {
342 case AC0_BE:
343 acm_ctrl &= (~AcmHw_BeqEn);
344 break;
345 case AC2_VI:
346 acm_ctrl &= (~AcmHw_ViqEn);
347 break;
348 case AC3_VO:
349 acm_ctrl &= (~AcmHw_BeqEn);
350 break;
351 default:
352 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
353 "switch case not processed\n");
354 break;
355 }
356 }
357
358 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
359 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
360 acm_ctrl);
361 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
362 break; }
363 case HW_VAR_RCR:
364 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
365 rtlpci->receive_config = ((u32 *) (val))[0];
366 break;
367 case HW_VAR_RETRY_LIMIT:{
368 u8 retry_limit = ((u8 *) (val))[0];
369
370 rtl_write_word(rtlpriv, REG_RL,
371 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
372 retry_limit << RETRY_LIMIT_LONG_SHIFT);
373 break; }
374 case HW_VAR_DUAL_TSF_RST:
375 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
376 break;
377 case HW_VAR_EFUSE_BYTES:
378 rtlefuse->efuse_usedbytes = *((u16 *) val);
379 break;
380 case HW_VAR_EFUSE_USAGE:
381 rtlefuse->efuse_usedpercentage = *((u8 *) val);
382 break;
383 case HW_VAR_IO_CMD:
384 rtl8723ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
385 break;
386 case HW_VAR_WPA_CONFIG:
387 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
388 break;
389 case HW_VAR_SET_RPWM:{
390 u8 rpwm_val;
391
392 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
393 udelay(1);
394
395 if (rpwm_val & BIT(7)) {
396 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
397 (*(u8 *) val));
398 } else {
399 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
400 ((*(u8 *) val) | BIT(7)));
401 }
402
403 break; }
404 case HW_VAR_H2C_FW_PWRMODE:{
405 u8 psmode = (*(u8 *) val);
406
407 if (psmode != FW_PS_ACTIVE_MODE)
408 rtl8723ae_dm_rf_saving(hw, true);
409
410 rtl8723ae_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
411 break; }
412 case HW_VAR_FW_PSMODE_STATUS:
413 ppsc->fw_current_inpsmode = *((bool *) val);
414 break;
415 case HW_VAR_H2C_FW_JOINBSSRPT:{
416 u8 mstatus = (*(u8 *) val);
417 u8 tmp_regcr, tmp_reg422;
418 bool recover = false;
419
420 if (mstatus == RT_MEDIA_CONNECT) {
421 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
422
423 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
424 rtl_write_byte(rtlpriv, REG_CR + 1,
425 (tmp_regcr | BIT(0)));
426
427 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
428 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
429
430 tmp_reg422 = rtl_read_byte(rtlpriv,
431 REG_FWHW_TXQ_CTRL + 2);
432 if (tmp_reg422 & BIT(6))
433 recover = true;
434 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
435 tmp_reg422 & (~BIT(6)));
436
437 rtl8723ae_set_fw_rsvdpagepkt(hw, 0);
438
439 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
440 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
441
442 if (recover)
443 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
444 tmp_reg422);
445
446 rtl_write_byte(rtlpriv, REG_CR + 1,
447 (tmp_regcr & ~(BIT(0))));
448 }
449 rtl8723ae_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
450
451 break; }
452 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
453 rtl8723ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
454 break;
455 case HW_VAR_AID:{
456 u16 u2btmp;
457 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
458 u2btmp &= 0xC000;
459 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
460 mac->assoc_id));
461 break; }
462 case HW_VAR_CORRECT_TSF:{
463 u8 btype_ibss = ((u8 *) (val))[0];
464
465 if (btype_ibss == true)
466 _rtl8723ae_stop_tx_beacon(hw);
467
468 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
469
470 rtl_write_dword(rtlpriv, REG_TSFTR,
471 (u32) (mac->tsf & 0xffffffff));
472 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
473 (u32) ((mac->tsf >> 32) & 0xffffffff));
474
475 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
476
477 if (btype_ibss == true)
478 _rtl8723ae_resume_tx_beacon(hw);
479 break; }
480 case HW_VAR_FW_LPS_ACTION: {
481 bool enter_fwlps = *((bool *)val);
482 u8 rpwm_val, fw_pwrmode;
483 bool fw_current_inps;
484
485 if (enter_fwlps) {
486 rpwm_val = 0x02; /* RF off */
487 fw_current_inps = true;
488 rtlpriv->cfg->ops->set_hw_reg(hw,
489 HW_VAR_FW_PSMODE_STATUS,
490 (u8 *)(&fw_current_inps));
491 rtlpriv->cfg->ops->set_hw_reg(hw,
492 HW_VAR_H2C_FW_PWRMODE,
493 (u8 *)(&ppsc->fwctrl_psmode));
494
495 rtlpriv->cfg->ops->set_hw_reg(hw,
496 HW_VAR_SET_RPWM,
497 (u8 *)(&rpwm_val));
498 } else {
499 rpwm_val = 0x0C; /* RF on */
500 fw_pwrmode = FW_PS_ACTIVE_MODE;
501 fw_current_inps = false;
502 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
503 (u8 *)(&rpwm_val));
504 rtlpriv->cfg->ops->set_hw_reg(hw,
505 HW_VAR_H2C_FW_PWRMODE,
506 (u8 *)(&fw_pwrmode));
507
508 rtlpriv->cfg->ops->set_hw_reg(hw,
509 HW_VAR_FW_PSMODE_STATUS,
510 (u8 *)(&fw_current_inps));
511 }
512 break; }
513 default:
514 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
515 "switch case not processed\n");
516 break;
517 }
518 }
519
520 static bool _rtl8723ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
521 {
522 struct rtl_priv *rtlpriv = rtl_priv(hw);
523 bool status = true;
524 long count = 0;
525 u32 value = _LLT_INIT_ADDR(address) |
526 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
527
528 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
529
530 do {
531 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
532 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
533 break;
534
535 if (count > POLLING_LLT_THRESHOLD) {
536 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
537 "Failed to polling write LLT done at address %d!\n",
538 address);
539 status = false;
540 break;
541 }
542 } while (++count);
543
544 return status;
545 }
546
547 static bool _rtl8723ae_llt_table_init(struct ieee80211_hw *hw)
548 {
549 struct rtl_priv *rtlpriv = rtl_priv(hw);
550 unsigned short i;
551 u8 txpktbuf_bndy;
552 u8 maxPage;
553 bool status;
554 u8 ubyte;
555
556 maxPage = 255;
557 txpktbuf_bndy = 246;
558
559 rtl_write_byte(rtlpriv, REG_CR, 0x8B);
560
561 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
562
563 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
564 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
565
566 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
567 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
568
569 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
570 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
571
572 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
573 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
574 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
575
576 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
577 status = _rtl8723ae_llt_write(hw, i, i + 1);
578 if (true != status)
579 return status;
580 }
581
582 status = _rtl8723ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
583 if (true != status)
584 return status;
585
586 for (i = txpktbuf_bndy; i < maxPage; i++) {
587 status = _rtl8723ae_llt_write(hw, i, (i + 1));
588 if (true != status)
589 return status;
590 }
591
592 status = _rtl8723ae_llt_write(hw, maxPage, txpktbuf_bndy);
593 if (true != status)
594 return status;
595
596 rtl_write_byte(rtlpriv, REG_CR, 0xff);
597 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
598 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
599
600 return true;
601 }
602
603 static void _rtl8723ae_gen_refresh_led_state(struct ieee80211_hw *hw)
604 {
605 struct rtl_priv *rtlpriv = rtl_priv(hw);
606 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
607 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
608 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
609
610 if (rtlpriv->rtlhal.up_first_time)
611 return;
612
613 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
614 rtl8723ae_sw_led_on(hw, pLed0);
615 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
616 rtl8723ae_sw_led_on(hw, pLed0);
617 else
618 rtl8723ae_sw_led_off(hw, pLed0);
619 }
620
621 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
622 {
623 struct rtl_priv *rtlpriv = rtl_priv(hw);
624 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
625 unsigned char bytetmp;
626 unsigned short wordtmp;
627 u16 retry = 0;
628 u16 tmpu2b;
629 bool mac_func_enable;
630
631 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
632 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
633 if (bytetmp == 0xFF)
634 mac_func_enable = true;
635 else
636 mac_func_enable = false;
637
638
639 /* HW Power on sequence */
640 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
641 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW))
642 return false;
643
644 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
645 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
646
647 /* eMAC time out function enable, 0x369[7]=1 */
648 bytetmp = rtl_read_byte(rtlpriv, 0x369);
649 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
650
651 /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
652 * we should do this before Enabling ASPM backdoor.
653 */
654 do {
655 rtl_write_word(rtlpriv, 0x358, 0x5e);
656 udelay(100);
657 rtl_write_word(rtlpriv, 0x356, 0xc280);
658 rtl_write_word(rtlpriv, 0x354, 0xc290);
659 rtl_write_word(rtlpriv, 0x358, 0x3e);
660 udelay(100);
661 rtl_write_word(rtlpriv, 0x358, 0x5e);
662 udelay(100);
663 tmpu2b = rtl_read_word(rtlpriv, 0x356);
664 retry++;
665 } while (tmpu2b != 0xc290 && retry < 100);
666
667 if (retry >= 100) {
668 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
669 "InitMAC(): ePHY configure fail!!!\n");
670 return false;
671 }
672
673 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
674 rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
675
676 if (!mac_func_enable) {
677 if (_rtl8723ae_llt_table_init(hw) == false)
678 return false;
679 }
680
681 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
682 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
683
684 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
685
686 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0xf;
687 wordtmp |= 0xF771;
688 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
689
690 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
691 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
692 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
693 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
694
695 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
696
697 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
698 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
699 DMA_BIT_MASK(32));
700 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
701 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
702 DMA_BIT_MASK(32));
703 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
704 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
705 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
706 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
707 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
708 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
709 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
710 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
711 rtl_write_dword(rtlpriv, REG_HQ_DESA,
712 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
713 DMA_BIT_MASK(32));
714 rtl_write_dword(rtlpriv, REG_RX_DESA,
715 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
716 DMA_BIT_MASK(32));
717
718 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
719
720 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
721
722 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
723 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
724 do {
725 retry++;
726 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
727 } while ((retry < 200) && (bytetmp & BIT(7)));
728
729 _rtl8723ae_gen_refresh_led_state(hw);
730
731 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
732
733 return true;
734 }
735
736 static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw)
737 {
738 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
739 struct rtl_priv *rtlpriv = rtl_priv(hw);
740 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
741 u8 reg_bw_opmode;
742 u32 reg_prsr;
743
744 reg_bw_opmode = BW_OPMODE_20MHZ;
745 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
746
747 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
748
749 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
750
751 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
752
753 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
754
755 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
756
757 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
758
759 rtl_write_word(rtlpriv, REG_RL, 0x0707);
760
761 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
762
763 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
764
765 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
766 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
767 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
768 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
769
770 if ((pcipriv->bt_coexist.bt_coexistence) &&
771 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
772 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
773 else
774 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
775
776 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
777
778 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
779
780 rtlpci->reg_bcn_ctrl_val = 0x1f;
781 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
782
783 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
784
785 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
786
787 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
788 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
789
790 if ((pcipriv->bt_coexist.bt_coexistence) &&
791 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
792 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
793 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
794 } else {
795 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
796 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
797 }
798
799 if ((pcipriv->bt_coexist.bt_coexistence) &&
800 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
801 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
802 else
803 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
804
805 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
806
807 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
808 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
809
810 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
811
812 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
813
814 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
815 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
816
817 rtl_write_dword(rtlpriv, 0x394, 0x1);
818 }
819
820 static void _rtl8723ae_enable_aspm_back_door(struct ieee80211_hw *hw)
821 {
822 struct rtl_priv *rtlpriv = rtl_priv(hw);
823 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
824
825 rtl_write_byte(rtlpriv, 0x34b, 0x93);
826 rtl_write_word(rtlpriv, 0x350, 0x870c);
827 rtl_write_byte(rtlpriv, 0x352, 0x1);
828
829 if (ppsc->support_backdoor)
830 rtl_write_byte(rtlpriv, 0x349, 0x1b);
831 else
832 rtl_write_byte(rtlpriv, 0x349, 0x03);
833
834 rtl_write_word(rtlpriv, 0x350, 0x2718);
835 rtl_write_byte(rtlpriv, 0x352, 0x1);
836 }
837
838 void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw)
839 {
840 struct rtl_priv *rtlpriv = rtl_priv(hw);
841 u8 sec_reg_value;
842
843 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
844 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
845 rtlpriv->sec.pairwise_enc_algorithm,
846 rtlpriv->sec.group_enc_algorithm);
847
848 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
849 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
850 "not open hw encryption\n");
851 return;
852 }
853
854 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
855
856 if (rtlpriv->sec.use_defaultkey) {
857 sec_reg_value |= SCR_TxUseDK;
858 sec_reg_value |= SCR_RxUseDK;
859 }
860
861 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
862
863 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
864
865 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
866 "The SECR-value %x\n", sec_reg_value);
867
868 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
869
870 }
871
872 int rtl8723ae_hw_init(struct ieee80211_hw *hw)
873 {
874 struct rtl_priv *rtlpriv = rtl_priv(hw);
875 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
876 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
877 struct rtl_phy *rtlphy = &(rtlpriv->phy);
878 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
879 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
880 bool rtstatus = true;
881 int err;
882 u8 tmp_u1b;
883 unsigned long flags;
884
885 rtlpriv->rtlhal.being_init_adapter = true;
886 /* As this function can take a very long time (up to 350 ms)
887 * and can be called with irqs disabled, reenable the irqs
888 * to let the other devices continue being serviced.
889 *
890 * It is safe doing so since our own interrupts will only be enabled
891 * in a subsequent step.
892 */
893 local_save_flags(flags);
894 local_irq_enable();
895
896 rtlpriv->intf_ops->disable_aspm(hw);
897 rtstatus = _rtl8712e_init_mac(hw);
898 if (rtstatus != true) {
899 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
900 err = 1;
901 goto exit;
902 }
903
904 err = rtl8723ae_download_fw(hw);
905 if (err) {
906 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
907 "Failed to download FW. Init HW without FW now..\n");
908 err = 1;
909 goto exit;
910 } else {
911 rtlhal->fw_ready = true;
912 }
913
914 rtlhal->last_hmeboxnum = 0;
915 rtl8723ae_phy_mac_config(hw);
916 /* because the last function modifies RCR, we update
917 * rcr var here, or TP will be unstable as ther receive_config
918 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
919 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
920 */
921 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
922 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
923 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
924
925 rtl8723ae_phy_bb_config(hw);
926 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
927 rtl8723ae_phy_rf_config(hw);
928 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
929 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
930 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
931 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
932 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
933 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
934 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
935 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
936 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
937 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
938 }
939 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
940 RF_CHNLBW, RFREG_OFFSET_MASK);
941 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
942 RF_CHNLBW, RFREG_OFFSET_MASK);
943 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
944 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
945 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
946 _rtl8723ae_hw_configure(hw);
947 rtl_cam_reset_all_entry(hw);
948 rtl8723ae_enable_hw_security_config(hw);
949
950 ppsc->rfpwr_state = ERFON;
951
952 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
953 _rtl8723ae_enable_aspm_back_door(hw);
954 rtlpriv->intf_ops->enable_aspm(hw);
955
956 rtl8723ae_bt_hw_init(hw);
957
958 if (ppsc->rfpwr_state == ERFON) {
959 rtl8723ae_phy_set_rfpath_switch(hw, 1);
960 if (rtlphy->iqk_initialized) {
961 rtl8723ae_phy_iq_calibrate(hw, true);
962 } else {
963 rtl8723ae_phy_iq_calibrate(hw, false);
964 rtlphy->iqk_initialized = true;
965 }
966
967 rtl8723ae_phy_lc_calibrate(hw);
968 }
969
970 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
971 if (!(tmp_u1b & BIT(0))) {
972 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
973 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
974 }
975
976 if (!(tmp_u1b & BIT(4))) {
977 tmp_u1b = rtl_read_byte(rtlpriv, 0x16) & 0x0F;
978 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
979 udelay(10);
980 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
981 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
982 }
983 rtl8723ae_dm_init(hw);
984 exit:
985 local_irq_restore(flags);
986 rtlpriv->rtlhal.being_init_adapter = false;
987 return err;
988 }
989
990 static enum version_8723e _rtl8723ae_read_chip_version(struct ieee80211_hw *hw)
991 {
992 struct rtl_priv *rtlpriv = rtl_priv(hw);
993 struct rtl_phy *rtlphy = &(rtlpriv->phy);
994 enum version_8723e version = 0x0000;
995 u32 value32;
996
997 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
998 if (value32 & TRP_VAUX_EN) {
999 version = (enum version_8723e)(version |
1000 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1001 /* RTL8723 with BT function. */
1002 version = (enum version_8723e)(version |
1003 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1004
1005 } else {
1006 /* Normal mass production chip. */
1007 version = (enum version_8723e) NORMAL_CHIP;
1008 version = (enum version_8723e)(version |
1009 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1010 /* RTL8723 with BT function. */
1011 version = (enum version_8723e)(version |
1012 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1013 if (IS_CHIP_VENDOR_UMC(version))
1014 version = (enum version_8723e)(version |
1015 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
1016 if (IS_8723_SERIES(version)) {
1017 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
1018 /* ROM code version */
1019 version = (enum version_8723e)(version |
1020 ((value32 & RF_RL_ID)>>20));
1021 }
1022 }
1023
1024 if (IS_8723_SERIES(version)) {
1025 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1026 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
1027 RT_POLARITY_HIGH_ACT :
1028 RT_POLARITY_LOW_ACT);
1029 }
1030 switch (version) {
1031 case VERSION_TEST_UMC_CHIP_8723:
1032 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1033 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1034 break;
1035 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
1036 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1037 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
1038 break;
1039 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
1040 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1041 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
1042 break;
1043 default:
1044 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1045 "Chip Version ID: Unknown. Bug?\n");
1046 break;
1047 }
1048
1049 if (IS_8723_SERIES(version))
1050 rtlphy->rf_type = RF_1T1R;
1051
1052 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1053 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1054
1055 return version;
1056 }
1057
1058 static int _rtl8723ae_set_media_status(struct ieee80211_hw *hw,
1059 enum nl80211_iftype type)
1060 {
1061 struct rtl_priv *rtlpriv = rtl_priv(hw);
1062 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1063 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1064
1065 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1066 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1067 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1068
1069 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1070 type == NL80211_IFTYPE_STATION) {
1071 _rtl8723ae_stop_tx_beacon(hw);
1072 _rtl8723ae_enable_bcn_sufunc(hw);
1073 } else if (type == NL80211_IFTYPE_ADHOC ||
1074 type == NL80211_IFTYPE_AP) {
1075 _rtl8723ae_resume_tx_beacon(hw);
1076 _rtl8723ae_disable_bcn_sufunc(hw);
1077 } else {
1078 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1079 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1080 type);
1081 }
1082
1083 switch (type) {
1084 case NL80211_IFTYPE_UNSPECIFIED:
1085 bt_msr |= MSR_NOLINK;
1086 ledaction = LED_CTL_LINK;
1087 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1088 "Set Network type to NO LINK!\n");
1089 break;
1090 case NL80211_IFTYPE_ADHOC:
1091 bt_msr |= MSR_ADHOC;
1092 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1093 "Set Network type to Ad Hoc!\n");
1094 break;
1095 case NL80211_IFTYPE_STATION:
1096 bt_msr |= MSR_INFRA;
1097 ledaction = LED_CTL_LINK;
1098 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1099 "Set Network type to STA!\n");
1100 break;
1101 case NL80211_IFTYPE_AP:
1102 bt_msr |= MSR_AP;
1103 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1104 "Set Network type to AP!\n");
1105 break;
1106 default:
1107 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1108 "Network type %d not supported!\n",
1109 type);
1110 return 1;
1111 break;
1112
1113 }
1114
1115 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1116 rtlpriv->cfg->ops->led_control(hw, ledaction);
1117 if ((bt_msr & 0x03) == MSR_AP)
1118 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1119 else
1120 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1121 return 0;
1122 }
1123
1124 void rtl8723ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1125 {
1126 struct rtl_priv *rtlpriv = rtl_priv(hw);
1127 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1128 u32 reg_rcr = rtlpci->receive_config;
1129
1130 if (rtlpriv->psc.rfpwr_state != ERFON)
1131 return;
1132
1133 if (check_bssid == true) {
1134 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1135 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1136 (u8 *)(&reg_rcr));
1137 _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
1138 } else if (check_bssid == false) {
1139 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1140 _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
1141 rtlpriv->cfg->ops->set_hw_reg(hw,
1142 HW_VAR_RCR, (u8 *) (&reg_rcr));
1143 }
1144 }
1145
1146 int rtl8723ae_set_network_type(struct ieee80211_hw *hw,
1147 enum nl80211_iftype type)
1148 {
1149 struct rtl_priv *rtlpriv = rtl_priv(hw);
1150
1151 if (_rtl8723ae_set_media_status(hw, type))
1152 return -EOPNOTSUPP;
1153
1154 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1155 if (type != NL80211_IFTYPE_AP)
1156 rtl8723ae_set_check_bssid(hw, true);
1157 } else {
1158 rtl8723ae_set_check_bssid(hw, false);
1159 }
1160 return 0;
1161 }
1162
1163 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1164 void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci)
1165 {
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167
1168 rtl8723ae_dm_init_edca_turbo(hw);
1169 switch (aci) {
1170 case AC1_BK:
1171 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1172 break;
1173 case AC0_BE:
1174 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4ac_param); */
1175 break;
1176 case AC2_VI:
1177 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1178 break;
1179 case AC3_VO:
1180 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1181 break;
1182 default:
1183 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1184 break;
1185 }
1186 }
1187
1188 void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw)
1189 {
1190 struct rtl_priv *rtlpriv = rtl_priv(hw);
1191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1192
1193 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1194 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1195 rtlpci->irq_enabled = true;
1196 }
1197
1198 void rtl8723ae_disable_interrupt(struct ieee80211_hw *hw)
1199 {
1200 struct rtl_priv *rtlpriv = rtl_priv(hw);
1201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1202
1203 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1204 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1205 rtlpci->irq_enabled = false;
1206 synchronize_irq(rtlpci->pdev->irq);
1207 }
1208
1209 static void _rtl8723ae_poweroff_adapter(struct ieee80211_hw *hw)
1210 {
1211 struct rtl_priv *rtlpriv = rtl_priv(hw);
1212 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1213 u8 u1tmp;
1214
1215 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1216 /* 1. Run LPS WL RFOFF flow */
1217 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1218 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW);
1219
1220 /* 2. 0x1F[7:0] = 0 */
1221 /* turn off RF */
1222 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1223 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1224 rtl8723ae_firmware_selfreset(hw);
1225
1226 /* Reset MCU. Suggested by Filen. */
1227 u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1228 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1tmp & (~BIT(2))));
1229
1230 /* g. MCUFWDL 0x80[1:0]=0 */
1231 /* reset MCU ready status */
1232 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1233
1234 /* HW card disable configuration. */
1235 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1236 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW);
1237
1238 /* Reset MCU IO Wrapper */
1239 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1240 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1tmp & (~BIT(0))));
1241 u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1242 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1tmp | BIT(0));
1243
1244 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1245 /* lock ISO/CLK/Power control register */
1246 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1247 }
1248
1249 void rtl8723ae_card_disable(struct ieee80211_hw *hw)
1250 {
1251 struct rtl_priv *rtlpriv = rtl_priv(hw);
1252 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1253 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1254 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1255 enum nl80211_iftype opmode;
1256
1257 mac->link_state = MAC80211_NOLINK;
1258 opmode = NL80211_IFTYPE_UNSPECIFIED;
1259 _rtl8723ae_set_media_status(hw, opmode);
1260 if (rtlpci->driver_is_goingto_unload ||
1261 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1262 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1263 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1264 _rtl8723ae_poweroff_adapter(hw);
1265
1266 /* after power off we should do iqk again */
1267 rtlpriv->phy.iqk_initialized = false;
1268 }
1269
1270 void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw,
1271 u32 *p_inta, u32 *p_intb)
1272 {
1273 struct rtl_priv *rtlpriv = rtl_priv(hw);
1274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1275
1276 *p_inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1277 rtl_write_dword(rtlpriv, 0x3a0, *p_inta);
1278 }
1279
1280 void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw)
1281 {
1282
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1285 u16 bcn_interval, atim_window;
1286
1287 bcn_interval = mac->beacon_interval;
1288 atim_window = 2; /*FIX MERGE */
1289 rtl8723ae_disable_interrupt(hw);
1290 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1291 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1292 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1293 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1294 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1295 rtl_write_byte(rtlpriv, 0x606, 0x30);
1296 rtl8723ae_enable_interrupt(hw);
1297 }
1298
1299 void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw)
1300 {
1301 struct rtl_priv *rtlpriv = rtl_priv(hw);
1302 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1303 u16 bcn_interval = mac->beacon_interval;
1304
1305 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1306 "beacon_interval:%d\n", bcn_interval);
1307 rtl8723ae_disable_interrupt(hw);
1308 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1309 rtl8723ae_enable_interrupt(hw);
1310 }
1311
1312 void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw,
1313 u32 add_msr, u32 rm_msr)
1314 {
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1317
1318 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1319 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1320
1321 if (add_msr)
1322 rtlpci->irq_mask[0] |= add_msr;
1323 if (rm_msr)
1324 rtlpci->irq_mask[0] &= (~rm_msr);
1325 rtl8723ae_disable_interrupt(hw);
1326 rtl8723ae_enable_interrupt(hw);
1327 }
1328
1329 static u8 _rtl8723ae_get_chnl_group(u8 chnl)
1330 {
1331 u8 group;
1332
1333 if (chnl < 3)
1334 group = 0;
1335 else if (chnl < 9)
1336 group = 1;
1337 else
1338 group = 2;
1339 return group;
1340 }
1341
1342 static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1343 bool autoload_fail,
1344 u8 *hwinfo)
1345 {
1346 struct rtl_priv *rtlpriv = rtl_priv(hw);
1347 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1348 u8 rf_path, index, tempval;
1349 u16 i;
1350
1351 for (rf_path = 0; rf_path < 1; rf_path++) {
1352 for (i = 0; i < 3; i++) {
1353 if (!autoload_fail) {
1354 rtlefuse->eeprom_chnlarea_txpwr_cck
1355 [rf_path][i] =
1356 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1357 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1358 [rf_path][i] =
1359 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path *
1360 3 + i];
1361 } else {
1362 rtlefuse->eeprom_chnlarea_txpwr_cck
1363 [rf_path][i] =
1364 EEPROM_DEFAULT_TXPOWERLEVEL;
1365 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1366 [rf_path][i] =
1367 EEPROM_DEFAULT_TXPOWERLEVEL;
1368 }
1369 }
1370 }
1371
1372 for (i = 0; i < 3; i++) {
1373 if (!autoload_fail)
1374 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1375 else
1376 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1377 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1378 (tempval & 0xf);
1379 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1380 ((tempval & 0xf0) >> 4);
1381 }
1382
1383 for (rf_path = 0; rf_path < 2; rf_path++)
1384 for (i = 0; i < 3; i++)
1385 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1386 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1387 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1388 [rf_path][i]);
1389 for (rf_path = 0; rf_path < 2; rf_path++)
1390 for (i = 0; i < 3; i++)
1391 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1392 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1393 rf_path, i,
1394 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1395 [rf_path][i]);
1396 for (rf_path = 0; rf_path < 2; rf_path++)
1397 for (i = 0; i < 3; i++)
1398 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1399 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1400 rf_path, i,
1401 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1402 [rf_path][i]);
1403
1404 for (rf_path = 0; rf_path < 2; rf_path++) {
1405 for (i = 0; i < 14; i++) {
1406 index = _rtl8723ae_get_chnl_group((u8) i);
1407
1408 rtlefuse->txpwrlevel_cck[rf_path][i] =
1409 rtlefuse->eeprom_chnlarea_txpwr_cck
1410 [rf_path][index];
1411 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1412 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1413 [rf_path][index];
1414
1415 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1416 [rf_path][index] -
1417 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path]
1418 [index]) > 0) {
1419 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1420 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1421 [rf_path][index] -
1422 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1423 [rf_path][index];
1424 } else {
1425 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1426 }
1427 }
1428
1429 for (i = 0; i < 14; i++) {
1430 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1431 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1432 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1433 rtlefuse->txpwrlevel_cck[rf_path][i],
1434 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1435 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1436 }
1437 }
1438
1439 for (i = 0; i < 3; i++) {
1440 if (!autoload_fail) {
1441 rtlefuse->eeprom_pwrlimit_ht40[i] =
1442 hwinfo[EEPROM_TXPWR_GROUP + i];
1443 rtlefuse->eeprom_pwrlimit_ht20[i] =
1444 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1445 } else {
1446 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1447 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1448 }
1449 }
1450
1451 for (rf_path = 0; rf_path < 2; rf_path++) {
1452 for (i = 0; i < 14; i++) {
1453 index = _rtl8723ae_get_chnl_group((u8) i);
1454
1455 if (rf_path == RF90_PATH_A) {
1456 rtlefuse->pwrgroup_ht20[rf_path][i] =
1457 (rtlefuse->eeprom_pwrlimit_ht20[index] &
1458 0xf);
1459 rtlefuse->pwrgroup_ht40[rf_path][i] =
1460 (rtlefuse->eeprom_pwrlimit_ht40[index] &
1461 0xf);
1462 } else if (rf_path == RF90_PATH_B) {
1463 rtlefuse->pwrgroup_ht20[rf_path][i] =
1464 ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1465 0xf0) >> 4);
1466 rtlefuse->pwrgroup_ht40[rf_path][i] =
1467 ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1468 0xf0) >> 4);
1469 }
1470
1471 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1472 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1473 rtlefuse->pwrgroup_ht20[rf_path][i]);
1474 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1475 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1476 rtlefuse->pwrgroup_ht40[rf_path][i]);
1477 }
1478 }
1479
1480 for (i = 0; i < 14; i++) {
1481 index = _rtl8723ae_get_chnl_group((u8) i);
1482
1483 if (!autoload_fail)
1484 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1485 else
1486 tempval = EEPROM_DEFAULT_HT20_DIFF;
1487
1488 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1489 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1490 ((tempval >> 4) & 0xF);
1491
1492 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1493 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1494
1495 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1496 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1497
1498 index = _rtl8723ae_get_chnl_group((u8) i);
1499
1500 if (!autoload_fail)
1501 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1502 else
1503 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1504
1505 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1506 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1507 ((tempval >> 4) & 0xF);
1508 }
1509
1510 rtlefuse->legacy_ht_txpowerdiff =
1511 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1512
1513 for (i = 0; i < 14; i++)
1514 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1515 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1516 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1517 for (i = 0; i < 14; i++)
1518 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1519 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1520 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1521 for (i = 0; i < 14; i++)
1522 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1523 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1524 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1525 for (i = 0; i < 14; i++)
1526 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1527 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1528 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1529
1530 if (!autoload_fail)
1531 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1532 else
1533 rtlefuse->eeprom_regulatory = 0;
1534 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1535 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1536
1537 if (!autoload_fail)
1538 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1539 else
1540 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1541 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1542 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1543 rtlefuse->eeprom_tssi[RF90_PATH_A],
1544 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1545
1546 if (!autoload_fail)
1547 tempval = hwinfo[EEPROM_THERMAL_METER];
1548 else
1549 tempval = EEPROM_DEFAULT_THERMALMETER;
1550 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1551
1552 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1553 rtlefuse->apk_thermalmeterignore = true;
1554
1555 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1556 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1557 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1558 }
1559
1560 static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw,
1561 bool pseudo_test)
1562 {
1563 struct rtl_priv *rtlpriv = rtl_priv(hw);
1564 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1565 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1566 u16 i, usvalue;
1567 u8 hwinfo[HWSET_MAX_SIZE];
1568 u16 eeprom_id;
1569
1570 if (pseudo_test) {
1571 /* need add */
1572 return;
1573 }
1574 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1575 rtl_efuse_shadow_map_update(hw);
1576
1577 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1578 HWSET_MAX_SIZE);
1579 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1580 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1581 "RTL819X Not boot from eeprom, check it !!");
1582 }
1583
1584 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1585 hwinfo, HWSET_MAX_SIZE);
1586
1587 eeprom_id = *((u16 *)&hwinfo[0]);
1588 if (eeprom_id != RTL8190_EEPROM_ID) {
1589 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1590 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1591 rtlefuse->autoload_failflag = true;
1592 } else {
1593 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1594 rtlefuse->autoload_failflag = false;
1595 }
1596
1597 if (rtlefuse->autoload_failflag == true)
1598 return;
1599
1600 rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
1601 rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
1602 rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
1603 rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
1604 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1605 "EEPROMId = 0x%4x\n", eeprom_id);
1606 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1607 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1608 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1609 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1610 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1611 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1612 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1613 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1614
1615 for (i = 0; i < 6; i += 2) {
1616 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1617 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1618 }
1619
1620 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1621 "dev_addr: %pM\n", rtlefuse->dev_addr);
1622
1623 _rtl8723ae_read_txpower_info_from_hwpg(hw,
1624 rtlefuse->autoload_failflag, hwinfo);
1625
1626 rtl8723ae_read_bt_coexist_info_from_hwpg(hw,
1627 rtlefuse->autoload_failflag, hwinfo);
1628
1629 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1630 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1631 rtlefuse->txpwr_fromeprom = true;
1632 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1633
1634 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1635 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1636
1637 /* set channel paln to world wide 13 */
1638 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1639
1640 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1641 switch (rtlefuse->eeprom_oemid) {
1642 case EEPROM_CID_DEFAULT:
1643 if (rtlefuse->eeprom_did == 0x8176) {
1644 if (CHK_SVID_SMID(0x10EC, 0x6151) ||
1645 CHK_SVID_SMID(0x10EC, 0x6152) ||
1646 CHK_SVID_SMID(0x10EC, 0x6154) ||
1647 CHK_SVID_SMID(0x10EC, 0x6155) ||
1648 CHK_SVID_SMID(0x10EC, 0x6177) ||
1649 CHK_SVID_SMID(0x10EC, 0x6178) ||
1650 CHK_SVID_SMID(0x10EC, 0x6179) ||
1651 CHK_SVID_SMID(0x10EC, 0x6180) ||
1652 CHK_SVID_SMID(0x10EC, 0x8151) ||
1653 CHK_SVID_SMID(0x10EC, 0x8152) ||
1654 CHK_SVID_SMID(0x10EC, 0x8154) ||
1655 CHK_SVID_SMID(0x10EC, 0x8155) ||
1656 CHK_SVID_SMID(0x10EC, 0x8181) ||
1657 CHK_SVID_SMID(0x10EC, 0x8182) ||
1658 CHK_SVID_SMID(0x10EC, 0x8184) ||
1659 CHK_SVID_SMID(0x10EC, 0x8185) ||
1660 CHK_SVID_SMID(0x10EC, 0x9151) ||
1661 CHK_SVID_SMID(0x10EC, 0x9152) ||
1662 CHK_SVID_SMID(0x10EC, 0x9154) ||
1663 CHK_SVID_SMID(0x10EC, 0x9155) ||
1664 CHK_SVID_SMID(0x10EC, 0x9181) ||
1665 CHK_SVID_SMID(0x10EC, 0x9182) ||
1666 CHK_SVID_SMID(0x10EC, 0x9184) ||
1667 CHK_SVID_SMID(0x10EC, 0x9185))
1668 rtlhal->oem_id = RT_CID_TOSHIBA;
1669 else if (rtlefuse->eeprom_svid == 0x1025)
1670 rtlhal->oem_id = RT_CID_819x_Acer;
1671 else if (CHK_SVID_SMID(0x10EC, 0x6191) ||
1672 CHK_SVID_SMID(0x10EC, 0x6192) ||
1673 CHK_SVID_SMID(0x10EC, 0x6193) ||
1674 CHK_SVID_SMID(0x10EC, 0x7191) ||
1675 CHK_SVID_SMID(0x10EC, 0x7192) ||
1676 CHK_SVID_SMID(0x10EC, 0x7193) ||
1677 CHK_SVID_SMID(0x10EC, 0x8191) ||
1678 CHK_SVID_SMID(0x10EC, 0x8192) ||
1679 CHK_SVID_SMID(0x10EC, 0x8193))
1680 rtlhal->oem_id = RT_CID_819x_SAMSUNG;
1681 else if (CHK_SVID_SMID(0x10EC, 0x8195) ||
1682 CHK_SVID_SMID(0x10EC, 0x9195) ||
1683 CHK_SVID_SMID(0x10EC, 0x7194) ||
1684 CHK_SVID_SMID(0x10EC, 0x8200) ||
1685 CHK_SVID_SMID(0x10EC, 0x8201) ||
1686 CHK_SVID_SMID(0x10EC, 0x8202) ||
1687 CHK_SVID_SMID(0x10EC, 0x9200))
1688 rtlhal->oem_id = RT_CID_819x_Lenovo;
1689 else if (CHK_SVID_SMID(0x10EC, 0x8197) ||
1690 CHK_SVID_SMID(0x10EC, 0x9196))
1691 rtlhal->oem_id = RT_CID_819x_CLEVO;
1692 else if (CHK_SVID_SMID(0x1028, 0x8194) ||
1693 CHK_SVID_SMID(0x1028, 0x8198) ||
1694 CHK_SVID_SMID(0x1028, 0x9197) ||
1695 CHK_SVID_SMID(0x1028, 0x9198))
1696 rtlhal->oem_id = RT_CID_819x_DELL;
1697 else if (CHK_SVID_SMID(0x103C, 0x1629))
1698 rtlhal->oem_id = RT_CID_819x_HP;
1699 else if (CHK_SVID_SMID(0x1A32, 0x2315))
1700 rtlhal->oem_id = RT_CID_819x_QMI;
1701 else if (CHK_SVID_SMID(0x10EC, 0x8203))
1702 rtlhal->oem_id = RT_CID_819x_PRONETS;
1703 else if (CHK_SVID_SMID(0x1043, 0x84B5))
1704 rtlhal->oem_id =
1705 RT_CID_819x_Edimax_ASUS;
1706 else
1707 rtlhal->oem_id = RT_CID_DEFAULT;
1708 } else if (rtlefuse->eeprom_did == 0x8178) {
1709 if (CHK_SVID_SMID(0x10EC, 0x6181) ||
1710 CHK_SVID_SMID(0x10EC, 0x6182) ||
1711 CHK_SVID_SMID(0x10EC, 0x6184) ||
1712 CHK_SVID_SMID(0x10EC, 0x6185) ||
1713 CHK_SVID_SMID(0x10EC, 0x7181) ||
1714 CHK_SVID_SMID(0x10EC, 0x7182) ||
1715 CHK_SVID_SMID(0x10EC, 0x7184) ||
1716 CHK_SVID_SMID(0x10EC, 0x7185) ||
1717 CHK_SVID_SMID(0x10EC, 0x8181) ||
1718 CHK_SVID_SMID(0x10EC, 0x8182) ||
1719 CHK_SVID_SMID(0x10EC, 0x8184) ||
1720 CHK_SVID_SMID(0x10EC, 0x8185) ||
1721 CHK_SVID_SMID(0x10EC, 0x9181) ||
1722 CHK_SVID_SMID(0x10EC, 0x9182) ||
1723 CHK_SVID_SMID(0x10EC, 0x9184) ||
1724 CHK_SVID_SMID(0x10EC, 0x9185))
1725 rtlhal->oem_id = RT_CID_TOSHIBA;
1726 else if (rtlefuse->eeprom_svid == 0x1025)
1727 rtlhal->oem_id = RT_CID_819x_Acer;
1728 else if (CHK_SVID_SMID(0x10EC, 0x8186))
1729 rtlhal->oem_id = RT_CID_819x_PRONETS;
1730 else if (CHK_SVID_SMID(0x1043, 0x8486))
1731 rtlhal->oem_id =
1732 RT_CID_819x_Edimax_ASUS;
1733 else
1734 rtlhal->oem_id = RT_CID_DEFAULT;
1735 } else {
1736 rtlhal->oem_id = RT_CID_DEFAULT;
1737 }
1738 break;
1739 case EEPROM_CID_TOSHIBA:
1740 rtlhal->oem_id = RT_CID_TOSHIBA;
1741 break;
1742 case EEPROM_CID_CCX:
1743 rtlhal->oem_id = RT_CID_CCX;
1744 break;
1745 case EEPROM_CID_QMI:
1746 rtlhal->oem_id = RT_CID_819x_QMI;
1747 break;
1748 case EEPROM_CID_WHQL:
1749 break;
1750 default:
1751 rtlhal->oem_id = RT_CID_DEFAULT;
1752 break;
1753
1754 }
1755 }
1756 }
1757
1758 static void _rtl8723ae_hal_customized_behavior(struct ieee80211_hw *hw)
1759 {
1760 struct rtl_priv *rtlpriv = rtl_priv(hw);
1761 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1762 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1763
1764 pcipriv->ledctl.led_opendrain = true;
1765 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1766 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1767 }
1768
1769 void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw)
1770 {
1771 struct rtl_priv *rtlpriv = rtl_priv(hw);
1772 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1773 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1775 u8 tmp_u1b;
1776 u32 value32;
1777
1778 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1779 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1780 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1781
1782 rtlhal->version = _rtl8723ae_read_chip_version(hw);
1783
1784 if (get_rf_type(rtlphy) == RF_1T1R)
1785 rtlpriv->dm.rfpath_rxenable[0] = true;
1786 else
1787 rtlpriv->dm.rfpath_rxenable[0] =
1788 rtlpriv->dm.rfpath_rxenable[1] = true;
1789 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1790 rtlhal->version);
1791
1792 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1793 if (tmp_u1b & BIT(4)) {
1794 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1795 rtlefuse->epromtype = EEPROM_93C46;
1796 } else {
1797 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1798 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1799 }
1800 if (tmp_u1b & BIT(5)) {
1801 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1802 rtlefuse->autoload_failflag = false;
1803 _rtl8723ae_read_adapter_info(hw, false);
1804 } else {
1805 rtlefuse->autoload_failflag = true;
1806 _rtl8723ae_read_adapter_info(hw, false);
1807 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1808 }
1809 _rtl8723ae_hal_customized_behavior(hw);
1810 }
1811
1812 static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw,
1813 struct ieee80211_sta *sta)
1814 {
1815 struct rtl_priv *rtlpriv = rtl_priv(hw);
1816 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1817 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1818 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1819 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1820 u32 ratr_value;
1821 u8 ratr_index = 0;
1822 u8 nmode = mac->ht_enable;
1823 u8 mimo_ps = IEEE80211_SMPS_OFF;
1824 u8 curtxbw_40mhz = mac->bw_40;
1825 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1826 1 : 0;
1827 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1828 1 : 0;
1829 enum wireless_mode wirelessmode = mac->mode;
1830
1831 if (rtlhal->current_bandtype == BAND_ON_5G)
1832 ratr_value = sta->supp_rates[1] << 4;
1833 else
1834 ratr_value = sta->supp_rates[0];
1835 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1836 ratr_value = 0xfff;
1837 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1838 sta->ht_cap.mcs.rx_mask[0] << 12);
1839 switch (wirelessmode) {
1840 case WIRELESS_MODE_B:
1841 if (ratr_value & 0x0000000c)
1842 ratr_value &= 0x0000000d;
1843 else
1844 ratr_value &= 0x0000000f;
1845 break;
1846 case WIRELESS_MODE_G:
1847 ratr_value &= 0x00000FF5;
1848 break;
1849 case WIRELESS_MODE_N_24G:
1850 case WIRELESS_MODE_N_5G:
1851 nmode = 1;
1852 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1853 ratr_value &= 0x0007F005;
1854 } else {
1855 u32 ratr_mask;
1856
1857 if (get_rf_type(rtlphy) == RF_1T2R ||
1858 get_rf_type(rtlphy) == RF_1T1R)
1859 ratr_mask = 0x000ff005;
1860 else
1861 ratr_mask = 0x0f0ff005;
1862
1863 ratr_value &= ratr_mask;
1864 }
1865 break;
1866 default:
1867 if (rtlphy->rf_type == RF_1T2R)
1868 ratr_value &= 0x000ff0ff;
1869 else
1870 ratr_value &= 0x0f0ff0ff;
1871
1872 break;
1873 }
1874
1875 if ((pcipriv->bt_coexist.bt_coexistence) &&
1876 (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1877 (pcipriv->bt_coexist.bt_cur_state) &&
1878 (pcipriv->bt_coexist.bt_ant_isolation) &&
1879 ((pcipriv->bt_coexist.bt_service == BT_SCO) ||
1880 (pcipriv->bt_coexist.bt_service == BT_BUSY)))
1881 ratr_value &= 0x0fffcfc0;
1882 else
1883 ratr_value &= 0x0FFFFFFF;
1884
1885 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1886 (!curtxbw_40mhz && curshortgi_20mhz)))
1887 ratr_value |= 0x10000000;
1888
1889 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1890
1891 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1892 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1893 }
1894
1895 static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw,
1896 struct ieee80211_sta *sta, u8 rssi_level)
1897 {
1898 struct rtl_priv *rtlpriv = rtl_priv(hw);
1899 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1900 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1901 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1902 struct rtl_sta_info *sta_entry = NULL;
1903 u32 ratr_bitmap;
1904 u8 ratr_index;
1905 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1906 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1907 1 : 0;
1908 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1909 1 : 0;
1910 enum wireless_mode wirelessmode = 0;
1911 bool shortgi = false;
1912 u8 rate_mask[5];
1913 u8 macid = 0;
1914 u8 mimo_ps = IEEE80211_SMPS_OFF;
1915
1916 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1917 wirelessmode = sta_entry->wireless_mode;
1918 if (mac->opmode == NL80211_IFTYPE_STATION)
1919 curtxbw_40mhz = mac->bw_40;
1920 else if (mac->opmode == NL80211_IFTYPE_AP ||
1921 mac->opmode == NL80211_IFTYPE_ADHOC)
1922 macid = sta->aid + 1;
1923
1924 if (rtlhal->current_bandtype == BAND_ON_5G)
1925 ratr_bitmap = sta->supp_rates[1] << 4;
1926 else
1927 ratr_bitmap = sta->supp_rates[0];
1928 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1929 ratr_bitmap = 0xfff;
1930 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1931 sta->ht_cap.mcs.rx_mask[0] << 12);
1932 switch (wirelessmode) {
1933 case WIRELESS_MODE_B:
1934 ratr_index = RATR_INX_WIRELESS_B;
1935 if (ratr_bitmap & 0x0000000c)
1936 ratr_bitmap &= 0x0000000d;
1937 else
1938 ratr_bitmap &= 0x0000000f;
1939 break;
1940 case WIRELESS_MODE_G:
1941 ratr_index = RATR_INX_WIRELESS_GB;
1942
1943 if (rssi_level == 1)
1944 ratr_bitmap &= 0x00000f00;
1945 else if (rssi_level == 2)
1946 ratr_bitmap &= 0x00000ff0;
1947 else
1948 ratr_bitmap &= 0x00000ff5;
1949 break;
1950 case WIRELESS_MODE_A:
1951 ratr_index = RATR_INX_WIRELESS_A;
1952 ratr_bitmap &= 0x00000ff0;
1953 break;
1954 case WIRELESS_MODE_N_24G:
1955 case WIRELESS_MODE_N_5G:
1956 ratr_index = RATR_INX_WIRELESS_NGB;
1957
1958 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1959 if (rssi_level == 1)
1960 ratr_bitmap &= 0x00070000;
1961 else if (rssi_level == 2)
1962 ratr_bitmap &= 0x0007f000;
1963 else
1964 ratr_bitmap &= 0x0007f005;
1965 } else {
1966 if (rtlphy->rf_type == RF_1T2R ||
1967 rtlphy->rf_type == RF_1T1R) {
1968 if (curtxbw_40mhz) {
1969 if (rssi_level == 1)
1970 ratr_bitmap &= 0x000f0000;
1971 else if (rssi_level == 2)
1972 ratr_bitmap &= 0x000ff000;
1973 else
1974 ratr_bitmap &= 0x000ff015;
1975 } else {
1976 if (rssi_level == 1)
1977 ratr_bitmap &= 0x000f0000;
1978 else if (rssi_level == 2)
1979 ratr_bitmap &= 0x000ff000;
1980 else
1981 ratr_bitmap &= 0x000ff005;
1982 }
1983 } else {
1984 if (curtxbw_40mhz) {
1985 if (rssi_level == 1)
1986 ratr_bitmap &= 0x0f0f0000;
1987 else if (rssi_level == 2)
1988 ratr_bitmap &= 0x0f0ff000;
1989 else
1990 ratr_bitmap &= 0x0f0ff015;
1991 } else {
1992 if (rssi_level == 1)
1993 ratr_bitmap &= 0x0f0f0000;
1994 else if (rssi_level == 2)
1995 ratr_bitmap &= 0x0f0ff000;
1996 else
1997 ratr_bitmap &= 0x0f0ff005;
1998 }
1999 }
2000 }
2001
2002 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2003 (!curtxbw_40mhz && curshortgi_20mhz)) {
2004 if (macid == 0)
2005 shortgi = true;
2006 else if (macid == 1)
2007 shortgi = false;
2008 }
2009 break;
2010 default:
2011 ratr_index = RATR_INX_WIRELESS_NGB;
2012
2013 if (rtlphy->rf_type == RF_1T2R)
2014 ratr_bitmap &= 0x000ff0ff;
2015 else
2016 ratr_bitmap &= 0x0f0ff0ff;
2017 break;
2018 }
2019 sta_entry->ratr_index = ratr_index;
2020
2021 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2022 "ratr_bitmap :%x\n", ratr_bitmap);
2023 /* convert ratr_bitmap to le byte array */
2024 rate_mask[0] = ratr_bitmap;
2025 rate_mask[1] = (ratr_bitmap >>= 8);
2026 rate_mask[2] = (ratr_bitmap >>= 8);
2027 rate_mask[3] = ((ratr_bitmap >> 8) & 0x0f) | (ratr_index << 4);
2028 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2029 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2030 "Rate_index:%x, ratr_bitmap: %*phC\n",
2031 ratr_index, 5, rate_mask);
2032 rtl8723ae_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2033 }
2034
2035 void rtl8723ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
2036 struct ieee80211_sta *sta, u8 rssi_level)
2037 {
2038 struct rtl_priv *rtlpriv = rtl_priv(hw);
2039
2040 if (rtlpriv->dm.useramask)
2041 rtl8723ae_update_hal_rate_mask(hw, sta, rssi_level);
2042 else
2043 rtl8723ae_update_hal_rate_table(hw, sta);
2044 }
2045
2046 void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw)
2047 {
2048 struct rtl_priv *rtlpriv = rtl_priv(hw);
2049 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2050 u16 sifs_timer;
2051
2052 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2053 (u8 *)&mac->slot_time);
2054 if (!mac->ht_enable)
2055 sifs_timer = 0x0a0a;
2056 else
2057 sifs_timer = 0x1010;
2058 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2059 }
2060
2061 bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2062 {
2063 struct rtl_priv *rtlpriv = rtl_priv(hw);
2064 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2065 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2066 enum rf_pwrstate e_rfpowerstate_toset;
2067 u8 u1tmp;
2068 bool actuallyset = false;
2069
2070 if (rtlpriv->rtlhal.being_init_adapter)
2071 return false;
2072
2073 if (ppsc->swrf_processing)
2074 return false;
2075
2076 spin_lock(&rtlpriv->locks.rf_ps_lock);
2077 if (ppsc->rfchange_inprogress) {
2078 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2079 return false;
2080 } else {
2081 ppsc->rfchange_inprogress = true;
2082 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2083 }
2084
2085 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2086 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2087
2088 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2089
2090 if (rtlphy->polarity_ctl)
2091 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2092 else
2093 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2094
2095 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
2096 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2097 "GPIOChangeRF - HW Radio ON, RF ON\n");
2098
2099 e_rfpowerstate_toset = ERFON;
2100 ppsc->hwradiooff = false;
2101 actuallyset = true;
2102 } else if ((ppsc->hwradiooff == false)
2103 && (e_rfpowerstate_toset == ERFOFF)) {
2104 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2105 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2106
2107 e_rfpowerstate_toset = ERFOFF;
2108 ppsc->hwradiooff = true;
2109 actuallyset = true;
2110 }
2111
2112 if (actuallyset) {
2113 spin_lock(&rtlpriv->locks.rf_ps_lock);
2114 ppsc->rfchange_inprogress = false;
2115 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2116 } else {
2117 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2118 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2119
2120 spin_lock(&rtlpriv->locks.rf_ps_lock);
2121 ppsc->rfchange_inprogress = false;
2122 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2123 }
2124
2125 *valid = 1;
2126 return !ppsc->hwradiooff;
2127 }
2128
2129 void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
2130 u8 *p_macaddr, bool is_group, u8 enc_algo,
2131 bool is_wepkey, bool clear_all)
2132 {
2133 struct rtl_priv *rtlpriv = rtl_priv(hw);
2134 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2135 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2136 u8 *macaddr = p_macaddr;
2137 u32 entry_id = 0;
2138 bool is_pairwise = false;
2139 static u8 cam_const_addr[4][6] = {
2140 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2141 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2142 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2143 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2144 };
2145 static u8 cam_const_broad[] = {
2146 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2147 };
2148
2149 if (clear_all) {
2150 u8 idx = 0;
2151 u8 cam_offset = 0;
2152 u8 clear_number = 5;
2153
2154 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2155
2156 for (idx = 0; idx < clear_number; idx++) {
2157 rtl_cam_mark_invalid(hw, cam_offset + idx);
2158 rtl_cam_empty_entry(hw, cam_offset + idx);
2159
2160 if (idx < 5) {
2161 memset(rtlpriv->sec.key_buf[idx], 0,
2162 MAX_KEY_LEN);
2163 rtlpriv->sec.key_len[idx] = 0;
2164 }
2165 }
2166 } else {
2167 switch (enc_algo) {
2168 case WEP40_ENCRYPTION:
2169 enc_algo = CAM_WEP40;
2170 break;
2171 case WEP104_ENCRYPTION:
2172 enc_algo = CAM_WEP104;
2173 break;
2174 case TKIP_ENCRYPTION:
2175 enc_algo = CAM_TKIP;
2176 break;
2177 case AESCCMP_ENCRYPTION:
2178 enc_algo = CAM_AES;
2179 break;
2180 default:
2181 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2182 "switch case not processed\n");
2183 enc_algo = CAM_TKIP;
2184 break;
2185 }
2186
2187 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2188 macaddr = cam_const_addr[key_index];
2189 entry_id = key_index;
2190 } else {
2191 if (is_group) {
2192 macaddr = cam_const_broad;
2193 entry_id = key_index;
2194 } else {
2195 if (mac->opmode == NL80211_IFTYPE_AP) {
2196 entry_id = rtl_cam_get_free_entry(hw,
2197 macaddr);
2198 if (entry_id >= TOTAL_CAM_ENTRY) {
2199 RT_TRACE(rtlpriv, COMP_SEC,
2200 DBG_EMERG,
2201 "Can not find free hw security cam entry\n");
2202 return;
2203 }
2204 } else {
2205 entry_id = CAM_PAIRWISE_KEY_POSITION;
2206 }
2207
2208 key_index = PAIRWISE_KEYIDX;
2209 is_pairwise = true;
2210 }
2211 }
2212
2213 if (rtlpriv->sec.key_len[key_index] == 0) {
2214 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2215 "delete one entry, entry_id is %d\n",
2216 entry_id);
2217 if (mac->opmode == NL80211_IFTYPE_AP)
2218 rtl_cam_del_entry(hw, p_macaddr);
2219 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2220 } else {
2221 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2222 "add one entry\n");
2223 if (is_pairwise) {
2224 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2225 "set Pairwiase key\n");
2226
2227 rtl_cam_add_one_entry(hw, macaddr, key_index,
2228 entry_id, enc_algo,
2229 CAM_CONFIG_NO_USEDK,
2230 rtlpriv->sec.key_buf[key_index]);
2231 } else {
2232 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2233 "set group key\n");
2234
2235 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2236 rtl_cam_add_one_entry(hw,
2237 rtlefuse->dev_addr,
2238 PAIRWISE_KEYIDX,
2239 CAM_PAIRWISE_KEY_POSITION,
2240 enc_algo,
2241 CAM_CONFIG_NO_USEDK,
2242 rtlpriv->sec.key_buf
2243 [entry_id]);
2244 }
2245
2246 rtl_cam_add_one_entry(hw, macaddr, key_index,
2247 entry_id, enc_algo,
2248 CAM_CONFIG_NO_USEDK,
2249 rtlpriv->sec.key_buf[entry_id]);
2250 }
2251
2252 }
2253 }
2254 }
2255
2256 static void rtl8723ae_bt_var_init(struct ieee80211_hw *hw)
2257 {
2258 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2259 struct rtl_priv *rtlpriv = rtl_priv(hw);
2260
2261 pcipriv->bt_coexist.bt_coexistence =
2262 pcipriv->bt_coexist.eeprom_bt_coexist;
2263 pcipriv->bt_coexist.bt_ant_num =
2264 pcipriv->bt_coexist.eeprom_bt_ant_num;
2265 pcipriv->bt_coexist.bt_coexist_type =
2266 pcipriv->bt_coexist.eeprom_bt_type;
2267
2268 pcipriv->bt_coexist.bt_ant_isolation =
2269 pcipriv->bt_coexist.eeprom_bt_ant_isol;
2270
2271 pcipriv->bt_coexist.bt_radio_shared_type =
2272 pcipriv->bt_coexist.eeprom_bt_radio_shared;
2273
2274 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2275 "BT Coexistance = 0x%x\n",
2276 pcipriv->bt_coexist.bt_coexistence);
2277
2278 if (pcipriv->bt_coexist.bt_coexistence) {
2279 pcipriv->bt_coexist.bt_busy_traffic = false;
2280 pcipriv->bt_coexist.bt_traffic_mode_set = false;
2281 pcipriv->bt_coexist.bt_non_traffic_mode_set = false;
2282
2283 pcipriv->bt_coexist.cstate = 0;
2284 pcipriv->bt_coexist.previous_state = 0;
2285
2286 if (pcipriv->bt_coexist.bt_ant_num == ANT_X2) {
2287 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2288 "BlueTooth BT_Ant_Num = Antx2\n");
2289 } else if (pcipriv->bt_coexist.bt_ant_num == ANT_X1) {
2290 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2291 "BlueTooth BT_Ant_Num = Antx1\n");
2292 }
2293
2294 switch (pcipriv->bt_coexist.bt_coexist_type) {
2295 case BT_2WIRE:
2296 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2297 "BlueTooth BT_CoexistType = BT_2Wire\n");
2298 break;
2299 case BT_ISSC_3WIRE:
2300 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2301 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2302 break;
2303 case BT_ACCEL:
2304 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2305 "BlueTooth BT_CoexistType = BT_ACCEL\n");
2306 break;
2307 case BT_CSR_BC4:
2308 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2309 "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2310 break;
2311 case BT_CSR_BC8:
2312 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2313 "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2314 break;
2315 case BT_RTL8756:
2316 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2317 "BlueTooth BT_CoexistType = BT_RTL8756\n");
2318 break;
2319 default:
2320 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2321 "BlueTooth BT_CoexistType = Unknown\n");
2322 break;
2323 }
2324 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2325 "BlueTooth BT_Ant_isolation = %d\n",
2326 pcipriv->bt_coexist.bt_ant_isolation);
2327 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2328 "BT_RadioSharedType = 0x%x\n",
2329 pcipriv->bt_coexist.bt_radio_shared_type);
2330 pcipriv->bt_coexist.bt_active_zero_cnt = 0;
2331 pcipriv->bt_coexist.cur_bt_disabled = false;
2332 pcipriv->bt_coexist.pre_bt_disabled = false;
2333 }
2334 }
2335
2336 void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2337 bool auto_load_fail, u8 *hwinfo)
2338 {
2339 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2340 struct rtl_priv *rtlpriv = rtl_priv(hw);
2341 u8 value;
2342 u32 tmpu_32;
2343
2344 if (!auto_load_fail) {
2345 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2346 if (tmpu_32 & BIT(18))
2347 pcipriv->bt_coexist.eeprom_bt_coexist = 1;
2348 else
2349 pcipriv->bt_coexist.eeprom_bt_coexist = 0;
2350 value = hwinfo[RF_OPTION4];
2351 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A;
2352 pcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2353 pcipriv->bt_coexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2354 pcipriv->bt_coexist.eeprom_bt_radio_shared =
2355 ((value & 0x20) >> 5);
2356 } else {
2357 pcipriv->bt_coexist.eeprom_bt_coexist = 0;
2358 pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A;
2359 pcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2360 pcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2361 pcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2362 }
2363
2364 rtl8723ae_bt_var_init(hw);
2365 }
2366
2367 void rtl8723ae_bt_reg_init(struct ieee80211_hw *hw)
2368 {
2369 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2370
2371 /* 0:Low, 1:High, 2:From Efuse. */
2372 pcipriv->bt_coexist.reg_bt_iso = 2;
2373 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2374 pcipriv->bt_coexist.reg_bt_sco = 3;
2375 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2376 pcipriv->bt_coexist.reg_bt_sco = 0;
2377 }
2378
2379
2380 void rtl8723ae_bt_hw_init(struct ieee80211_hw *hw)
2381 {
2382 }
2383
2384 void rtl8723ae_suspend(struct ieee80211_hw *hw)
2385 {
2386 }
2387
2388 void rtl8723ae_resume(struct ieee80211_hw *hw)
2389 {
2390 }
2391
2392 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2393 void rtl8723ae_allow_all_destaddr(struct ieee80211_hw *hw,
2394 bool allow_all_da, bool write_into_reg)
2395 {
2396 struct rtl_priv *rtlpriv = rtl_priv(hw);
2397 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2398
2399 if (allow_all_da) /* Set BIT0 */
2400 rtlpci->receive_config |= RCR_AAP;
2401 else /* Clear BIT0 */
2402 rtlpci->receive_config &= ~RCR_AAP;
2403
2404 if (write_into_reg)
2405 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2406
2407
2408 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2409 "receive_config=0x%08X, write_into_reg=%d\n",
2410 rtlpci->receive_config, write_into_reg);
2411 }
Linux with added FPC-III support