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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / wifi.h
blobe576a927fde7bf9db5b8c9c349a9af69a81d9565
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #include <linux/sched.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <linux/vmalloc.h>
39 #include <linux/usb.h>
40 #include <net/mac80211.h>
41 #include <linux/completion.h>
42 #include "debug.h"
43
44 #define RF_CHANGE_BY_INIT 0
45 #define RF_CHANGE_BY_IPS BIT(28)
46 #define RF_CHANGE_BY_PS BIT(29)
47 #define RF_CHANGE_BY_HW BIT(30)
48 #define RF_CHANGE_BY_SW BIT(31)
49
50 #define IQK_ADDA_REG_NUM 16
51 #define IQK_MAC_REG_NUM 4
52
53 #define MAX_KEY_LEN 61
54 #define KEY_BUF_SIZE 5
55
56 /* QoS related. */
57 /*aci: 0x00 Best Effort*/
58 /*aci: 0x01 Background*/
59 /*aci: 0x10 Video*/
60 /*aci: 0x11 Voice*/
61 /*Max: define total number.*/
62 #define AC0_BE 0
63 #define AC1_BK 1
64 #define AC2_VI 2
65 #define AC3_VO 3
66 #define AC_MAX 4
67 #define QOS_QUEUE_NUM 4
68 #define RTL_MAC80211_NUM_QUEUE 5
69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
70 #define RTL_USB_MAX_RX_COUNT 100
71 #define QBSS_LOAD_SIZE 5
72 #define MAX_WMMELE_LENGTH 64
73
74 #define TOTAL_CAM_ENTRY 32
75
76 /*slot time for 11g. */
77 #define RTL_SLOT_TIME_9 9
78 #define RTL_SLOT_TIME_20 20
79
80 /*related to tcp/ip. */
81 #define SNAP_SIZE 6
82 #define PROTOC_TYPE_SIZE 2
83
84 /*related with 802.11 frame*/
85 #define MAC80211_3ADDR_LEN 24
86 #define MAC80211_4ADDR_LEN 30
87
88 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
89 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
90 #define MAX_PG_GROUP 13
91 #define CHANNEL_GROUP_MAX_2G 3
92 #define CHANNEL_GROUP_IDX_5GL 3
93 #define CHANNEL_GROUP_IDX_5GM 6
94 #define CHANNEL_GROUP_IDX_5GH 9
95 #define CHANNEL_GROUP_MAX_5G 9
96 #define CHANNEL_MAX_NUMBER_2G 14
97 #define AVG_THERMAL_NUM 8
98 #define AVG_THERMAL_NUM_88E 4
99 #define MAX_TID_COUNT 9
100
101 /* for early mode */
102 #define FCS_LEN 4
103 #define EM_HDR_LEN 8
104
105 #define MAX_TX_COUNT 4
106 #define MAX_RF_PATH 4
107 #define MAX_CHNL_GROUP_24G 6
108 #define MAX_CHNL_GROUP_5G 14
109
110 struct txpower_info_2g {
111 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
112 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
113 /*If only one tx, only BW20 and OFDM are used.*/
114 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
115 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
116 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
117 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
118 };
119
120 struct txpower_info_5g {
121 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
122 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
123 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
124 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
125 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
126 };
127
128 enum intf_type {
129 INTF_PCI = 0,
130 INTF_USB = 1,
131 };
132
133 enum radio_path {
134 RF90_PATH_A = 0,
135 RF90_PATH_B = 1,
136 RF90_PATH_C = 2,
137 RF90_PATH_D = 3,
138 };
139
140 enum rt_eeprom_type {
141 EEPROM_93C46,
142 EEPROM_93C56,
143 EEPROM_BOOT_EFUSE,
144 };
145
146 enum ttl_status {
147 RTL_STATUS_INTERFACE_START = 0,
148 };
149
150 enum hardware_type {
151 HARDWARE_TYPE_RTL8192E,
152 HARDWARE_TYPE_RTL8192U,
153 HARDWARE_TYPE_RTL8192SE,
154 HARDWARE_TYPE_RTL8192SU,
155 HARDWARE_TYPE_RTL8192CE,
156 HARDWARE_TYPE_RTL8192CU,
157 HARDWARE_TYPE_RTL8192DE,
158 HARDWARE_TYPE_RTL8192DU,
159 HARDWARE_TYPE_RTL8723AE,
160 HARDWARE_TYPE_RTL8723U,
161 HARDWARE_TYPE_RTL8188EE,
162
163 /* keep it last */
164 HARDWARE_TYPE_NUM
165 };
166
167 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
168 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
169 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
170 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
171 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
172 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
173 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
174 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
175 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
176 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
177 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
178 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
179 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
180 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
181 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
182 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
183 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
184 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
185 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
186 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
187 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
188 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
189 #define IS_HARDWARE_TYPE_8723(rtlhal) \
190 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
191 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
192 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
193
194 #define RX_HAL_IS_CCK_RATE(_pdesc)\
195 (_pdesc->rxmcs == DESC92_RATE1M || \
196 _pdesc->rxmcs == DESC92_RATE2M || \
197 _pdesc->rxmcs == DESC92_RATE5_5M || \
198 _pdesc->rxmcs == DESC92_RATE11M)
199
200 enum scan_operation_backup_opt {
201 SCAN_OPT_BACKUP = 0,
202 SCAN_OPT_RESTORE,
203 SCAN_OPT_MAX
204 };
205
206 /*RF state.*/
207 enum rf_pwrstate {
208 ERFON,
209 ERFSLEEP,
210 ERFOFF
211 };
212
213 struct bb_reg_def {
214 u32 rfintfs;
215 u32 rfintfi;
216 u32 rfintfo;
217 u32 rfintfe;
218 u32 rf3wire_offset;
219 u32 rflssi_select;
220 u32 rftxgain_stage;
221 u32 rfhssi_para1;
222 u32 rfhssi_para2;
223 u32 rfsw_ctrl;
224 u32 rfagc_control1;
225 u32 rfagc_control2;
226 u32 rfrxiq_imbal;
227 u32 rfrx_afe;
228 u32 rftxiq_imbal;
229 u32 rftx_afe;
230 u32 rf_rb; /* rflssi_readback */
231 u32 rf_rbpi; /* rflssi_readbackpi */
232 };
233
234 enum io_type {
235 IO_CMD_PAUSE_DM_BY_SCAN = 0,
236 IO_CMD_RESUME_DM_BY_SCAN = 1,
237 };
238
239 enum hw_variables {
240 HW_VAR_ETHER_ADDR,
241 HW_VAR_MULTICAST_REG,
242 HW_VAR_BASIC_RATE,
243 HW_VAR_BSSID,
244 HW_VAR_MEDIA_STATUS,
245 HW_VAR_SECURITY_CONF,
246 HW_VAR_BEACON_INTERVAL,
247 HW_VAR_ATIM_WINDOW,
248 HW_VAR_LISTEN_INTERVAL,
249 HW_VAR_CS_COUNTER,
250 HW_VAR_DEFAULTKEY0,
251 HW_VAR_DEFAULTKEY1,
252 HW_VAR_DEFAULTKEY2,
253 HW_VAR_DEFAULTKEY3,
254 HW_VAR_SIFS,
255 HW_VAR_DIFS,
256 HW_VAR_EIFS,
257 HW_VAR_SLOT_TIME,
258 HW_VAR_ACK_PREAMBLE,
259 HW_VAR_CW_CONFIG,
260 HW_VAR_CW_VALUES,
261 HW_VAR_RATE_FALLBACK_CONTROL,
262 HW_VAR_CONTENTION_WINDOW,
263 HW_VAR_RETRY_COUNT,
264 HW_VAR_TR_SWITCH,
265 HW_VAR_COMMAND,
266 HW_VAR_WPA_CONFIG,
267 HW_VAR_AMPDU_MIN_SPACE,
268 HW_VAR_SHORTGI_DENSITY,
269 HW_VAR_AMPDU_FACTOR,
270 HW_VAR_MCS_RATE_AVAILABLE,
271 HW_VAR_AC_PARAM,
272 HW_VAR_ACM_CTRL,
273 HW_VAR_DIS_Req_Qsize,
274 HW_VAR_CCX_CHNL_LOAD,
275 HW_VAR_CCX_NOISE_HISTOGRAM,
276 HW_VAR_CCX_CLM_NHM,
277 HW_VAR_TxOPLimit,
278 HW_VAR_TURBO_MODE,
279 HW_VAR_RF_STATE,
280 HW_VAR_RF_OFF_BY_HW,
281 HW_VAR_BUS_SPEED,
282 HW_VAR_SET_DEV_POWER,
283
284 HW_VAR_RCR,
285 HW_VAR_RATR_0,
286 HW_VAR_RRSR,
287 HW_VAR_CPU_RST,
288 HW_VAR_CHECK_BSSID,
289 HW_VAR_LBK_MODE,
290 HW_VAR_AES_11N_FIX,
291 HW_VAR_USB_RX_AGGR,
292 HW_VAR_USER_CONTROL_TURBO_MODE,
293 HW_VAR_RETRY_LIMIT,
294 HW_VAR_INIT_TX_RATE,
295 HW_VAR_TX_RATE_REG,
296 HW_VAR_EFUSE_USAGE,
297 HW_VAR_EFUSE_BYTES,
298 HW_VAR_AUTOLOAD_STATUS,
299 HW_VAR_RF_2R_DISABLE,
300 HW_VAR_SET_RPWM,
301 HW_VAR_H2C_FW_PWRMODE,
302 HW_VAR_H2C_FW_JOINBSSRPT,
303 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
304 HW_VAR_FW_PSMODE_STATUS,
305 HW_VAR_RESUME_CLK_ON,
306 HW_VAR_FW_LPS_ACTION,
307 HW_VAR_1X1_RECV_COMBINE,
308 HW_VAR_STOP_SEND_BEACON,
309 HW_VAR_TSF_TIMER,
310 HW_VAR_IO_CMD,
311
312 HW_VAR_RF_RECOVERY,
313 HW_VAR_H2C_FW_UPDATE_GTK,
314 HW_VAR_WF_MASK,
315 HW_VAR_WF_CRC,
316 HW_VAR_WF_IS_MAC_ADDR,
317 HW_VAR_H2C_FW_OFFLOAD,
318 HW_VAR_RESET_WFCRC,
319
320 HW_VAR_HANDLE_FW_C2H,
321 HW_VAR_DL_FW_RSVD_PAGE,
322 HW_VAR_AID,
323 HW_VAR_HW_SEQ_ENABLE,
324 HW_VAR_CORRECT_TSF,
325 HW_VAR_BCN_VALID,
326 HW_VAR_FWLPS_RF_ON,
327 HW_VAR_DUAL_TSF_RST,
328 HW_VAR_SWITCH_EPHY_WoWLAN,
329 HW_VAR_INT_MIGRATION,
330 HW_VAR_INT_AC,
331 HW_VAR_RF_TIMING,
332
333 HAL_DEF_WOWLAN,
334 HW_VAR_MRC,
335
336 HW_VAR_MGT_FILTER,
337 HW_VAR_CTRL_FILTER,
338 HW_VAR_DATA_FILTER,
339 };
340
341 enum _RT_MEDIA_STATUS {
342 RT_MEDIA_DISCONNECT = 0,
343 RT_MEDIA_CONNECT = 1
344 };
345
346 enum rt_oem_id {
347 RT_CID_DEFAULT = 0,
348 RT_CID_8187_ALPHA0 = 1,
349 RT_CID_8187_SERCOMM_PS = 2,
350 RT_CID_8187_HW_LED = 3,
351 RT_CID_8187_NETGEAR = 4,
352 RT_CID_WHQL = 5,
353 RT_CID_819x_CAMEO = 6,
354 RT_CID_819x_RUNTOP = 7,
355 RT_CID_819x_Senao = 8,
356 RT_CID_TOSHIBA = 9,
357 RT_CID_819x_Netcore = 10,
358 RT_CID_Nettronix = 11,
359 RT_CID_DLINK = 12,
360 RT_CID_PRONET = 13,
361 RT_CID_COREGA = 14,
362 RT_CID_819x_ALPHA = 15,
363 RT_CID_819x_Sitecom = 16,
364 RT_CID_CCX = 17,
365 RT_CID_819x_Lenovo = 18,
366 RT_CID_819x_QMI = 19,
367 RT_CID_819x_Edimax_Belkin = 20,
368 RT_CID_819x_Sercomm_Belkin = 21,
369 RT_CID_819x_CAMEO1 = 22,
370 RT_CID_819x_MSI = 23,
371 RT_CID_819x_Acer = 24,
372 RT_CID_819x_HP = 27,
373 RT_CID_819x_CLEVO = 28,
374 RT_CID_819x_Arcadyan_Belkin = 29,
375 RT_CID_819x_SAMSUNG = 30,
376 RT_CID_819x_WNC_COREGA = 31,
377 RT_CID_819x_Foxcoon = 32,
378 RT_CID_819x_DELL = 33,
379 RT_CID_819x_PRONETS = 34,
380 RT_CID_819x_Edimax_ASUS = 35,
381 RT_CID_NETGEAR = 36,
382 RT_CID_PLANEX = 37,
383 RT_CID_CC_C = 38,
384 };
385
386 enum hw_descs {
387 HW_DESC_OWN,
388 HW_DESC_RXOWN,
389 HW_DESC_TX_NEXTDESC_ADDR,
390 HW_DESC_TXBUFF_ADDR,
391 HW_DESC_RXBUFF_ADDR,
392 HW_DESC_RXPKT_LEN,
393 HW_DESC_RXERO,
394 };
395
396 enum prime_sc {
397 PRIME_CHNL_OFFSET_DONT_CARE = 0,
398 PRIME_CHNL_OFFSET_LOWER = 1,
399 PRIME_CHNL_OFFSET_UPPER = 2,
400 };
401
402 enum rf_type {
403 RF_1T1R = 0,
404 RF_1T2R = 1,
405 RF_2T2R = 2,
406 RF_2T2R_GREEN = 3,
407 };
408
409 enum ht_channel_width {
410 HT_CHANNEL_WIDTH_20 = 0,
411 HT_CHANNEL_WIDTH_20_40 = 1,
412 };
413
414 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
415 Cipher Suites Encryption Algorithms */
416 enum rt_enc_alg {
417 NO_ENCRYPTION = 0,
418 WEP40_ENCRYPTION = 1,
419 TKIP_ENCRYPTION = 2,
420 RSERVED_ENCRYPTION = 3,
421 AESCCMP_ENCRYPTION = 4,
422 WEP104_ENCRYPTION = 5,
423 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
424 };
425
426 enum rtl_hal_state {
427 _HAL_STATE_STOP = 0,
428 _HAL_STATE_START = 1,
429 };
430
431 enum rtl_desc92_rate {
432 DESC92_RATE1M = 0x00,
433 DESC92_RATE2M = 0x01,
434 DESC92_RATE5_5M = 0x02,
435 DESC92_RATE11M = 0x03,
436
437 DESC92_RATE6M = 0x04,
438 DESC92_RATE9M = 0x05,
439 DESC92_RATE12M = 0x06,
440 DESC92_RATE18M = 0x07,
441 DESC92_RATE24M = 0x08,
442 DESC92_RATE36M = 0x09,
443 DESC92_RATE48M = 0x0a,
444 DESC92_RATE54M = 0x0b,
445
446 DESC92_RATEMCS0 = 0x0c,
447 DESC92_RATEMCS1 = 0x0d,
448 DESC92_RATEMCS2 = 0x0e,
449 DESC92_RATEMCS3 = 0x0f,
450 DESC92_RATEMCS4 = 0x10,
451 DESC92_RATEMCS5 = 0x11,
452 DESC92_RATEMCS6 = 0x12,
453 DESC92_RATEMCS7 = 0x13,
454 DESC92_RATEMCS8 = 0x14,
455 DESC92_RATEMCS9 = 0x15,
456 DESC92_RATEMCS10 = 0x16,
457 DESC92_RATEMCS11 = 0x17,
458 DESC92_RATEMCS12 = 0x18,
459 DESC92_RATEMCS13 = 0x19,
460 DESC92_RATEMCS14 = 0x1a,
461 DESC92_RATEMCS15 = 0x1b,
462 DESC92_RATEMCS15_SG = 0x1c,
463 DESC92_RATEMCS32 = 0x20,
464 };
465
466 enum rtl_var_map {
467 /*reg map */
468 SYS_ISO_CTRL = 0,
469 SYS_FUNC_EN,
470 SYS_CLK,
471 MAC_RCR_AM,
472 MAC_RCR_AB,
473 MAC_RCR_ACRC32,
474 MAC_RCR_ACF,
475 MAC_RCR_AAP,
476
477 /*efuse map */
478 EFUSE_TEST,
479 EFUSE_CTRL,
480 EFUSE_CLK,
481 EFUSE_CLK_CTRL,
482 EFUSE_PWC_EV12V,
483 EFUSE_FEN_ELDR,
484 EFUSE_LOADER_CLK_EN,
485 EFUSE_ANA8M,
486 EFUSE_HWSET_MAX_SIZE,
487 EFUSE_MAX_SECTION_MAP,
488 EFUSE_REAL_CONTENT_SIZE,
489 EFUSE_OOB_PROTECT_BYTES_LEN,
490 EFUSE_ACCESS,
491
492 /*CAM map */
493 RWCAM,
494 WCAMI,
495 RCAMO,
496 CAMDBG,
497 SECR,
498 SEC_CAM_NONE,
499 SEC_CAM_WEP40,
500 SEC_CAM_TKIP,
501 SEC_CAM_AES,
502 SEC_CAM_WEP104,
503
504 /*IMR map */
505 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
506 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
507 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
508 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
509 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
510 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
511 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
512 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
513 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
514 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
515 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
516 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
517 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
518 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
519 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
520 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
521 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
522 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
523 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
524 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
525 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
526 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
527 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
528 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
529 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
530 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
531 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
532 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
533 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
534 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
535 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
536 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
537 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
538 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
539 * RTL_IMR_TBDER) */
540 RTL_IMR_C2HCMD, /*fw interrupt*/
541
542 /*CCK Rates, TxHT = 0 */
543 RTL_RC_CCK_RATE1M,
544 RTL_RC_CCK_RATE2M,
545 RTL_RC_CCK_RATE5_5M,
546 RTL_RC_CCK_RATE11M,
547
548 /*OFDM Rates, TxHT = 0 */
549 RTL_RC_OFDM_RATE6M,
550 RTL_RC_OFDM_RATE9M,
551 RTL_RC_OFDM_RATE12M,
552 RTL_RC_OFDM_RATE18M,
553 RTL_RC_OFDM_RATE24M,
554 RTL_RC_OFDM_RATE36M,
555 RTL_RC_OFDM_RATE48M,
556 RTL_RC_OFDM_RATE54M,
557
558 RTL_RC_HT_RATEMCS7,
559 RTL_RC_HT_RATEMCS15,
560
561 /*keep it last */
562 RTL_VAR_MAP_MAX,
563 };
564
565 /*Firmware PS mode for control LPS.*/
566 enum _fw_ps_mode {
567 FW_PS_ACTIVE_MODE = 0,
568 FW_PS_MIN_MODE = 1,
569 FW_PS_MAX_MODE = 2,
570 FW_PS_DTIM_MODE = 3,
571 FW_PS_VOIP_MODE = 4,
572 FW_PS_UAPSD_WMM_MODE = 5,
573 FW_PS_UAPSD_MODE = 6,
574 FW_PS_IBSS_MODE = 7,
575 FW_PS_WWLAN_MODE = 8,
576 FW_PS_PM_Radio_Off = 9,
577 FW_PS_PM_Card_Disable = 10,
578 };
579
580 enum rt_psmode {
581 EACTIVE, /*Active/Continuous access. */
582 EMAXPS, /*Max power save mode. */
583 EFASTPS, /*Fast power save mode. */
584 EAUTOPS, /*Auto power save mode. */
585 };
586
587 /*LED related.*/
588 enum led_ctl_mode {
589 LED_CTL_POWER_ON = 1,
590 LED_CTL_LINK = 2,
591 LED_CTL_NO_LINK = 3,
592 LED_CTL_TX = 4,
593 LED_CTL_RX = 5,
594 LED_CTL_SITE_SURVEY = 6,
595 LED_CTL_POWER_OFF = 7,
596 LED_CTL_START_TO_LINK = 8,
597 LED_CTL_START_WPS = 9,
598 LED_CTL_STOP_WPS = 10,
599 };
600
601 enum rtl_led_pin {
602 LED_PIN_GPIO0,
603 LED_PIN_LED0,
604 LED_PIN_LED1,
605 LED_PIN_LED2
606 };
607
608 /*QoS related.*/
609 /*acm implementation method.*/
610 enum acm_method {
611 eAcmWay0_SwAndHw = 0,
612 eAcmWay1_HW = 1,
613 eAcmWay2_SW = 2,
614 };
615
616 enum macphy_mode {
617 SINGLEMAC_SINGLEPHY = 0,
618 DUALMAC_DUALPHY,
619 DUALMAC_SINGLEPHY,
620 };
621
622 enum band_type {
623 BAND_ON_2_4G = 0,
624 BAND_ON_5G,
625 BAND_ON_BOTH,
626 BANDMAX
627 };
628
629 /*aci/aifsn Field.
630 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
631 union aci_aifsn {
632 u8 char_data;
633
634 struct {
635 u8 aifsn:4;
636 u8 acm:1;
637 u8 aci:2;
638 u8 reserved:1;
639 } f; /* Field */
640 };
641
642 /*mlme related.*/
643 enum wireless_mode {
644 WIRELESS_MODE_UNKNOWN = 0x00,
645 WIRELESS_MODE_A = 0x01,
646 WIRELESS_MODE_B = 0x02,
647 WIRELESS_MODE_G = 0x04,
648 WIRELESS_MODE_AUTO = 0x08,
649 WIRELESS_MODE_N_24G = 0x10,
650 WIRELESS_MODE_N_5G = 0x20
651 };
652
653 #define IS_WIRELESS_MODE_A(wirelessmode) \
654 (wirelessmode == WIRELESS_MODE_A)
655 #define IS_WIRELESS_MODE_B(wirelessmode) \
656 (wirelessmode == WIRELESS_MODE_B)
657 #define IS_WIRELESS_MODE_G(wirelessmode) \
658 (wirelessmode == WIRELESS_MODE_G)
659 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
660 (wirelessmode == WIRELESS_MODE_N_24G)
661 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
662 (wirelessmode == WIRELESS_MODE_N_5G)
663
664 enum ratr_table_mode {
665 RATR_INX_WIRELESS_NGB = 0,
666 RATR_INX_WIRELESS_NG = 1,
667 RATR_INX_WIRELESS_NB = 2,
668 RATR_INX_WIRELESS_N = 3,
669 RATR_INX_WIRELESS_GB = 4,
670 RATR_INX_WIRELESS_G = 5,
671 RATR_INX_WIRELESS_B = 6,
672 RATR_INX_WIRELESS_MC = 7,
673 RATR_INX_WIRELESS_A = 8,
674 };
675
676 enum rtl_link_state {
677 MAC80211_NOLINK = 0,
678 MAC80211_LINKING = 1,
679 MAC80211_LINKED = 2,
680 MAC80211_LINKED_SCANNING = 3,
681 };
682
683 enum act_category {
684 ACT_CAT_QOS = 1,
685 ACT_CAT_DLS = 2,
686 ACT_CAT_BA = 3,
687 ACT_CAT_HT = 7,
688 ACT_CAT_WMM = 17,
689 };
690
691 enum ba_action {
692 ACT_ADDBAREQ = 0,
693 ACT_ADDBARSP = 1,
694 ACT_DELBA = 2,
695 };
696
697 enum rt_polarity_ctl {
698 RT_POLARITY_LOW_ACT = 0,
699 RT_POLARITY_HIGH_ACT = 1,
700 };
701
702 struct octet_string {
703 u8 *octet;
704 u16 length;
705 };
706
707 struct rtl_hdr_3addr {
708 __le16 frame_ctl;
709 __le16 duration_id;
710 u8 addr1[ETH_ALEN];
711 u8 addr2[ETH_ALEN];
712 u8 addr3[ETH_ALEN];
713 __le16 seq_ctl;
714 u8 payload[0];
715 } __packed;
716
717 struct rtl_info_element {
718 u8 id;
719 u8 len;
720 u8 data[0];
721 } __packed;
722
723 struct rtl_probe_rsp {
724 struct rtl_hdr_3addr header;
725 u32 time_stamp[2];
726 __le16 beacon_interval;
727 __le16 capability;
728 /*SSID, supported rates, FH params, DS params,
729 CF params, IBSS params, TIM (if beacon), RSN */
730 struct rtl_info_element info_element[0];
731 } __packed;
732
733 /*LED related.*/
734 /*ledpin Identify how to implement this SW led.*/
735 struct rtl_led {
736 void *hw;
737 enum rtl_led_pin ledpin;
738 bool ledon;
739 };
740
741 struct rtl_led_ctl {
742 bool led_opendrain;
743 struct rtl_led sw_led0;
744 struct rtl_led sw_led1;
745 };
746
747 struct rtl_qos_parameters {
748 __le16 cw_min;
749 __le16 cw_max;
750 u8 aifs;
751 u8 flag;
752 __le16 tx_op;
753 } __packed;
754
755 struct rt_smooth_data {
756 u32 elements[100]; /*array to store values */
757 u32 index; /*index to current array to store */
758 u32 total_num; /*num of valid elements */
759 u32 total_val; /*sum of valid elements */
760 };
761
762 struct false_alarm_statistics {
763 u32 cnt_parity_fail;
764 u32 cnt_rate_illegal;
765 u32 cnt_crc8_fail;
766 u32 cnt_mcs_fail;
767 u32 cnt_fast_fsync_fail;
768 u32 cnt_sb_search_fail;
769 u32 cnt_ofdm_fail;
770 u32 cnt_cck_fail;
771 u32 cnt_all;
772 u32 cnt_ofdm_cca;
773 u32 cnt_cck_cca;
774 u32 cnt_cca_all;
775 u32 cnt_bw_usc;
776 u32 cnt_bw_lsc;
777 };
778
779 struct init_gain {
780 u8 xaagccore1;
781 u8 xbagccore1;
782 u8 xcagccore1;
783 u8 xdagccore1;
784 u8 cca;
785
786 };
787
788 struct wireless_stats {
789 unsigned long txbytesunicast;
790 unsigned long txbytesmulticast;
791 unsigned long txbytesbroadcast;
792 unsigned long rxbytesunicast;
793
794 long rx_snr_db[4];
795 /*Correct smoothed ss in Dbm, only used
796 in driver to report real power now. */
797 long recv_signal_power;
798 long signal_quality;
799 long last_sigstrength_inpercent;
800
801 u32 rssi_calculate_cnt;
802
803 /*Transformed, in dbm. Beautified signal
804 strength for UI, not correct. */
805 long signal_strength;
806
807 u8 rx_rssi_percentage[4];
808 u8 rx_evm_percentage[2];
809
810 struct rt_smooth_data ui_rssi;
811 struct rt_smooth_data ui_link_quality;
812 };
813
814 struct rate_adaptive {
815 u8 rate_adaptive_disabled;
816 u8 ratr_state;
817 u16 reserve;
818
819 u32 high_rssi_thresh_for_ra;
820 u32 high2low_rssi_thresh_for_ra;
821 u8 low2high_rssi_thresh_for_ra40m;
822 u32 low_rssi_thresh_for_ra40M;
823 u8 low2high_rssi_thresh_for_ra20m;
824 u32 low_rssi_thresh_for_ra20M;
825 u32 upper_rssi_threshold_ratr;
826 u32 middleupper_rssi_threshold_ratr;
827 u32 middle_rssi_threshold_ratr;
828 u32 middlelow_rssi_threshold_ratr;
829 u32 low_rssi_threshold_ratr;
830 u32 ultralow_rssi_threshold_ratr;
831 u32 low_rssi_threshold_ratr_40m;
832 u32 low_rssi_threshold_ratr_20m;
833 u8 ping_rssi_enable;
834 u32 ping_rssi_ratr;
835 u32 ping_rssi_thresh_for_ra;
836 u32 last_ratr;
837 u8 pre_ratr_state;
838 };
839
840 struct regd_pair_mapping {
841 u16 reg_dmnenum;
842 u16 reg_5ghz_ctl;
843 u16 reg_2ghz_ctl;
844 };
845
846 struct rtl_regulatory {
847 char alpha2[2];
848 u16 country_code;
849 u16 max_power_level;
850 u32 tp_scale;
851 u16 current_rd;
852 u16 current_rd_ext;
853 int16_t power_limit;
854 struct regd_pair_mapping *regpair;
855 };
856
857 struct rtl_rfkill {
858 bool rfkill_state; /*0 is off, 1 is on */
859 };
860
861 /*for P2P PS**/
862 #define P2P_MAX_NOA_NUM 2
863
864 enum p2p_role {
865 P2P_ROLE_DISABLE = 0,
866 P2P_ROLE_DEVICE = 1,
867 P2P_ROLE_CLIENT = 2,
868 P2P_ROLE_GO = 3
869 };
870
871 enum p2p_ps_state {
872 P2P_PS_DISABLE = 0,
873 P2P_PS_ENABLE = 1,
874 P2P_PS_SCAN = 2,
875 P2P_PS_SCAN_DONE = 3,
876 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
877 };
878
879 enum p2p_ps_mode {
880 P2P_PS_NONE = 0,
881 P2P_PS_CTWINDOW = 1,
882 P2P_PS_NOA = 2,
883 P2P_PS_MIX = 3, /* CTWindow and NoA */
884 };
885
886 struct rtl_p2p_ps_info {
887 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
888 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
889 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
890 /* Client traffic window. A period of time in TU after TBTT. */
891 u8 ctwindow;
892 u8 opp_ps; /* opportunistic power save. */
893 u8 noa_num; /* number of NoA descriptor in P2P IE. */
894 /* Count for owner, Type of client. */
895 u8 noa_count_type[P2P_MAX_NOA_NUM];
896 /* Max duration for owner, preferred or min acceptable duration
897 * for client.
898 */
899 u32 noa_duration[P2P_MAX_NOA_NUM];
900 /* Length of interval for owner, preferred or max acceptable intervali
901 * of client.
902 */
903 u32 noa_interval[P2P_MAX_NOA_NUM];
904 /* schedule in terms of the lower 4 bytes of the TSF timer. */
905 u32 noa_start_time[P2P_MAX_NOA_NUM];
906 };
907
908 struct p2p_ps_offload_t {
909 u8 offload_en:1;
910 u8 role:1; /* 1: Owner, 0: Client */
911 u8 ctwindow_en:1;
912 u8 noa0_en:1;
913 u8 noa1_en:1;
914 u8 allstasleep:1;
915 u8 discovery:1;
916 u8 reserved:1;
917 };
918
919 #define IQK_MATRIX_REG_NUM 8
920 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
921
922 struct iqk_matrix_regs {
923 bool iqk_done;
924 long value[1][IQK_MATRIX_REG_NUM];
925 };
926
927 struct phy_parameters {
928 u16 length;
929 u32 *pdata;
930 };
931
932 enum hw_param_tab_index {
933 PHY_REG_2T,
934 PHY_REG_1T,
935 PHY_REG_PG,
936 RADIOA_2T,
937 RADIOB_2T,
938 RADIOA_1T,
939 RADIOB_1T,
940 MAC_REG,
941 AGCTAB_2T,
942 AGCTAB_1T,
943 MAX_TAB
944 };
945
946 struct rtl_phy {
947 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
948 struct init_gain initgain_backup;
949 enum io_type current_io_type;
950
951 u8 rf_mode;
952 u8 rf_type;
953 u8 current_chan_bw;
954 u8 set_bwmode_inprogress;
955 u8 sw_chnl_inprogress;
956 u8 sw_chnl_stage;
957 u8 sw_chnl_step;
958 u8 current_channel;
959 u8 h2c_box_num;
960 u8 set_io_inprogress;
961 u8 lck_inprogress;
962
963 /* record for power tracking */
964 s32 reg_e94;
965 s32 reg_e9c;
966 s32 reg_ea4;
967 s32 reg_eac;
968 s32 reg_eb4;
969 s32 reg_ebc;
970 s32 reg_ec4;
971 s32 reg_ecc;
972 u8 rfpienable;
973 u8 reserve_0;
974 u16 reserve_1;
975 u32 reg_c04, reg_c08, reg_874;
976 u32 adda_backup[16];
977 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
978 u32 iqk_bb_backup[10];
979 bool iqk_initialized;
980
981 /* Dual mac */
982 bool need_iqk;
983 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
984
985 bool rfpi_enable;
986
987 u8 pwrgroup_cnt;
988 u8 cck_high_power;
989 /* MAX_PG_GROUP groups of pwr diff by rates */
990 u32 mcs_offset[MAX_PG_GROUP][16];
991 u8 default_initialgain[4];
992
993 /* the current Tx power level */
994 u8 cur_cck_txpwridx;
995 u8 cur_ofdm24g_txpwridx;
996 u8 cur_bw20_txpwridx;
997 u8 cur_bw40_txpwridx;
998
999 u32 rfreg_chnlval[2];
1000 bool apk_done;
1001 u32 reg_rf3c[2]; /* pathA / pathB */
1002
1003 /* bfsync */
1004 u8 framesync;
1005 u32 framesync_c34;
1006
1007 u8 num_total_rfpath;
1008 struct phy_parameters hwparam_tables[MAX_TAB];
1009 u16 rf_pathmap;
1010
1011 enum rt_polarity_ctl polarity_ctl;
1012 };
1013
1014 #define MAX_TID_COUNT 9
1015 #define RTL_AGG_STOP 0
1016 #define RTL_AGG_PROGRESS 1
1017 #define RTL_AGG_START 2
1018 #define RTL_AGG_OPERATIONAL 3
1019 #define RTL_AGG_OFF 0
1020 #define RTL_AGG_ON 1
1021 #define RTL_RX_AGG_START 1
1022 #define RTL_RX_AGG_STOP 0
1023 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1024 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1025
1026 struct rtl_ht_agg {
1027 u16 txq_id;
1028 u16 wait_for_ba;
1029 u16 start_idx;
1030 u64 bitmap;
1031 u32 rate_n_flags;
1032 u8 agg_state;
1033 u8 rx_agg_state;
1034 };
1035
1036 struct rssi_sta {
1037 long undec_sm_pwdb;
1038 long undec_sm_cck;
1039 };
1040
1041 struct rtl_tid_data {
1042 u16 seq_number;
1043 struct rtl_ht_agg agg;
1044 };
1045
1046 struct rtl_sta_info {
1047 struct list_head list;
1048 u8 ratr_index;
1049 u8 wireless_mode;
1050 u8 mimo_ps;
1051 u8 mac_addr[ETH_ALEN];
1052 struct rtl_tid_data tids[MAX_TID_COUNT];
1053
1054 /* just used for ap adhoc or mesh*/
1055 struct rssi_sta rssi_stat;
1056 } __packed;
1057
1058 struct rtl_priv;
1059 struct rtl_io {
1060 struct device *dev;
1061 struct mutex bb_mutex;
1062
1063 /*PCI MEM map */
1064 unsigned long pci_mem_end; /*shared mem end */
1065 unsigned long pci_mem_start; /*shared mem start */
1066
1067 /*PCI IO map */
1068 unsigned long pci_base_addr; /*device I/O address */
1069
1070 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1071 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1072 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1073 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1074 u16 len);
1075
1076 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1077 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1078 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1079
1080 };
1081
1082 struct rtl_mac {
1083 u8 mac_addr[ETH_ALEN];
1084 u8 mac80211_registered;
1085 u8 beacon_enabled;
1086
1087 u32 tx_ss_num;
1088 u32 rx_ss_num;
1089
1090 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1091 struct ieee80211_hw *hw;
1092 struct ieee80211_vif *vif;
1093 enum nl80211_iftype opmode;
1094
1095 /*Probe Beacon management */
1096 struct rtl_tid_data tids[MAX_TID_COUNT];
1097 enum rtl_link_state link_state;
1098
1099 int n_channels;
1100 int n_bitrates;
1101
1102 bool offchan_delay;
1103 u8 p2p; /*using p2p role*/
1104 bool p2p_in_use;
1105
1106 /*filters */
1107 u32 rx_conf;
1108 u16 rx_mgt_filter;
1109 u16 rx_ctrl_filter;
1110 u16 rx_data_filter;
1111
1112 bool act_scanning;
1113 u8 cnt_after_linked;
1114 bool skip_scan;
1115
1116 /* early mode */
1117 /* skb wait queue */
1118 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1119
1120 /*RDG*/
1121 bool rdg_en;
1122
1123 /*AP*/
1124 u8 bssid[6];
1125 u32 vendor;
1126 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1127 u32 basic_rates; /* b/g rates */
1128 u8 ht_enable;
1129 u8 sgi_40;
1130 u8 sgi_20;
1131 u8 bw_40;
1132 u8 mode; /* wireless mode */
1133 u8 slot_time;
1134 u8 short_preamble;
1135 u8 use_cts_protect;
1136 u8 cur_40_prime_sc;
1137 u8 cur_40_prime_sc_bk;
1138 u64 tsf;
1139 u8 retry_short;
1140 u8 retry_long;
1141 u16 assoc_id;
1142 bool hiddenssid;
1143
1144 /*IBSS*/
1145 int beacon_interval;
1146
1147 /*AMPDU*/
1148 u8 min_space_cfg; /*For Min spacing configurations */
1149 u8 max_mss_density;
1150 u8 current_ampdu_factor;
1151 u8 current_ampdu_density;
1152
1153 /*QOS & EDCA */
1154 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1155 struct rtl_qos_parameters ac[AC_MAX];
1156
1157 /* counters */
1158 u64 last_txok_cnt;
1159 u64 last_rxok_cnt;
1160 u32 last_bt_edca_ul;
1161 u32 last_bt_edca_dl;
1162 };
1163
1164 struct btdm_8723 {
1165 bool all_off;
1166 bool agc_table_en;
1167 bool adc_back_off_on;
1168 bool b2_ant_hid_en;
1169 bool low_penalty_rate_adaptive;
1170 bool rf_rx_lpf_shrink;
1171 bool reject_aggre_pkt;
1172 bool tra_tdma_on;
1173 u8 tra_tdma_nav;
1174 u8 tra_tdma_ant;
1175 bool tdma_on;
1176 u8 tdma_ant;
1177 u8 tdma_nav;
1178 u8 tdma_dac_swing;
1179 u8 fw_dac_swing_lvl;
1180 bool ps_tdma_on;
1181 u8 ps_tdma_byte[5];
1182 bool pta_on;
1183 u32 val_0x6c0;
1184 u32 val_0x6c8;
1185 u32 val_0x6cc;
1186 bool sw_dac_swing_on;
1187 u32 sw_dac_swing_lvl;
1188 u32 wlan_act_hi;
1189 u32 wlan_act_lo;
1190 u32 bt_retry_index;
1191 bool dec_bt_pwr;
1192 bool ignore_wlan_act;
1193 };
1194
1195 struct bt_coexist_8723 {
1196 u32 high_priority_tx;
1197 u32 high_priority_rx;
1198 u32 low_priority_tx;
1199 u32 low_priority_rx;
1200 u8 c2h_bt_info;
1201 bool c2h_bt_info_req_sent;
1202 bool c2h_bt_inquiry_page;
1203 u32 bt_inq_page_start_time;
1204 u8 bt_retry_cnt;
1205 u8 c2h_bt_info_original;
1206 u8 bt_inquiry_page_cnt;
1207 struct btdm_8723 btdm;
1208 };
1209
1210 struct rtl_hal {
1211 struct ieee80211_hw *hw;
1212 bool driver_is_goingto_unload;
1213 bool up_first_time;
1214 bool first_init;
1215 bool being_init_adapter;
1216 bool bbrf_ready;
1217 bool mac_func_enable;
1218 struct bt_coexist_8723 hal_coex_8723;
1219
1220 enum intf_type interface;
1221 u16 hw_type; /*92c or 92d or 92s and so on */
1222 u8 ic_class;
1223 u8 oem_id;
1224 u32 version; /*version of chip */
1225 u8 state; /*stop 0, start 1 */
1226 u8 board_type;
1227
1228 /*firmware */
1229 u32 fwsize;
1230 u8 *pfirmware;
1231 u16 fw_version;
1232 u16 fw_subversion;
1233 bool h2c_setinprogress;
1234 u8 last_hmeboxnum;
1235 bool fw_ready;
1236 /*Reserve page start offset except beacon in TxQ. */
1237 u8 fw_rsvdpage_startoffset;
1238 u8 h2c_txcmd_seq;
1239
1240 /* FW Cmd IO related */
1241 u16 fwcmd_iomap;
1242 u32 fwcmd_ioparam;
1243 bool set_fwcmd_inprogress;
1244 u8 current_fwcmd_io;
1245
1246 struct p2p_ps_offload_t p2p_ps_offload;
1247 bool fw_clk_change_in_progress;
1248 bool allow_sw_to_change_hwclc;
1249 u8 fw_ps_state;
1250 /**/
1251 bool driver_going2unload;
1252
1253 /*AMPDU init min space*/
1254 u8 minspace_cfg; /*For Min spacing configurations */
1255
1256 /* Dual mac */
1257 enum macphy_mode macphymode;
1258 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1259 enum band_type current_bandtypebackup;
1260 enum band_type bandset;
1261 /* dual MAC 0--Mac0 1--Mac1 */
1262 u32 interfaceindex;
1263 /* just for DualMac S3S4 */
1264 u8 macphyctl_reg;
1265 bool earlymode_enable;
1266 u8 max_earlymode_num;
1267 /* Dual mac*/
1268 bool during_mac0init_radiob;
1269 bool during_mac1init_radioa;
1270 bool reloadtxpowerindex;
1271 /* True if IMR or IQK have done
1272 for 2.4G in scan progress */
1273 bool load_imrandiqk_setting_for2g;
1274
1275 bool disable_amsdu_8k;
1276 bool master_of_dmsp;
1277 bool slave_of_dmsp;
1278 };
1279
1280 struct rtl_security {
1281 /*default 0 */
1282 bool use_sw_sec;
1283
1284 bool being_setkey;
1285 bool use_defaultkey;
1286 /*Encryption Algorithm for Unicast Packet */
1287 enum rt_enc_alg pairwise_enc_algorithm;
1288 /*Encryption Algorithm for Brocast/Multicast */
1289 enum rt_enc_alg group_enc_algorithm;
1290 /*Cam Entry Bitmap */
1291 u32 hwsec_cam_bitmap;
1292 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1293 /*local Key buffer, indx 0 is for
1294 pairwise key 1-4 is for agoup key. */
1295 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1296 u8 key_len[KEY_BUF_SIZE];
1297
1298 /*The pointer of Pairwise Key,
1299 it always points to KeyBuf[4] */
1300 u8 *pairwise_key;
1301 };
1302
1303 #define ASSOCIATE_ENTRY_NUM 33
1304
1305 struct fast_ant_training {
1306 u8 bssid[6];
1307 u8 antsel_rx_keep_0;
1308 u8 antsel_rx_keep_1;
1309 u8 antsel_rx_keep_2;
1310 u32 ant_sum[7];
1311 u32 ant_cnt[7];
1312 u32 ant_ave[7];
1313 u8 fat_state;
1314 u32 train_idx;
1315 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1316 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1317 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1318 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1319 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1320 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1321 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1322 u8 rx_idle_ant;
1323 bool becomelinked;
1324 };
1325
1326 struct rtl_dm {
1327 /*PHY status for Dynamic Management */
1328 long entry_min_undec_sm_pwdb;
1329 long undec_sm_cck;
1330 long undec_sm_pwdb; /*out dm */
1331 long entry_max_undec_sm_pwdb;
1332 s32 ofdm_pkt_cnt;
1333 bool dm_initialgain_enable;
1334 bool dynamic_txpower_enable;
1335 bool current_turbo_edca;
1336 bool is_any_nonbepkts; /*out dm */
1337 bool is_cur_rdlstate;
1338 bool txpower_trackinginit;
1339 bool disable_framebursting;
1340 bool cck_inch14;
1341 bool txpower_tracking;
1342 bool useramask;
1343 bool rfpath_rxenable[4];
1344 bool inform_fw_driverctrldm;
1345 bool current_mrc_switch;
1346 u8 txpowercount;
1347 u8 powerindex_backup[6];
1348
1349 u8 thermalvalue_rxgain;
1350 u8 thermalvalue_iqk;
1351 u8 thermalvalue_lck;
1352 u8 thermalvalue;
1353 u8 last_dtp_lvl;
1354 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1355 u8 thermalvalue_avg_index;
1356 bool done_txpower;
1357 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1358 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1359 u8 dm_flag_tmp;
1360 u8 dm_type;
1361 u8 dm_rssi_sel;
1362 u8 txpower_track_control;
1363 bool interrupt_migration;
1364 bool disable_tx_int;
1365 char ofdm_index[2];
1366 char cck_index;
1367 char delta_power_index;
1368 char delta_power_index_last;
1369 char power_index_offset;
1370
1371 /*88e tx power tracking*/
1372 u8 swing_idx_ofdm[2];
1373 u8 swing_idx_ofdm_cur;
1374 u8 swing_idx_ofdm_base;
1375 bool swing_flag_ofdm;
1376 u8 swing_idx_cck;
1377 u8 swing_idx_cck_cur;
1378 u8 swing_idx_cck_base;
1379 bool swing_flag_cck;
1380
1381 /* DMSP */
1382 bool supp_phymode_switch;
1383
1384 struct fast_ant_training fat_table;
1385 };
1386
1387 #define EFUSE_MAX_LOGICAL_SIZE 256
1388
1389 struct rtl_efuse {
1390 bool autoLoad_ok;
1391 bool bootfromefuse;
1392 u16 max_physical_size;
1393
1394 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1395 u16 efuse_usedbytes;
1396 u8 efuse_usedpercentage;
1397 #ifdef EFUSE_REPG_WORKAROUND
1398 bool efuse_re_pg_sec1flag;
1399 u8 efuse_re_pg_data[8];
1400 #endif
1401
1402 u8 autoload_failflag;
1403 u8 autoload_status;
1404
1405 short epromtype;
1406 u16 eeprom_vid;
1407 u16 eeprom_did;
1408 u16 eeprom_svid;
1409 u16 eeprom_smid;
1410 u8 eeprom_oemid;
1411 u16 eeprom_channelplan;
1412 u8 eeprom_version;
1413 u8 board_type;
1414 u8 external_pa;
1415
1416 u8 dev_addr[6];
1417 u8 wowlan_enable;
1418 u8 antenna_div_cfg;
1419 u8 antenna_div_type;
1420
1421 bool txpwr_fromeprom;
1422 u8 eeprom_crystalcap;
1423 u8 eeprom_tssi[2];
1424 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1425 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1426 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1427 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1428 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1429 u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
1430 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1431 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1432 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1433
1434 u8 internal_pa_5g[2]; /* pathA / pathB */
1435 u8 eeprom_c9;
1436 u8 eeprom_cc;
1437
1438 /*For power group */
1439 u8 eeprom_pwrgroup[2][3];
1440 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1441 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1442
1443 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1444 /*For HT<->legacy pwr diff*/
1445 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1446 u8 txpwr_safetyflag; /* Band edge enable flag */
1447 u16 eeprom_txpowerdiff;
1448 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1449 u8 antenna_txpwdiff[3];
1450
1451 u8 eeprom_regulatory;
1452 u8 eeprom_thermalmeter;
1453 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1454 u16 tssi_13dbm;
1455 u8 crystalcap; /* CrystalCap. */
1456 u8 delta_iqk;
1457 u8 delta_lck;
1458
1459 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1460 bool apk_thermalmeterignore;
1461
1462 bool b1x1_recvcombine;
1463 bool b1ss_support;
1464
1465 /*channel plan */
1466 u8 channel_plan;
1467 };
1468
1469 struct rtl_ps_ctl {
1470 bool pwrdomain_protect;
1471 bool in_powersavemode;
1472 bool rfchange_inprogress;
1473 bool swrf_processing;
1474 bool hwradiooff;
1475 /*
1476 * just for PCIE ASPM
1477 * If it supports ASPM, Offset[560h] = 0x40,
1478 * otherwise Offset[560h] = 0x00.
1479 * */
1480 bool support_aspm;
1481 bool support_backdoor;
1482
1483 /*for LPS */
1484 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1485 bool swctrl_lps;
1486 bool leisure_ps;
1487 bool fwctrl_lps;
1488 u8 fwctrl_psmode;
1489 /*For Fw control LPS mode */
1490 u8 reg_fwctrl_lps;
1491 /*Record Fw PS mode status. */
1492 bool fw_current_inpsmode;
1493 u8 reg_max_lps_awakeintvl;
1494 bool report_linked;
1495 bool low_power_enable;/*for 32k*/
1496
1497 /*for IPS */
1498 bool inactiveps;
1499
1500 u32 rfoff_reason;
1501
1502 /*RF OFF Level */
1503 u32 cur_ps_level;
1504 u32 reg_rfps_level;
1505
1506 /*just for PCIE ASPM */
1507 u8 const_amdpci_aspm;
1508 bool pwrdown_mode;
1509
1510 enum rf_pwrstate inactive_pwrstate;
1511 enum rf_pwrstate rfpwr_state; /*cur power state */
1512
1513 /* for SW LPS*/
1514 bool sw_ps_enabled;
1515 bool state;
1516 bool state_inap;
1517 bool multi_buffered;
1518 u16 nullfunc_seq;
1519 unsigned int dtim_counter;
1520 unsigned int sleep_ms;
1521 unsigned long last_sleep_jiffies;
1522 unsigned long last_awake_jiffies;
1523 unsigned long last_delaylps_stamp_jiffies;
1524 unsigned long last_dtim;
1525 unsigned long last_beacon;
1526 unsigned long last_action;
1527 unsigned long last_slept;
1528
1529 /*For P2P PS */
1530 struct rtl_p2p_ps_info p2p_ps_info;
1531 u8 pwr_mode;
1532 u8 smart_ps;
1533 };
1534
1535 struct rtl_stats {
1536 u8 psaddr[ETH_ALEN];
1537 u32 mac_time[2];
1538 s8 rssi;
1539 u8 signal;
1540 u8 noise;
1541 u8 rate; /* hw desc rate */
1542 u8 received_channel;
1543 u8 control;
1544 u8 mask;
1545 u8 freq;
1546 u16 len;
1547 u64 tsf;
1548 u32 beacon_time;
1549 u8 nic_type;
1550 u16 length;
1551 u8 signalquality; /*in 0-100 index. */
1552 /*
1553 * Real power in dBm for this packet,
1554 * no beautification and aggregation.
1555 * */
1556 s32 recvsignalpower;
1557 s8 rxpower; /*in dBm Translate from PWdB */
1558 u8 signalstrength; /*in 0-100 index. */
1559 u16 hwerror:1;
1560 u16 crc:1;
1561 u16 icv:1;
1562 u16 shortpreamble:1;
1563 u16 antenna:1;
1564 u16 decrypted:1;
1565 u16 wakeup:1;
1566 u32 timestamp_low;
1567 u32 timestamp_high;
1568
1569 u8 rx_drvinfo_size;
1570 u8 rx_bufshift;
1571 bool isampdu;
1572 bool isfirst_ampdu;
1573 bool rx_is40Mhzpacket;
1574 u32 rx_pwdb_all;
1575 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1576 s8 rx_mimo_sig_qual[2];
1577 bool packet_matchbssid;
1578 bool is_cck;
1579 bool is_ht;
1580 bool packet_toself;
1581 bool packet_beacon; /*for rssi */
1582 char cck_adc_pwdb[4]; /*for rx path selection */
1583
1584 u8 packet_report_type;
1585
1586 u32 macid;
1587 u8 wake_match;
1588 u32 bt_rx_rssi_percentage;
1589 u32 macid_valid_entry[2];
1590 };
1591
1592
1593 struct rt_link_detect {
1594 /* count for roaming */
1595 u32 bcn_rx_inperiod;
1596 u32 roam_times;
1597
1598 u32 num_tx_in4period[4];
1599 u32 num_rx_in4period[4];
1600
1601 u32 num_tx_inperiod;
1602 u32 num_rx_inperiod;
1603
1604 bool busytraffic;
1605 bool tx_busy_traffic;
1606 bool rx_busy_traffic;
1607 bool higher_busytraffic;
1608 bool higher_busyrxtraffic;
1609
1610 u32 tidtx_in4period[MAX_TID_COUNT][4];
1611 u32 tidtx_inperiod[MAX_TID_COUNT];
1612 bool higher_busytxtraffic[MAX_TID_COUNT];
1613 };
1614
1615 struct rtl_tcb_desc {
1616 u8 packet_bw:1;
1617 u8 multicast:1;
1618 u8 broadcast:1;
1619
1620 u8 rts_stbc:1;
1621 u8 rts_enable:1;
1622 u8 cts_enable:1;
1623 u8 rts_use_shortpreamble:1;
1624 u8 rts_use_shortgi:1;
1625 u8 rts_sc:1;
1626 u8 rts_bw:1;
1627 u8 rts_rate;
1628
1629 u8 use_shortgi:1;
1630 u8 use_shortpreamble:1;
1631 u8 use_driver_rate:1;
1632 u8 disable_ratefallback:1;
1633
1634 u8 ratr_index;
1635 u8 mac_id;
1636 u8 hw_rate;
1637
1638 u8 last_inipkt:1;
1639 u8 cmd_or_init:1;
1640 u8 queue_index;
1641
1642 /* early mode */
1643 u8 empkt_num;
1644 /* The max value by HW */
1645 u32 empkt_len[10];
1646 bool btx_enable_sw_calc_duration;
1647 };
1648
1649 struct rtl_hal_ops {
1650 int (*init_sw_vars) (struct ieee80211_hw *hw);
1651 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1652 void (*read_chip_version)(struct ieee80211_hw *hw);
1653 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1654 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1655 u32 *p_inta, u32 *p_intb);
1656 int (*hw_init) (struct ieee80211_hw *hw);
1657 void (*hw_disable) (struct ieee80211_hw *hw);
1658 void (*hw_suspend) (struct ieee80211_hw *hw);
1659 void (*hw_resume) (struct ieee80211_hw *hw);
1660 void (*enable_interrupt) (struct ieee80211_hw *hw);
1661 void (*disable_interrupt) (struct ieee80211_hw *hw);
1662 int (*set_network_type) (struct ieee80211_hw *hw,
1663 enum nl80211_iftype type);
1664 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1665 bool check_bssid);
1666 void (*set_bw_mode) (struct ieee80211_hw *hw,
1667 enum nl80211_channel_type ch_type);
1668 u8(*switch_channel) (struct ieee80211_hw *hw);
1669 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1670 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1671 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1672 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1673 u32 add_msr, u32 rm_msr);
1674 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1675 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1676 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1677 struct ieee80211_sta *sta, u8 rssi_level);
1678 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1679 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1680 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1681 struct ieee80211_tx_info *info,
1682 struct ieee80211_sta *sta,
1683 struct sk_buff *skb, u8 hw_queue,
1684 struct rtl_tcb_desc *ptcb_desc);
1685 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1686 u32 buffer_len, bool bIsPsPoll);
1687 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1688 bool firstseg, bool lastseg,
1689 struct sk_buff *skb);
1690 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1691 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1692 struct rtl_stats *stats,
1693 struct ieee80211_rx_status *rx_status,
1694 u8 *pdesc, struct sk_buff *skb);
1695 void (*set_channel_access) (struct ieee80211_hw *hw);
1696 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1697 void (*dm_watchdog) (struct ieee80211_hw *hw);
1698 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1699 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1700 enum rf_pwrstate rfpwr_state);
1701 void (*led_control) (struct ieee80211_hw *hw,
1702 enum led_ctl_mode ledaction);
1703 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1704 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1705 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1706 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1707 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1708 u8 *macaddr, bool is_group, u8 enc_algo,
1709 bool is_wepkey, bool clear_all);
1710 void (*init_sw_leds) (struct ieee80211_hw *hw);
1711 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1712 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1713 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1714 u32 data);
1715 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1716 u32 regaddr, u32 bitmask);
1717 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1718 u32 regaddr, u32 bitmask, u32 data);
1719 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1720 bool allow_all_da, bool write_into_reg);
1721 void (*linked_set_reg) (struct ieee80211_hw *hw);
1722 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
1723 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1724 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1725 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1726 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1727 u8 *powerlevel);
1728 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1729 u8 *ppowerlevel, u8 channel);
1730 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1731 u8 configtype);
1732 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1733 u8 configtype);
1734 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1735 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1736 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1737 void (*c2h_command_handle) (struct ieee80211_hw *hw);
1738 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1739 bool mstate);
1740 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
1741 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
1742 u32 cmd_len, u8 *p_cmdbuffer);
1743 };
1744
1745 struct rtl_intf_ops {
1746 /*com */
1747 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1748 int (*adapter_start) (struct ieee80211_hw *hw);
1749 void (*adapter_stop) (struct ieee80211_hw *hw);
1750 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1751 struct rtl_priv **buddy_priv);
1752
1753 int (*adapter_tx) (struct ieee80211_hw *hw,
1754 struct ieee80211_sta *sta,
1755 struct sk_buff *skb,
1756 struct rtl_tcb_desc *ptcb_desc);
1757 void (*flush)(struct ieee80211_hw *hw, bool drop);
1758 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1759 bool (*waitq_insert) (struct ieee80211_hw *hw,
1760 struct ieee80211_sta *sta,
1761 struct sk_buff *skb);
1762
1763 /*pci */
1764 void (*disable_aspm) (struct ieee80211_hw *hw);
1765 void (*enable_aspm) (struct ieee80211_hw *hw);
1766
1767 /*usb */
1768 };
1769
1770 struct rtl_mod_params {
1771 /* default: 0 = using hardware encryption */
1772 bool sw_crypto;
1773
1774 /* default: 0 = DBG_EMERG (0)*/
1775 int debug;
1776
1777 /* default: 1 = using no linked power save */
1778 bool inactiveps;
1779
1780 /* default: 1 = using linked sw power save */
1781 bool swctrl_lps;
1782
1783 /* default: 1 = using linked fw power save */
1784 bool fwctrl_lps;
1785 };
1786
1787 struct rtl_hal_usbint_cfg {
1788 /* data - rx */
1789 u32 in_ep_num;
1790 u32 rx_urb_num;
1791 u32 rx_max_size;
1792
1793 /* op - rx */
1794 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1795 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1796 struct sk_buff_head *);
1797
1798 /* tx */
1799 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1800 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1801 struct sk_buff *);
1802 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1803 struct sk_buff_head *);
1804
1805 /* endpoint mapping */
1806 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1807 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1808 };
1809
1810 struct rtl_hal_cfg {
1811 u8 bar_id;
1812 bool write_readback;
1813 char *name;
1814 char *fw_name;
1815 char *alt_fw_name;
1816 struct rtl_hal_ops *ops;
1817 struct rtl_mod_params *mod_params;
1818 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1819
1820 /*this map used for some registers or vars
1821 defined int HAL but used in MAIN */
1822 u32 maps[RTL_VAR_MAP_MAX];
1823
1824 };
1825
1826 struct rtl_locks {
1827 /* mutex */
1828 struct mutex conf_mutex;
1829 struct mutex ps_mutex;
1830
1831 /*spin lock */
1832 spinlock_t ips_lock;
1833 spinlock_t irq_th_lock;
1834 spinlock_t irq_pci_lock;
1835 spinlock_t tx_lock;
1836 spinlock_t h2c_lock;
1837 spinlock_t rf_ps_lock;
1838 spinlock_t rf_lock;
1839 spinlock_t lps_lock;
1840 spinlock_t waitq_lock;
1841 spinlock_t entry_list_lock;
1842 spinlock_t usb_lock;
1843
1844 /*FW clock change */
1845 spinlock_t fw_ps_lock;
1846
1847 /*Dual mac*/
1848 spinlock_t cck_and_rw_pagea_lock;
1849
1850 /*Easy concurrent*/
1851 spinlock_t check_sendpkt_lock;
1852 };
1853
1854 struct rtl_works {
1855 struct ieee80211_hw *hw;
1856
1857 /*timer */
1858 struct timer_list watchdog_timer;
1859 struct timer_list dualmac_easyconcurrent_retrytimer;
1860 struct timer_list fw_clockoff_timer;
1861 struct timer_list fast_antenna_training_timer;
1862 /*task */
1863 struct tasklet_struct irq_tasklet;
1864 struct tasklet_struct irq_prepare_bcn_tasklet;
1865
1866 /*work queue */
1867 struct workqueue_struct *rtl_wq;
1868 struct delayed_work watchdog_wq;
1869 struct delayed_work ips_nic_off_wq;
1870
1871 /* For SW LPS */
1872 struct delayed_work ps_work;
1873 struct delayed_work ps_rfon_wq;
1874 struct delayed_work fwevt_wq;
1875
1876 struct work_struct lps_change_work;
1877 struct work_struct fill_h2c_cmd;
1878 };
1879
1880 struct rtl_debug {
1881 u32 dbgp_type[DBGP_TYPE_MAX];
1882 int global_debuglevel;
1883 u64 global_debugcomponents;
1884
1885 /* add for proc debug */
1886 struct proc_dir_entry *proc_dir;
1887 char proc_name[20];
1888 };
1889
1890 #define MIMO_PS_STATIC 0
1891 #define MIMO_PS_DYNAMIC 1
1892 #define MIMO_PS_NOLIMIT 3
1893
1894 struct rtl_dualmac_easy_concurrent_ctl {
1895 enum band_type currentbandtype_backfordmdp;
1896 bool close_bbandrf_for_dmsp;
1897 bool change_to_dmdp;
1898 bool change_to_dmsp;
1899 bool switch_in_process;
1900 };
1901
1902 struct rtl_dmsp_ctl {
1903 bool activescan_for_slaveofdmsp;
1904 bool scan_for_anothermac_fordmsp;
1905 bool scan_for_itself_fordmsp;
1906 bool writedig_for_anothermacofdmsp;
1907 u32 curdigvalue_for_anothermacofdmsp;
1908 bool changecckpdstate_for_anothermacofdmsp;
1909 u8 curcckpdstate_for_anothermacofdmsp;
1910 bool changetxhighpowerlvl_for_anothermacofdmsp;
1911 u8 curtxhighlvl_for_anothermacofdmsp;
1912 long rssivalmin_for_anothermacofdmsp;
1913 };
1914
1915 struct ps_t {
1916 u8 pre_ccastate;
1917 u8 cur_ccasate;
1918 u8 pre_rfstate;
1919 u8 cur_rfstate;
1920 long rssi_val_min;
1921 };
1922
1923 struct dig_t {
1924 u32 rssi_lowthresh;
1925 u32 rssi_highthresh;
1926 u32 fa_lowthresh;
1927 u32 fa_highthresh;
1928 long last_min_undec_pwdb_for_dm;
1929 long rssi_highpower_lowthresh;
1930 long rssi_highpower_highthresh;
1931 u32 recover_cnt;
1932 u32 pre_igvalue;
1933 u32 cur_igvalue;
1934 long rssi_val;
1935 u8 dig_enable_flag;
1936 u8 dig_ext_port_stage;
1937 u8 dig_algorithm;
1938 u8 dig_twoport_algorithm;
1939 u8 dig_dbgmode;
1940 u8 dig_slgorithm_switch;
1941 u8 cursta_cstate;
1942 u8 presta_cstate;
1943 u8 curmultista_cstate;
1944 char back_val;
1945 char back_range_max;
1946 char back_range_min;
1947 u8 rx_gain_max;
1948 u8 rx_gain_min;
1949 u8 min_undec_pwdb_for_dm;
1950 u8 rssi_val_min;
1951 u8 pre_cck_cca_thres;
1952 u8 cur_cck_cca_thres;
1953 u8 pre_cck_pd_state;
1954 u8 cur_cck_pd_state;
1955 u8 pre_cck_fa_state;
1956 u8 cur_cck_fa_state;
1957 u8 pre_ccastate;
1958 u8 cur_ccasate;
1959 u8 large_fa_hit;
1960 u8 dig_dynamic_min;
1961 u8 forbidden_igi;
1962 u8 dig_state;
1963 u8 dig_highpwrstate;
1964 u8 cur_sta_cstate;
1965 u8 pre_sta_cstate;
1966 u8 cur_ap_cstate;
1967 u8 pre_ap_cstate;
1968 u8 cur_pd_thstate;
1969 u8 pre_pd_thstate;
1970 u8 cur_cs_ratiostate;
1971 u8 pre_cs_ratiostate;
1972 u8 backoff_enable_flag;
1973 char backoffval_range_max;
1974 char backoffval_range_min;
1975 u8 dig_min_0;
1976 u8 dig_min_1;
1977 bool media_connect_0;
1978 bool media_connect_1;
1979
1980 u32 antdiv_rssi_max;
1981 u32 rssi_max;
1982 };
1983
1984 struct rtl_global_var {
1985 /* from this list we can get
1986 * other adapter's rtl_priv */
1987 struct list_head glb_priv_list;
1988 spinlock_t glb_list_lock;
1989 };
1990
1991 struct rtl_priv {
1992 struct ieee80211_hw *hw;
1993 struct completion firmware_loading_complete;
1994 struct list_head list;
1995 struct rtl_priv *buddy_priv;
1996 struct rtl_global_var *glb_var;
1997 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
1998 struct rtl_dmsp_ctl dmsp_ctl;
1999 struct rtl_locks locks;
2000 struct rtl_works works;
2001 struct rtl_mac mac80211;
2002 struct rtl_hal rtlhal;
2003 struct rtl_regulatory regd;
2004 struct rtl_rfkill rfkill;
2005 struct rtl_io io;
2006 struct rtl_phy phy;
2007 struct rtl_dm dm;
2008 struct rtl_security sec;
2009 struct rtl_efuse efuse;
2010
2011 struct rtl_ps_ctl psc;
2012 struct rate_adaptive ra;
2013 struct wireless_stats stats;
2014 struct rt_link_detect link_info;
2015 struct false_alarm_statistics falsealm_cnt;
2016
2017 struct rtl_rate_priv *rate_priv;
2018
2019 /* sta entry list for ap adhoc or mesh */
2020 struct list_head entry_list;
2021
2022 struct rtl_debug dbg;
2023 int max_fw_size;
2024
2025 /*
2026 *hal_cfg : for diff cards
2027 *intf_ops : for diff interrface usb/pcie
2028 */
2029 struct rtl_hal_cfg *cfg;
2030 struct rtl_intf_ops *intf_ops;
2031
2032 /*this var will be set by set_bit,
2033 and was used to indicate status of
2034 interface or hardware */
2035 unsigned long status;
2036
2037 /* tables for dm */
2038 struct dig_t dm_digtable;
2039 struct ps_t dm_pstable;
2040
2041 u32 reg_874;
2042 u32 reg_c70;
2043 u32 reg_85c;
2044 u32 reg_a74;
2045 bool reg_init; /* true if regs saved */
2046 bool bt_operation_on;
2047 __le32 *usb_data;
2048 int usb_data_index;
2049 bool initialized;
2050 bool enter_ps; /* true when entering PS */
2051 u8 rate_mask[5];
2052
2053 /*This must be the last item so
2054 that it points to the data allocated
2055 beyond this structure like:
2056 rtl_pci_priv or rtl_usb_priv */
2057 u8 priv[0] __aligned(sizeof(void *));
2058 };
2059
2060 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2061 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2062 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2063 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2064 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2065
2066
2067 /***************************************
2068 Bluetooth Co-existence Related
2069 ****************************************/
2070
2071 enum bt_ant_num {
2072 ANT_X2 = 0,
2073 ANT_X1 = 1,
2074 };
2075
2076 enum bt_co_type {
2077 BT_2WIRE = 0,
2078 BT_ISSC_3WIRE = 1,
2079 BT_ACCEL = 2,
2080 BT_CSR_BC4 = 3,
2081 BT_CSR_BC8 = 4,
2082 BT_RTL8756 = 5,
2083 BT_RTL8723A = 6,
2084 };
2085
2086 enum bt_cur_state {
2087 BT_OFF = 0,
2088 BT_ON = 1,
2089 };
2090
2091 enum bt_service_type {
2092 BT_SCO = 0,
2093 BT_A2DP = 1,
2094 BT_HID = 2,
2095 BT_HID_IDLE = 3,
2096 BT_SCAN = 4,
2097 BT_IDLE = 5,
2098 BT_OTHER_ACTION = 6,
2099 BT_BUSY = 7,
2100 BT_OTHERBUSY = 8,
2101 BT_PAN = 9,
2102 };
2103
2104 enum bt_radio_shared {
2105 BT_RADIO_SHARED = 0,
2106 BT_RADIO_INDIVIDUAL = 1,
2107 };
2108
2109 struct bt_coexist_info {
2110
2111 /* EEPROM BT info. */
2112 u8 eeprom_bt_coexist;
2113 u8 eeprom_bt_type;
2114 u8 eeprom_bt_ant_num;
2115 u8 eeprom_bt_ant_isol;
2116 u8 eeprom_bt_radio_shared;
2117
2118 u8 bt_coexistence;
2119 u8 bt_ant_num;
2120 u8 bt_coexist_type;
2121 u8 bt_state;
2122 u8 bt_cur_state; /* 0:on, 1:off */
2123 u8 bt_ant_isolation; /* 0:good, 1:bad */
2124 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2125 u8 bt_service;
2126 u8 bt_radio_shared_type;
2127 u8 bt_rfreg_origin_1e;
2128 u8 bt_rfreg_origin_1f;
2129 u8 bt_rssi_state;
2130 u32 ratio_tx;
2131 u32 ratio_pri;
2132 u32 bt_edca_ul;
2133 u32 bt_edca_dl;
2134
2135 bool init_set;
2136 bool bt_busy_traffic;
2137 bool bt_traffic_mode_set;
2138 bool bt_non_traffic_mode_set;
2139
2140 bool fw_coexist_all_off;
2141 bool sw_coexist_all_off;
2142 bool hw_coexist_all_off;
2143 u32 cstate;
2144 u32 previous_state;
2145 u32 cstate_h;
2146 u32 previous_state_h;
2147
2148 u8 bt_pre_rssi_state;
2149 u8 bt_pre_rssi_state1;
2150
2151 u8 reg_bt_iso;
2152 u8 reg_bt_sco;
2153 bool balance_on;
2154 u8 bt_active_zero_cnt;
2155 bool cur_bt_disabled;
2156 bool pre_bt_disabled;
2157
2158 u8 bt_profile_case;
2159 u8 bt_profile_action;
2160 bool bt_busy;
2161 bool hold_for_bt_operation;
2162 u8 lps_counter;
2163 };
2164
2165
2166 /****************************************
2167 mem access macro define start
2168 Call endian free function when
2169 1. Read/write packet content.
2170 2. Before write integer to IO.
2171 3. After read integer from IO.
2172 ****************************************/
2173 /* Convert little data endian to host ordering */
2174 #define EF1BYTE(_val) \
2175 ((u8)(_val))
2176 #define EF2BYTE(_val) \
2177 (le16_to_cpu(_val))
2178 #define EF4BYTE(_val) \
2179 (le32_to_cpu(_val))
2180
2181 /* Read data from memory */
2182 #define READEF1BYTE(_ptr) \
2183 EF1BYTE(*((u8 *)(_ptr)))
2184 /* Read le16 data from memory and convert to host ordering */
2185 #define READEF2BYTE(_ptr) \
2186 EF2BYTE(*(_ptr))
2187 #define READEF4BYTE(_ptr) \
2188 EF4BYTE(*(_ptr))
2189
2190 /* Write data to memory */
2191 #define WRITEEF1BYTE(_ptr, _val) \
2192 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2193 /* Write le16 data to memory in host ordering */
2194 #define WRITEEF2BYTE(_ptr, _val) \
2195 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2196 #define WRITEEF4BYTE(_ptr, _val) \
2197 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2198
2199 /* Create a bit mask
2200 * Examples:
2201 * BIT_LEN_MASK_32(0) => 0x00000000
2202 * BIT_LEN_MASK_32(1) => 0x00000001
2203 * BIT_LEN_MASK_32(2) => 0x00000003
2204 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2205 */
2206 #define BIT_LEN_MASK_32(__bitlen) \
2207 (0xFFFFFFFF >> (32 - (__bitlen)))
2208 #define BIT_LEN_MASK_16(__bitlen) \
2209 (0xFFFF >> (16 - (__bitlen)))
2210 #define BIT_LEN_MASK_8(__bitlen) \
2211 (0xFF >> (8 - (__bitlen)))
2212
2213 /* Create an offset bit mask
2214 * Examples:
2215 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2216 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2217 */
2218 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2219 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2220 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2221 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2222 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2223 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2224
2225 /*Description:
2226 * Return 4-byte value in host byte ordering from
2227 * 4-byte pointer in little-endian system.
2228 */
2229 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2230 (EF4BYTE(*((__le32 *)(__pstart))))
2231 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2232 (EF2BYTE(*((__le16 *)(__pstart))))
2233 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2234 (EF1BYTE(*((u8 *)(__pstart))))
2235
2236 /*Description:
2237 Translate subfield (continuous bits in little-endian) of 4-byte
2238 value to host byte ordering.*/
2239 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2240 ( \
2241 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2242 BIT_LEN_MASK_32(__bitlen) \
2243 )
2244 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2245 ( \
2246 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2247 BIT_LEN_MASK_16(__bitlen) \
2248 )
2249 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2250 ( \
2251 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2252 BIT_LEN_MASK_8(__bitlen) \
2253 )
2254
2255 /* Description:
2256 * Mask subfield (continuous bits in little-endian) of 4-byte value
2257 * and return the result in 4-byte value in host byte ordering.
2258 */
2259 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2260 ( \
2261 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2262 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2263 )
2264 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2265 ( \
2266 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2267 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2268 )
2269 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2270 ( \
2271 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2272 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2273 )
2274
2275 /* Description:
2276 * Set subfield of little-endian 4-byte value to specified value.
2277 */
2278 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2279 *((u32 *)(__pstart)) = \
2280 ( \
2281 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2282 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2283 );
2284 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2285 *((u16 *)(__pstart)) = \
2286 ( \
2287 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2288 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2289 );
2290 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2291 *((u8 *)(__pstart)) = EF1BYTE \
2292 ( \
2293 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2294 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2295 );
2296
2297 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2298 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2299
2300 /****************************************
2301 mem access macro define end
2302 ****************************************/
2303
2304 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2305
2306 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2307 #define RTL_WATCH_DOG_TIME 2000
2308 #define MSECS(t) msecs_to_jiffies(t)
2309 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2310 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2311 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2312 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2313 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2314
2315 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2316 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2317 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2318 /*NIC halt, re-initialize hw parameters*/
2319 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2320 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2321 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2322 /*Always enable ASPM and Clock Req in initialization.*/
2323 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2324 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2325 #define RT_PS_LEVEL_ASPM BIT(7)
2326 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2327 #define RT_RF_LPS_DISALBE_2R BIT(30)
2328 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2329 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2330 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2331 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2332 (ppsc->cur_ps_level &= (~(_ps_flg)))
2333 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2334 (ppsc->cur_ps_level |= _ps_flg)
2335
2336 #define container_of_dwork_rtl(x, y, z) \
2337 container_of(container_of(x, struct delayed_work, work), y, z)
2338
2339 #define FILL_OCTET_STRING(_os, _octet, _len) \
2340 (_os).octet = (u8 *)(_octet); \
2341 (_os).length = (_len);
2342
2343 #define CP_MACADDR(des, src) \
2344 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2345 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2346 (des)[4] = (src)[4], (des)[5] = (src)[5])
2347
2348 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2349 {
2350 return rtlpriv->io.read8_sync(rtlpriv, addr);
2351 }
2352
2353 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2354 {
2355 return rtlpriv->io.read16_sync(rtlpriv, addr);
2356 }
2357
2358 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2359 {
2360 return rtlpriv->io.read32_sync(rtlpriv, addr);
2361 }
2362
2363 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2364 {
2365 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2366
2367 if (rtlpriv->cfg->write_readback)
2368 rtlpriv->io.read8_sync(rtlpriv, addr);
2369 }
2370
2371 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2372 {
2373 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2374
2375 if (rtlpriv->cfg->write_readback)
2376 rtlpriv->io.read16_sync(rtlpriv, addr);
2377 }
2378
2379 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2380 u32 addr, u32 val32)
2381 {
2382 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2383
2384 if (rtlpriv->cfg->write_readback)
2385 rtlpriv->io.read32_sync(rtlpriv, addr);
2386 }
2387
2388 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2389 u32 regaddr, u32 bitmask)
2390 {
2391 struct rtl_priv *rtlpriv = hw->priv;
2392
2393 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2394 }
2395
2396 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2397 u32 bitmask, u32 data)
2398 {
2399 struct rtl_priv *rtlpriv = hw->priv;
2400
2401 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2402 }
2403
2404 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2405 enum radio_path rfpath, u32 regaddr,
2406 u32 bitmask)
2407 {
2408 struct rtl_priv *rtlpriv = hw->priv;
2409
2410 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2411 }
2412
2413 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2414 enum radio_path rfpath, u32 regaddr,
2415 u32 bitmask, u32 data)
2416 {
2417 struct rtl_priv *rtlpriv = hw->priv;
2418
2419 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2420 }
2421
2422 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2423 {
2424 return (_HAL_STATE_STOP == rtlhal->state);
2425 }
2426
2427 static inline void set_hal_start(struct rtl_hal *rtlhal)
2428 {
2429 rtlhal->state = _HAL_STATE_START;
2430 }
2431
2432 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2433 {
2434 rtlhal->state = _HAL_STATE_STOP;
2435 }
2436
2437 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2438 {
2439 return rtlphy->rf_type;
2440 }
2441
2442 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2443 {
2444 return (struct ieee80211_hdr *)(skb->data);
2445 }
2446
2447 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2448 {
2449 return rtl_get_hdr(skb)->frame_control;
2450 }
2451
2452 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2453 {
2454 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2455 }
2456
2457 static inline u16 rtl_get_tid(struct sk_buff *skb)
2458 {
2459 return rtl_get_tid_h(rtl_get_hdr(skb));
2460 }
2461
2462 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2463 struct ieee80211_vif *vif,
2464 const u8 *bssid)
2465 {
2466 return ieee80211_find_sta(vif, bssid);
2467 }
2468
2469 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2470 u8 *mac_addr)
2471 {
2472 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2473 return ieee80211_find_sta(mac->vif, mac_addr);
2474 }
2475
2476 #endif
Linux with added FPC-III support