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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / pci / access.c
blob6bc9b12ba42a67312e61749983b142081058f5e3
1 #include <linux/delay.h>
2 #include <linux/pci.h>
3 #include <linux/module.h>
4 #include <linux/sched.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
8
9 #include "pci.h"
10
11 /*
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
14 */
15
16 DEFINE_RAW_SPINLOCK(pci_lock);
17
18 /*
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
21 * by pci_dev->ops.
22 */
23
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
27
28 #define PCI_OP_READ(size,type,len) \
29 int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
31 { \
32 int res; \
33 unsigned long flags; \
34 u32 data = 0; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
36 raw_spin_lock_irqsave(&pci_lock, flags); \
37 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
39 raw_spin_unlock_irqrestore(&pci_lock, flags); \
40 return res; \
41 }
42
43 #define PCI_OP_WRITE(size,type,len) \
44 int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
46 { \
47 int res; \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
50 raw_spin_lock_irqsave(&pci_lock, flags); \
51 res = bus->ops->write(bus, devfn, pos, len, value); \
52 raw_spin_unlock_irqrestore(&pci_lock, flags); \
53 return res; \
54 }
55
56 PCI_OP_READ(byte, u8, 1)
57 PCI_OP_READ(word, u16, 2)
58 PCI_OP_READ(dword, u32, 4)
59 PCI_OP_WRITE(byte, u8, 1)
60 PCI_OP_WRITE(word, u16, 2)
61 PCI_OP_WRITE(dword, u32, 4)
62
63 EXPORT_SYMBOL(pci_bus_read_config_byte);
64 EXPORT_SYMBOL(pci_bus_read_config_word);
65 EXPORT_SYMBOL(pci_bus_read_config_dword);
66 EXPORT_SYMBOL(pci_bus_write_config_byte);
67 EXPORT_SYMBOL(pci_bus_write_config_word);
68 EXPORT_SYMBOL(pci_bus_write_config_dword);
69
70 /**
71 * pci_bus_set_ops - Set raw operations of pci bus
72 * @bus: pci bus struct
73 * @ops: new raw operations
74 *
75 * Return previous raw operations
76 */
77 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
78 {
79 struct pci_ops *old_ops;
80 unsigned long flags;
81
82 raw_spin_lock_irqsave(&pci_lock, flags);
83 old_ops = bus->ops;
84 bus->ops = ops;
85 raw_spin_unlock_irqrestore(&pci_lock, flags);
86 return old_ops;
87 }
88 EXPORT_SYMBOL(pci_bus_set_ops);
89
90 /**
91 * pci_read_vpd - Read one entry from Vital Product Data
92 * @dev: pci device struct
93 * @pos: offset in vpd space
94 * @count: number of bytes to read
95 * @buf: pointer to where to store result
96 *
97 */
98 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
99 {
100 if (!dev->vpd || !dev->vpd->ops)
101 return -ENODEV;
102 return dev->vpd->ops->read(dev, pos, count, buf);
103 }
104 EXPORT_SYMBOL(pci_read_vpd);
105
106 /**
107 * pci_write_vpd - Write entry to Vital Product Data
108 * @dev: pci device struct
109 * @pos: offset in vpd space
110 * @count: number of bytes to write
111 * @buf: buffer containing write data
112 *
113 */
114 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
115 {
116 if (!dev->vpd || !dev->vpd->ops)
117 return -ENODEV;
118 return dev->vpd->ops->write(dev, pos, count, buf);
119 }
120 EXPORT_SYMBOL(pci_write_vpd);
121
122 /*
123 * The following routines are to prevent the user from accessing PCI config
124 * space when it's unsafe to do so. Some devices require this during BIST and
125 * we're required to prevent it during D-state transitions.
126 *
127 * We have a bit per device to indicate it's blocked and a global wait queue
128 * for callers to sleep on until devices are unblocked.
129 */
130 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
131
132 static noinline void pci_wait_cfg(struct pci_dev *dev)
133 {
134 DECLARE_WAITQUEUE(wait, current);
135
136 __add_wait_queue(&pci_cfg_wait, &wait);
137 do {
138 set_current_state(TASK_UNINTERRUPTIBLE);
139 raw_spin_unlock_irq(&pci_lock);
140 schedule();
141 raw_spin_lock_irq(&pci_lock);
142 } while (dev->block_cfg_access);
143 __remove_wait_queue(&pci_cfg_wait, &wait);
144 }
145
146 /* Returns 0 on success, negative values indicate error. */
147 #define PCI_USER_READ_CONFIG(size,type) \
148 int pci_user_read_config_##size \
149 (struct pci_dev *dev, int pos, type *val) \
150 { \
151 int ret = 0; \
152 u32 data = -1; \
153 if (PCI_##size##_BAD) \
154 return -EINVAL; \
155 raw_spin_lock_irq(&pci_lock); \
156 if (unlikely(dev->block_cfg_access)) \
157 pci_wait_cfg(dev); \
158 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
159 pos, sizeof(type), &data); \
160 raw_spin_unlock_irq(&pci_lock); \
161 *val = (type)data; \
162 if (ret > 0) \
163 ret = -EINVAL; \
164 return ret; \
165 } \
166 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
167
168 /* Returns 0 on success, negative values indicate error. */
169 #define PCI_USER_WRITE_CONFIG(size,type) \
170 int pci_user_write_config_##size \
171 (struct pci_dev *dev, int pos, type val) \
172 { \
173 int ret = -EIO; \
174 if (PCI_##size##_BAD) \
175 return -EINVAL; \
176 raw_spin_lock_irq(&pci_lock); \
177 if (unlikely(dev->block_cfg_access)) \
178 pci_wait_cfg(dev); \
179 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
180 pos, sizeof(type), val); \
181 raw_spin_unlock_irq(&pci_lock); \
182 if (ret > 0) \
183 ret = -EINVAL; \
184 return ret; \
185 } \
186 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
187
188 PCI_USER_READ_CONFIG(byte, u8)
189 PCI_USER_READ_CONFIG(word, u16)
190 PCI_USER_READ_CONFIG(dword, u32)
191 PCI_USER_WRITE_CONFIG(byte, u8)
192 PCI_USER_WRITE_CONFIG(word, u16)
193 PCI_USER_WRITE_CONFIG(dword, u32)
194
195 /* VPD access through PCI 2.2+ VPD capability */
196
197 #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
198
199 struct pci_vpd_pci22 {
200 struct pci_vpd base;
201 struct mutex lock;
202 u16 flag;
203 bool busy;
204 u8 cap;
205 };
206
207 /*
208 * Wait for last operation to complete.
209 * This code has to spin since there is no other notification from the PCI
210 * hardware. Since the VPD is often implemented by serial attachment to an
211 * EEPROM, it may take many milliseconds to complete.
212 *
213 * Returns 0 on success, negative values indicate error.
214 */
215 static int pci_vpd_pci22_wait(struct pci_dev *dev)
216 {
217 struct pci_vpd_pci22 *vpd =
218 container_of(dev->vpd, struct pci_vpd_pci22, base);
219 unsigned long timeout = jiffies + HZ/20 + 2;
220 u16 status;
221 int ret;
222
223 if (!vpd->busy)
224 return 0;
225
226 for (;;) {
227 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
228 &status);
229 if (ret < 0)
230 return ret;
231
232 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
233 vpd->busy = false;
234 return 0;
235 }
236
237 if (time_after(jiffies, timeout)) {
238 dev_printk(KERN_DEBUG, &dev->dev,
239 "vpd r/w failed. This is likely a firmware "
240 "bug on this device. Contact the card "
241 "vendor for a firmware update.");
242 return -ETIMEDOUT;
243 }
244 if (fatal_signal_pending(current))
245 return -EINTR;
246 if (!cond_resched())
247 udelay(10);
248 }
249 }
250
251 static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
252 void *arg)
253 {
254 struct pci_vpd_pci22 *vpd =
255 container_of(dev->vpd, struct pci_vpd_pci22, base);
256 int ret;
257 loff_t end = pos + count;
258 u8 *buf = arg;
259
260 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
261 return -EINVAL;
262
263 if (mutex_lock_killable(&vpd->lock))
264 return -EINTR;
265
266 ret = pci_vpd_pci22_wait(dev);
267 if (ret < 0)
268 goto out;
269
270 while (pos < end) {
271 u32 val;
272 unsigned int i, skip;
273
274 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
275 pos & ~3);
276 if (ret < 0)
277 break;
278 vpd->busy = true;
279 vpd->flag = PCI_VPD_ADDR_F;
280 ret = pci_vpd_pci22_wait(dev);
281 if (ret < 0)
282 break;
283
284 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
285 if (ret < 0)
286 break;
287
288 skip = pos & 3;
289 for (i = 0; i < sizeof(u32); i++) {
290 if (i >= skip) {
291 *buf++ = val;
292 if (++pos == end)
293 break;
294 }
295 val >>= 8;
296 }
297 }
298 out:
299 mutex_unlock(&vpd->lock);
300 return ret ? ret : count;
301 }
302
303 static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
304 const void *arg)
305 {
306 struct pci_vpd_pci22 *vpd =
307 container_of(dev->vpd, struct pci_vpd_pci22, base);
308 const u8 *buf = arg;
309 loff_t end = pos + count;
310 int ret = 0;
311
312 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
313 return -EINVAL;
314
315 if (mutex_lock_killable(&vpd->lock))
316 return -EINTR;
317
318 ret = pci_vpd_pci22_wait(dev);
319 if (ret < 0)
320 goto out;
321
322 while (pos < end) {
323 u32 val;
324
325 val = *buf++;
326 val |= *buf++ << 8;
327 val |= *buf++ << 16;
328 val |= *buf++ << 24;
329
330 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
331 if (ret < 0)
332 break;
333 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
334 pos | PCI_VPD_ADDR_F);
335 if (ret < 0)
336 break;
337
338 vpd->busy = true;
339 vpd->flag = 0;
340 ret = pci_vpd_pci22_wait(dev);
341 if (ret < 0)
342 break;
343
344 pos += sizeof(u32);
345 }
346 out:
347 mutex_unlock(&vpd->lock);
348 return ret ? ret : count;
349 }
350
351 static void pci_vpd_pci22_release(struct pci_dev *dev)
352 {
353 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
354 }
355
356 static const struct pci_vpd_ops pci_vpd_pci22_ops = {
357 .read = pci_vpd_pci22_read,
358 .write = pci_vpd_pci22_write,
359 .release = pci_vpd_pci22_release,
360 };
361
362 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
363 void *arg)
364 {
365 struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
366 ssize_t ret;
367
368 if (!tdev)
369 return -ENODEV;
370
371 ret = pci_read_vpd(tdev, pos, count, arg);
372 pci_dev_put(tdev);
373 return ret;
374 }
375
376 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
377 const void *arg)
378 {
379 struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
380 ssize_t ret;
381
382 if (!tdev)
383 return -ENODEV;
384
385 ret = pci_write_vpd(tdev, pos, count, arg);
386 pci_dev_put(tdev);
387 return ret;
388 }
389
390 static const struct pci_vpd_ops pci_vpd_f0_ops = {
391 .read = pci_vpd_f0_read,
392 .write = pci_vpd_f0_write,
393 .release = pci_vpd_pci22_release,
394 };
395
396 static int pci_vpd_f0_dev_check(struct pci_dev *dev)
397 {
398 struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
399 int ret = 0;
400
401 if (!tdev)
402 return -ENODEV;
403 if (!tdev->vpd || !tdev->multifunction ||
404 dev->class != tdev->class || dev->vendor != tdev->vendor ||
405 dev->device != tdev->device)
406 ret = -ENODEV;
407
408 pci_dev_put(tdev);
409 return ret;
410 }
411
412 int pci_vpd_pci22_init(struct pci_dev *dev)
413 {
414 struct pci_vpd_pci22 *vpd;
415 u8 cap;
416
417 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
418 if (!cap)
419 return -ENODEV;
420 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
421 int ret = pci_vpd_f0_dev_check(dev);
422
423 if (ret)
424 return ret;
425 }
426 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
427 if (!vpd)
428 return -ENOMEM;
429
430 vpd->base.len = PCI_VPD_PCI22_SIZE;
431 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
432 vpd->base.ops = &pci_vpd_f0_ops;
433 else
434 vpd->base.ops = &pci_vpd_pci22_ops;
435 mutex_init(&vpd->lock);
436 vpd->cap = cap;
437 vpd->busy = false;
438 dev->vpd = &vpd->base;
439 return 0;
440 }
441
442 /**
443 * pci_vpd_truncate - Set available Vital Product Data size
444 * @dev: pci device struct
445 * @size: available memory in bytes
446 *
447 * Adjust size of available VPD area.
448 */
449 int pci_vpd_truncate(struct pci_dev *dev, size_t size)
450 {
451 if (!dev->vpd)
452 return -EINVAL;
453
454 /* limited by the access method */
455 if (size > dev->vpd->len)
456 return -EINVAL;
457
458 dev->vpd->len = size;
459 if (dev->vpd->attr)
460 dev->vpd->attr->size = size;
461
462 return 0;
463 }
464 EXPORT_SYMBOL(pci_vpd_truncate);
465
466 /**
467 * pci_cfg_access_lock - Lock PCI config reads/writes
468 * @dev: pci device struct
469 *
470 * When access is locked, any userspace reads or writes to config
471 * space and concurrent lock requests will sleep until access is
472 * allowed via pci_cfg_access_unlocked again.
473 */
474 void pci_cfg_access_lock(struct pci_dev *dev)
475 {
476 might_sleep();
477
478 raw_spin_lock_irq(&pci_lock);
479 if (dev->block_cfg_access)
480 pci_wait_cfg(dev);
481 dev->block_cfg_access = 1;
482 raw_spin_unlock_irq(&pci_lock);
483 }
484 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
485
486 /**
487 * pci_cfg_access_trylock - try to lock PCI config reads/writes
488 * @dev: pci device struct
489 *
490 * Same as pci_cfg_access_lock, but will return 0 if access is
491 * already locked, 1 otherwise. This function can be used from
492 * atomic contexts.
493 */
494 bool pci_cfg_access_trylock(struct pci_dev *dev)
495 {
496 unsigned long flags;
497 bool locked = true;
498
499 raw_spin_lock_irqsave(&pci_lock, flags);
500 if (dev->block_cfg_access)
501 locked = false;
502 else
503 dev->block_cfg_access = 1;
504 raw_spin_unlock_irqrestore(&pci_lock, flags);
505
506 return locked;
507 }
508 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
509
510 /**
511 * pci_cfg_access_unlock - Unlock PCI config reads/writes
512 * @dev: pci device struct
513 *
514 * This function allows PCI config accesses to resume.
515 */
516 void pci_cfg_access_unlock(struct pci_dev *dev)
517 {
518 unsigned long flags;
519
520 raw_spin_lock_irqsave(&pci_lock, flags);
521
522 /* This indicates a problem in the caller, but we don't need
523 * to kill them, unlike a double-block above. */
524 WARN_ON(!dev->block_cfg_access);
525
526 dev->block_cfg_access = 0;
527 wake_up_all(&pci_cfg_wait);
528 raw_spin_unlock_irqrestore(&pci_lock, flags);
529 }
530 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
531
532 static inline int pcie_cap_version(const struct pci_dev *dev)
533 {
534 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
535 }
536
537 static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
538 {
539 int type = pci_pcie_type(dev);
540
541 return type == PCI_EXP_TYPE_ENDPOINT ||
542 type == PCI_EXP_TYPE_LEG_END ||
543 type == PCI_EXP_TYPE_ROOT_PORT ||
544 type == PCI_EXP_TYPE_UPSTREAM ||
545 type == PCI_EXP_TYPE_DOWNSTREAM ||
546 type == PCI_EXP_TYPE_PCI_BRIDGE ||
547 type == PCI_EXP_TYPE_PCIE_BRIDGE;
548 }
549
550 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
551 {
552 int type = pci_pcie_type(dev);
553
554 return (type == PCI_EXP_TYPE_ROOT_PORT ||
555 type == PCI_EXP_TYPE_DOWNSTREAM) &&
556 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
557 }
558
559 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
560 {
561 int type = pci_pcie_type(dev);
562
563 return type == PCI_EXP_TYPE_ROOT_PORT ||
564 type == PCI_EXP_TYPE_RC_EC;
565 }
566
567 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
568 {
569 if (!pci_is_pcie(dev))
570 return false;
571
572 switch (pos) {
573 case PCI_EXP_FLAGS:
574 return true;
575 case PCI_EXP_DEVCAP:
576 case PCI_EXP_DEVCTL:
577 case PCI_EXP_DEVSTA:
578 return true;
579 case PCI_EXP_LNKCAP:
580 case PCI_EXP_LNKCTL:
581 case PCI_EXP_LNKSTA:
582 return pcie_cap_has_lnkctl(dev);
583 case PCI_EXP_SLTCAP:
584 case PCI_EXP_SLTCTL:
585 case PCI_EXP_SLTSTA:
586 return pcie_cap_has_sltctl(dev);
587 case PCI_EXP_RTCTL:
588 case PCI_EXP_RTCAP:
589 case PCI_EXP_RTSTA:
590 return pcie_cap_has_rtctl(dev);
591 case PCI_EXP_DEVCAP2:
592 case PCI_EXP_DEVCTL2:
593 case PCI_EXP_LNKCAP2:
594 case PCI_EXP_LNKCTL2:
595 case PCI_EXP_LNKSTA2:
596 return pcie_cap_version(dev) > 1;
597 default:
598 return false;
599 }
600 }
601
602 /*
603 * Note that these accessor functions are only for the "PCI Express
604 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
605 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
606 */
607 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
608 {
609 int ret;
610
611 *val = 0;
612 if (pos & 1)
613 return -EINVAL;
614
615 if (pcie_capability_reg_implemented(dev, pos)) {
616 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
617 /*
618 * Reset *val to 0 if pci_read_config_word() fails, it may
619 * have been written as 0xFFFF if hardware error happens
620 * during pci_read_config_word().
621 */
622 if (ret)
623 *val = 0;
624 return ret;
625 }
626
627 /*
628 * For Functions that do not implement the Slot Capabilities,
629 * Slot Status, and Slot Control registers, these spaces must
630 * be hardwired to 0b, with the exception of the Presence Detect
631 * State bit in the Slot Status register of Downstream Ports,
632 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
633 */
634 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
635 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
636 *val = PCI_EXP_SLTSTA_PDS;
637 }
638
639 return 0;
640 }
641 EXPORT_SYMBOL(pcie_capability_read_word);
642
643 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
644 {
645 int ret;
646
647 *val = 0;
648 if (pos & 3)
649 return -EINVAL;
650
651 if (pcie_capability_reg_implemented(dev, pos)) {
652 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
653 /*
654 * Reset *val to 0 if pci_read_config_dword() fails, it may
655 * have been written as 0xFFFFFFFF if hardware error happens
656 * during pci_read_config_dword().
657 */
658 if (ret)
659 *val = 0;
660 return ret;
661 }
662
663 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
664 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
665 *val = PCI_EXP_SLTSTA_PDS;
666 }
667
668 return 0;
669 }
670 EXPORT_SYMBOL(pcie_capability_read_dword);
671
672 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
673 {
674 if (pos & 1)
675 return -EINVAL;
676
677 if (!pcie_capability_reg_implemented(dev, pos))
678 return 0;
679
680 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
681 }
682 EXPORT_SYMBOL(pcie_capability_write_word);
683
684 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
685 {
686 if (pos & 3)
687 return -EINVAL;
688
689 if (!pcie_capability_reg_implemented(dev, pos))
690 return 0;
691
692 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
693 }
694 EXPORT_SYMBOL(pcie_capability_write_dword);
695
696 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
697 u16 clear, u16 set)
698 {
699 int ret;
700 u16 val;
701
702 ret = pcie_capability_read_word(dev, pos, &val);
703 if (!ret) {
704 val &= ~clear;
705 val |= set;
706 ret = pcie_capability_write_word(dev, pos, val);
707 }
708
709 return ret;
710 }
711 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
712
713 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
714 u32 clear, u32 set)
715 {
716 int ret;
717 u32 val;
718
719 ret = pcie_capability_read_dword(dev, pos, &val);
720 if (!ret) {
721 val &= ~clear;
722 val |= set;
723 ret = pcie_capability_write_dword(dev, pos, val);
724 }
725
726 return ret;
727 }
728 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
Linux with added FPC-III support