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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / scsi / ipr.h
blob06b3b4bb29110be18ac3ff2be4c4deee625f0d86
1 /*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26 #ifndef _IPR_H
27 #define _IPR_H
28
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/blk-iopoll.h>
36 #include <scsi/scsi.h>
37 #include <scsi/scsi_cmnd.h>
38
39 /*
40 * Literals
41 */
42 #define IPR_DRIVER_VERSION "2.6.0"
43 #define IPR_DRIVER_DATE "(November 16, 2012)"
44
45 /*
46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
47 * ops per device for devices not running tagged command queuing.
48 * This can be adjusted at runtime through sysfs device attributes.
49 */
50 #define IPR_MAX_CMD_PER_LUN 6
51 #define IPR_MAX_CMD_PER_ATA_LUN 1
52
53 /*
54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
55 * ops the mid-layer can send to the adapter.
56 */
57 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
58
59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
60
61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
62 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
63
64 #define IPR_SUBS_DEV_ID_2780 0x0264
65 #define IPR_SUBS_DEV_ID_5702 0x0266
66 #define IPR_SUBS_DEV_ID_5703 0x0278
67 #define IPR_SUBS_DEV_ID_572E 0x028D
68 #define IPR_SUBS_DEV_ID_573E 0x02D3
69 #define IPR_SUBS_DEV_ID_573D 0x02D4
70 #define IPR_SUBS_DEV_ID_571A 0x02C0
71 #define IPR_SUBS_DEV_ID_571B 0x02BE
72 #define IPR_SUBS_DEV_ID_571E 0x02BF
73 #define IPR_SUBS_DEV_ID_571F 0x02D5
74 #define IPR_SUBS_DEV_ID_572A 0x02C1
75 #define IPR_SUBS_DEV_ID_572B 0x02C2
76 #define IPR_SUBS_DEV_ID_572F 0x02C3
77 #define IPR_SUBS_DEV_ID_574E 0x030A
78 #define IPR_SUBS_DEV_ID_575B 0x030D
79 #define IPR_SUBS_DEV_ID_575C 0x0338
80 #define IPR_SUBS_DEV_ID_57B3 0x033A
81 #define IPR_SUBS_DEV_ID_57B7 0x0360
82 #define IPR_SUBS_DEV_ID_57B8 0x02C2
83
84 #define IPR_SUBS_DEV_ID_57B4 0x033B
85 #define IPR_SUBS_DEV_ID_57B2 0x035F
86 #define IPR_SUBS_DEV_ID_57C0 0x0352
87 #define IPR_SUBS_DEV_ID_57C3 0x0353
88 #define IPR_SUBS_DEV_ID_57C4 0x0354
89 #define IPR_SUBS_DEV_ID_57C6 0x0357
90 #define IPR_SUBS_DEV_ID_57CC 0x035C
91
92 #define IPR_SUBS_DEV_ID_57B5 0x033C
93 #define IPR_SUBS_DEV_ID_57CE 0x035E
94 #define IPR_SUBS_DEV_ID_57B1 0x0355
95
96 #define IPR_SUBS_DEV_ID_574D 0x0356
97 #define IPR_SUBS_DEV_ID_57C8 0x035D
98
99 #define IPR_SUBS_DEV_ID_57D5 0x03FB
100 #define IPR_SUBS_DEV_ID_57D6 0x03FC
101 #define IPR_SUBS_DEV_ID_57D7 0x03FF
102 #define IPR_SUBS_DEV_ID_57D8 0x03FE
103 #define IPR_SUBS_DEV_ID_57D9 0x046D
104 #define IPR_SUBS_DEV_ID_57EB 0x0474
105 #define IPR_SUBS_DEV_ID_57EC 0x0475
106 #define IPR_SUBS_DEV_ID_57ED 0x0499
107 #define IPR_SUBS_DEV_ID_57EE 0x049A
108 #define IPR_SUBS_DEV_ID_57EF 0x049B
109 #define IPR_SUBS_DEV_ID_57F0 0x049C
110 #define IPR_SUBS_DEV_ID_2CCA 0x04C7
111 #define IPR_SUBS_DEV_ID_2CD2 0x04C8
112 #define IPR_SUBS_DEV_ID_2CCD 0x04C9
113 #define IPR_NAME "ipr"
114
115 /*
116 * Return codes
117 */
118 #define IPR_RC_JOB_CONTINUE 1
119 #define IPR_RC_JOB_RETURN 2
120
121 /*
122 * IOASCs
123 */
124 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
125 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
126 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
127 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
128 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
129 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
130 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
131 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
132 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
133 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
134 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
135 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
136 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
137 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
138 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
139
140 #define IPR_FIRST_DRIVER_IOASC 0x10000000
141 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
142 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
143
144 /* Driver data flags */
145 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
146 #define IPR_USE_PCI_WARM_RESET 0x00000002
147
148 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
149 #define IPR_NUM_LOG_HCAMS 2
150 #define IPR_NUM_CFG_CHG_HCAMS 2
151 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
152
153 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
154 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
155
156 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
157 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
158 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
159 #define IPR_VSET_BUS 0xff
160 #define IPR_IOA_BUS 0xff
161 #define IPR_IOA_TARGET 0xff
162 #define IPR_IOA_LUN 0xff
163 #define IPR_MAX_NUM_BUSES 16
164 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
165
166 #define IPR_NUM_RESET_RELOAD_RETRIES 3
167
168 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
169 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
170 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
171
172 #define IPR_MAX_COMMANDS 100
173 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
174 IPR_NUM_INTERNAL_CMD_BLKS)
175
176 #define IPR_MAX_PHYSICAL_DEVS 192
177 #define IPR_DEFAULT_SIS64_DEVS 1024
178 #define IPR_MAX_SIS64_DEVS 4096
179
180 #define IPR_MAX_SGLIST 64
181 #define IPR_IOA_MAX_SECTORS 32767
182 #define IPR_VSET_MAX_SECTORS 512
183 #define IPR_MAX_CDB_LEN 16
184 #define IPR_MAX_HRRQ_RETRIES 3
185
186 #define IPR_DEFAULT_BUS_WIDTH 16
187 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
188 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
189 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
190 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
191
192 #define IPR_IOA_RES_HANDLE 0xffffffff
193 #define IPR_INVALID_RES_HANDLE 0
194 #define IPR_IOA_RES_ADDR 0x00ffffff
195
196 /*
197 * Adapter Commands
198 */
199 #define IPR_QUERY_RSRC_STATE 0xC2
200 #define IPR_RESET_DEVICE 0xC3
201 #define IPR_RESET_TYPE_SELECT 0x80
202 #define IPR_LUN_RESET 0x40
203 #define IPR_TARGET_RESET 0x20
204 #define IPR_BUS_RESET 0x10
205 #define IPR_ATA_PHY_RESET 0x80
206 #define IPR_ID_HOST_RR_Q 0xC4
207 #define IPR_QUERY_IOA_CONFIG 0xC5
208 #define IPR_CANCEL_ALL_REQUESTS 0xCE
209 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
210 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
211 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
212 #define IPR_SET_SUPPORTED_DEVICES 0xFB
213 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
214 #define IPR_IOA_SHUTDOWN 0xF7
215 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
216
217 /*
218 * Timeouts
219 */
220 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
221 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
222 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
223 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
224 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
225 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
226 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
227 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
228 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
229 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
230 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
231 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
232 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
233 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
234 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
235 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
236 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
237 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
238 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
239 #define IPR_DUMP_DELAY_SECONDS 4
240 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
241
242 /*
243 * SCSI Literals
244 */
245 #define IPR_VENDOR_ID_LEN 8
246 #define IPR_PROD_ID_LEN 16
247 #define IPR_SERIAL_NUM_LEN 8
248
249 /*
250 * Hardware literals
251 */
252 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
253 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
254 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
255 #define IPR_GET_FMT2_BAR_SEL(mbx) \
256 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
257 #define IPR_SDT_FMT2_BAR0_SEL 0x0
258 #define IPR_SDT_FMT2_BAR1_SEL 0x1
259 #define IPR_SDT_FMT2_BAR2_SEL 0x2
260 #define IPR_SDT_FMT2_BAR3_SEL 0x3
261 #define IPR_SDT_FMT2_BAR4_SEL 0x4
262 #define IPR_SDT_FMT2_BAR5_SEL 0x5
263 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
264 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
265 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
266 #define IPR_DOORBELL 0x82800000
267 #define IPR_RUNTIME_RESET 0x40000000
268
269 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
270 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 30
271 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
272 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
273 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
274 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
275 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
276
277 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
278 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
279 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
280 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
281 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
282 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
283 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
284 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
285 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
286 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
287 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
288
289 #define IPR_PCII_ERROR_INTERRUPTS \
290 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
291 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
292
293 #define IPR_PCII_OPER_INTERRUPTS \
294 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
295
296 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
297 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
298 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
299
300 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
301 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
302
303 /*
304 * Dump literals
305 */
306 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
307 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024)
308 #define IPR_FMT2_NUM_SDT_ENTRIES 511
309 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
310 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
311 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
312
313 /*
314 * Misc literals
315 */
316 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
317 #define IPR_MAX_MSIX_VECTORS 0x5
318 #define IPR_MAX_HRRQ_NUM 0x10
319 #define IPR_INIT_HRRQ 0x0
320
321 /*
322 * Adapter interface types
323 */
324
325 struct ipr_res_addr {
326 u8 reserved;
327 u8 bus;
328 u8 target;
329 u8 lun;
330 #define IPR_GET_PHYS_LOC(res_addr) \
331 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
332 }__attribute__((packed, aligned (4)));
333
334 struct ipr_std_inq_vpids {
335 u8 vendor_id[IPR_VENDOR_ID_LEN];
336 u8 product_id[IPR_PROD_ID_LEN];
337 }__attribute__((packed));
338
339 struct ipr_vpd {
340 struct ipr_std_inq_vpids vpids;
341 u8 sn[IPR_SERIAL_NUM_LEN];
342 }__attribute__((packed));
343
344 struct ipr_ext_vpd {
345 struct ipr_vpd vpd;
346 __be32 wwid[2];
347 }__attribute__((packed));
348
349 struct ipr_ext_vpd64 {
350 struct ipr_vpd vpd;
351 __be32 wwid[4];
352 }__attribute__((packed));
353
354 struct ipr_std_inq_data {
355 u8 peri_qual_dev_type;
356 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
357 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
358
359 u8 removeable_medium_rsvd;
360 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
361
362 #define IPR_IS_DASD_DEVICE(std_inq) \
363 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
364 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
365
366 #define IPR_IS_SES_DEVICE(std_inq) \
367 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
368
369 u8 version;
370 u8 aen_naca_fmt;
371 u8 additional_len;
372 u8 sccs_rsvd;
373 u8 bq_enc_multi;
374 u8 sync_cmdq_flags;
375
376 struct ipr_std_inq_vpids vpids;
377
378 u8 ros_rsvd_ram_rsvd[4];
379
380 u8 serial_num[IPR_SERIAL_NUM_LEN];
381 }__attribute__ ((packed));
382
383 #define IPR_RES_TYPE_AF_DASD 0x00
384 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
385 #define IPR_RES_TYPE_VOLUME_SET 0x02
386 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
387 #define IPR_RES_TYPE_GENERIC_ATA 0x04
388 #define IPR_RES_TYPE_ARRAY 0x05
389 #define IPR_RES_TYPE_IOAFP 0xff
390
391 struct ipr_config_table_entry {
392 u8 proto;
393 #define IPR_PROTO_SATA 0x02
394 #define IPR_PROTO_SATA_ATAPI 0x03
395 #define IPR_PROTO_SAS_STP 0x06
396 #define IPR_PROTO_SAS_STP_ATAPI 0x07
397 u8 array_id;
398 u8 flags;
399 #define IPR_IS_IOA_RESOURCE 0x80
400 u8 rsvd_subtype;
401
402 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
403 #define IPR_QUEUE_FROZEN_MODEL 0
404 #define IPR_QUEUE_NACA_MODEL 1
405
406 struct ipr_res_addr res_addr;
407 __be32 res_handle;
408 __be32 lun_wwn[2];
409 struct ipr_std_inq_data std_inq_data;
410 }__attribute__ ((packed, aligned (4)));
411
412 struct ipr_config_table_entry64 {
413 u8 res_type;
414 u8 proto;
415 u8 vset_num;
416 u8 array_id;
417 __be16 flags;
418 __be16 res_flags;
419 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
420 __be32 res_handle;
421 u8 dev_id_type;
422 u8 reserved[3];
423 __be64 dev_id;
424 __be64 lun;
425 __be64 lun_wwn[2];
426 #define IPR_MAX_RES_PATH_LENGTH 48
427 __be64 res_path;
428 struct ipr_std_inq_data std_inq_data;
429 u8 reserved2[4];
430 __be64 reserved3[2];
431 u8 reserved4[8];
432 }__attribute__ ((packed, aligned (8)));
433
434 struct ipr_config_table_hdr {
435 u8 num_entries;
436 u8 flags;
437 #define IPR_UCODE_DOWNLOAD_REQ 0x10
438 __be16 reserved;
439 }__attribute__((packed, aligned (4)));
440
441 struct ipr_config_table_hdr64 {
442 __be16 num_entries;
443 __be16 reserved;
444 u8 flags;
445 u8 reserved2[11];
446 }__attribute__((packed, aligned (4)));
447
448 struct ipr_config_table {
449 struct ipr_config_table_hdr hdr;
450 struct ipr_config_table_entry dev[0];
451 }__attribute__((packed, aligned (4)));
452
453 struct ipr_config_table64 {
454 struct ipr_config_table_hdr64 hdr64;
455 struct ipr_config_table_entry64 dev[0];
456 }__attribute__((packed, aligned (8)));
457
458 struct ipr_config_table_entry_wrapper {
459 union {
460 struct ipr_config_table_entry *cfgte;
461 struct ipr_config_table_entry64 *cfgte64;
462 } u;
463 };
464
465 struct ipr_hostrcb_cfg_ch_not {
466 union {
467 struct ipr_config_table_entry cfgte;
468 struct ipr_config_table_entry64 cfgte64;
469 } u;
470 u8 reserved[936];
471 }__attribute__((packed, aligned (4)));
472
473 struct ipr_supported_device {
474 __be16 data_length;
475 u8 reserved;
476 u8 num_records;
477 struct ipr_std_inq_vpids vpids;
478 u8 reserved2[16];
479 }__attribute__((packed, aligned (4)));
480
481 struct ipr_hrr_queue {
482 struct ipr_ioa_cfg *ioa_cfg;
483 __be32 *host_rrq;
484 dma_addr_t host_rrq_dma;
485 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
486 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
487 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
488 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
489 #define IPR_ID_HRRQ_SELE_ENABLE 0x02
490 volatile __be32 *hrrq_start;
491 volatile __be32 *hrrq_end;
492 volatile __be32 *hrrq_curr;
493
494 struct list_head hrrq_free_q;
495 struct list_head hrrq_pending_q;
496 spinlock_t _lock;
497 spinlock_t *lock;
498
499 volatile u32 toggle_bit;
500 u32 size;
501 u32 min_cmd_id;
502 u32 max_cmd_id;
503 u8 allow_interrupts:1;
504 u8 ioa_is_dead:1;
505 u8 allow_cmds:1;
506 u8 removing_ioa:1;
507
508 struct blk_iopoll iopoll;
509 };
510
511 /* Command packet structure */
512 struct ipr_cmd_pkt {
513 u8 reserved; /* Reserved by IOA */
514 u8 hrrq_id;
515 u8 request_type;
516 #define IPR_RQTYPE_SCSICDB 0x00
517 #define IPR_RQTYPE_IOACMD 0x01
518 #define IPR_RQTYPE_HCAM 0x02
519 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
520
521 u8 reserved2;
522
523 u8 flags_hi;
524 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
525 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
526 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
527 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
528 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
529
530 u8 flags_lo;
531 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
532 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
533 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
534 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
535 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
536 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
537 #define IPR_FLAGS_LO_ACA_TASK 0x08
538
539 u8 cdb[16];
540 __be16 timeout;
541 }__attribute__ ((packed, aligned(4)));
542
543 struct ipr_ioarcb_ata_regs { /* 22 bytes */
544 u8 flags;
545 #define IPR_ATA_FLAG_PACKET_CMD 0x80
546 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
547 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
548 u8 reserved[3];
549
550 __be16 data;
551 u8 feature;
552 u8 nsect;
553 u8 lbal;
554 u8 lbam;
555 u8 lbah;
556 u8 device;
557 u8 command;
558 u8 reserved2[3];
559 u8 hob_feature;
560 u8 hob_nsect;
561 u8 hob_lbal;
562 u8 hob_lbam;
563 u8 hob_lbah;
564 u8 ctl;
565 }__attribute__ ((packed, aligned(2)));
566
567 struct ipr_ioadl_desc {
568 __be32 flags_and_data_len;
569 #define IPR_IOADL_FLAGS_MASK 0xff000000
570 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
571 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
572 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
573 #define IPR_IOADL_FLAGS_READ 0x48000000
574 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
575 #define IPR_IOADL_FLAGS_WRITE 0x68000000
576 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
577 #define IPR_IOADL_FLAGS_LAST 0x01000000
578
579 __be32 address;
580 }__attribute__((packed, aligned (8)));
581
582 struct ipr_ioadl64_desc {
583 __be32 flags;
584 __be32 data_len;
585 __be64 address;
586 }__attribute__((packed, aligned (16)));
587
588 struct ipr_ata64_ioadl {
589 struct ipr_ioarcb_ata_regs regs;
590 u16 reserved[5];
591 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
592 }__attribute__((packed, aligned (16)));
593
594 struct ipr_ioarcb_add_data {
595 union {
596 struct ipr_ioarcb_ata_regs regs;
597 struct ipr_ioadl_desc ioadl[5];
598 __be32 add_cmd_parms[10];
599 } u;
600 }__attribute__ ((packed, aligned (4)));
601
602 struct ipr_ioarcb_sis64_add_addr_ecb {
603 __be64 ioasa_host_pci_addr;
604 __be64 data_ioadl_addr;
605 __be64 reserved;
606 __be32 ext_control_buf[4];
607 }__attribute__((packed, aligned (8)));
608
609 /* IOA Request Control Block 128 bytes */
610 struct ipr_ioarcb {
611 union {
612 __be32 ioarcb_host_pci_addr;
613 __be64 ioarcb_host_pci_addr64;
614 } a;
615 __be32 res_handle;
616 __be32 host_response_handle;
617 __be32 reserved1;
618 __be32 reserved2;
619 __be32 reserved3;
620
621 __be32 data_transfer_length;
622 __be32 read_data_transfer_length;
623 __be32 write_ioadl_addr;
624 __be32 ioadl_len;
625 __be32 read_ioadl_addr;
626 __be32 read_ioadl_len;
627
628 __be32 ioasa_host_pci_addr;
629 __be16 ioasa_len;
630 __be16 reserved4;
631
632 struct ipr_cmd_pkt cmd_pkt;
633
634 __be16 add_cmd_parms_offset;
635 __be16 add_cmd_parms_len;
636
637 union {
638 struct ipr_ioarcb_add_data add_data;
639 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
640 } u;
641
642 }__attribute__((packed, aligned (4)));
643
644 struct ipr_ioasa_vset {
645 __be32 failing_lba_hi;
646 __be32 failing_lba_lo;
647 __be32 reserved;
648 }__attribute__((packed, aligned (4)));
649
650 struct ipr_ioasa_af_dasd {
651 __be32 failing_lba;
652 __be32 reserved[2];
653 }__attribute__((packed, aligned (4)));
654
655 struct ipr_ioasa_gpdd {
656 u8 end_state;
657 u8 bus_phase;
658 __be16 reserved;
659 __be32 ioa_data[2];
660 }__attribute__((packed, aligned (4)));
661
662 struct ipr_ioasa_gata {
663 u8 error;
664 u8 nsect; /* Interrupt reason */
665 u8 lbal;
666 u8 lbam;
667 u8 lbah;
668 u8 device;
669 u8 status;
670 u8 alt_status; /* ATA CTL */
671 u8 hob_nsect;
672 u8 hob_lbal;
673 u8 hob_lbam;
674 u8 hob_lbah;
675 }__attribute__((packed, aligned (4)));
676
677 struct ipr_auto_sense {
678 __be16 auto_sense_len;
679 __be16 ioa_data_len;
680 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
681 };
682
683 struct ipr_ioasa_hdr {
684 __be32 ioasc;
685 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
686 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
687 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
688 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
689
690 __be16 ret_stat_len; /* Length of the returned IOASA */
691
692 __be16 avail_stat_len; /* Total Length of status available. */
693
694 __be32 residual_data_len; /* number of bytes in the host data */
695 /* buffers that were not used by the IOARCB command. */
696
697 __be32 ilid;
698 #define IPR_NO_ILID 0
699 #define IPR_DRIVER_ILID 0xffffffff
700
701 __be32 fd_ioasc;
702
703 __be32 fd_phys_locator;
704
705 __be32 fd_res_handle;
706
707 __be32 ioasc_specific; /* status code specific field */
708 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
709 #define IPR_AUTOSENSE_VALID 0x40000000
710 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
711 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
712 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
713 #define IPR_FIELD_POINTER_MASK 0x0000ffff
714
715 }__attribute__((packed, aligned (4)));
716
717 struct ipr_ioasa {
718 struct ipr_ioasa_hdr hdr;
719
720 union {
721 struct ipr_ioasa_vset vset;
722 struct ipr_ioasa_af_dasd dasd;
723 struct ipr_ioasa_gpdd gpdd;
724 struct ipr_ioasa_gata gata;
725 } u;
726
727 struct ipr_auto_sense auto_sense;
728 }__attribute__((packed, aligned (4)));
729
730 struct ipr_ioasa64 {
731 struct ipr_ioasa_hdr hdr;
732 u8 fd_res_path[8];
733
734 union {
735 struct ipr_ioasa_vset vset;
736 struct ipr_ioasa_af_dasd dasd;
737 struct ipr_ioasa_gpdd gpdd;
738 struct ipr_ioasa_gata gata;
739 } u;
740
741 struct ipr_auto_sense auto_sense;
742 }__attribute__((packed, aligned (4)));
743
744 struct ipr_mode_parm_hdr {
745 u8 length;
746 u8 medium_type;
747 u8 device_spec_parms;
748 u8 block_desc_len;
749 }__attribute__((packed));
750
751 struct ipr_mode_pages {
752 struct ipr_mode_parm_hdr hdr;
753 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
754 }__attribute__((packed));
755
756 struct ipr_mode_page_hdr {
757 u8 ps_page_code;
758 #define IPR_MODE_PAGE_PS 0x80
759 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
760 u8 page_length;
761 }__attribute__ ((packed));
762
763 struct ipr_dev_bus_entry {
764 struct ipr_res_addr res_addr;
765 u8 flags;
766 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
767 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
768 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
769 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
770 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
771 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
772 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
773
774 u8 scsi_id;
775 u8 bus_width;
776 u8 extended_reset_delay;
777 #define IPR_EXTENDED_RESET_DELAY 7
778
779 __be32 max_xfer_rate;
780
781 u8 spinup_delay;
782 u8 reserved3;
783 __be16 reserved4;
784 }__attribute__((packed, aligned (4)));
785
786 struct ipr_mode_page28 {
787 struct ipr_mode_page_hdr hdr;
788 u8 num_entries;
789 u8 entry_length;
790 struct ipr_dev_bus_entry bus[0];
791 }__attribute__((packed));
792
793 struct ipr_mode_page24 {
794 struct ipr_mode_page_hdr hdr;
795 u8 flags;
796 #define IPR_ENABLE_DUAL_IOA_AF 0x80
797 }__attribute__((packed));
798
799 struct ipr_ioa_vpd {
800 struct ipr_std_inq_data std_inq_data;
801 u8 ascii_part_num[12];
802 u8 reserved[40];
803 u8 ascii_plant_code[4];
804 }__attribute__((packed));
805
806 struct ipr_inquiry_page3 {
807 u8 peri_qual_dev_type;
808 u8 page_code;
809 u8 reserved1;
810 u8 page_length;
811 u8 ascii_len;
812 u8 reserved2[3];
813 u8 load_id[4];
814 u8 major_release;
815 u8 card_type;
816 u8 minor_release[2];
817 u8 ptf_number[4];
818 u8 patch_number[4];
819 }__attribute__((packed));
820
821 struct ipr_inquiry_cap {
822 u8 peri_qual_dev_type;
823 u8 page_code;
824 u8 reserved1;
825 u8 page_length;
826 u8 ascii_len;
827 u8 reserved2;
828 u8 sis_version[2];
829 u8 cap;
830 #define IPR_CAP_DUAL_IOA_RAID 0x80
831 u8 reserved3[15];
832 }__attribute__((packed));
833
834 #define IPR_INQUIRY_PAGE0_ENTRIES 20
835 struct ipr_inquiry_page0 {
836 u8 peri_qual_dev_type;
837 u8 page_code;
838 u8 reserved1;
839 u8 len;
840 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
841 }__attribute__((packed));
842
843 struct ipr_hostrcb_device_data_entry {
844 struct ipr_vpd vpd;
845 struct ipr_res_addr dev_res_addr;
846 struct ipr_vpd new_vpd;
847 struct ipr_vpd ioa_last_with_dev_vpd;
848 struct ipr_vpd cfc_last_with_dev_vpd;
849 __be32 ioa_data[5];
850 }__attribute__((packed, aligned (4)));
851
852 struct ipr_hostrcb_device_data_entry_enhanced {
853 struct ipr_ext_vpd vpd;
854 u8 ccin[4];
855 struct ipr_res_addr dev_res_addr;
856 struct ipr_ext_vpd new_vpd;
857 u8 new_ccin[4];
858 struct ipr_ext_vpd ioa_last_with_dev_vpd;
859 struct ipr_ext_vpd cfc_last_with_dev_vpd;
860 }__attribute__((packed, aligned (4)));
861
862 struct ipr_hostrcb64_device_data_entry_enhanced {
863 struct ipr_ext_vpd vpd;
864 u8 ccin[4];
865 u8 res_path[8];
866 struct ipr_ext_vpd new_vpd;
867 u8 new_ccin[4];
868 struct ipr_ext_vpd ioa_last_with_dev_vpd;
869 struct ipr_ext_vpd cfc_last_with_dev_vpd;
870 }__attribute__((packed, aligned (4)));
871
872 struct ipr_hostrcb_array_data_entry {
873 struct ipr_vpd vpd;
874 struct ipr_res_addr expected_dev_res_addr;
875 struct ipr_res_addr dev_res_addr;
876 }__attribute__((packed, aligned (4)));
877
878 struct ipr_hostrcb64_array_data_entry {
879 struct ipr_ext_vpd vpd;
880 u8 ccin[4];
881 u8 expected_res_path[8];
882 u8 res_path[8];
883 }__attribute__((packed, aligned (4)));
884
885 struct ipr_hostrcb_array_data_entry_enhanced {
886 struct ipr_ext_vpd vpd;
887 u8 ccin[4];
888 struct ipr_res_addr expected_dev_res_addr;
889 struct ipr_res_addr dev_res_addr;
890 }__attribute__((packed, aligned (4)));
891
892 struct ipr_hostrcb_type_ff_error {
893 __be32 ioa_data[758];
894 }__attribute__((packed, aligned (4)));
895
896 struct ipr_hostrcb_type_01_error {
897 __be32 seek_counter;
898 __be32 read_counter;
899 u8 sense_data[32];
900 __be32 ioa_data[236];
901 }__attribute__((packed, aligned (4)));
902
903 struct ipr_hostrcb_type_02_error {
904 struct ipr_vpd ioa_vpd;
905 struct ipr_vpd cfc_vpd;
906 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
907 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
908 __be32 ioa_data[3];
909 }__attribute__((packed, aligned (4)));
910
911 struct ipr_hostrcb_type_12_error {
912 struct ipr_ext_vpd ioa_vpd;
913 struct ipr_ext_vpd cfc_vpd;
914 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
915 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
916 __be32 ioa_data[3];
917 }__attribute__((packed, aligned (4)));
918
919 struct ipr_hostrcb_type_03_error {
920 struct ipr_vpd ioa_vpd;
921 struct ipr_vpd cfc_vpd;
922 __be32 errors_detected;
923 __be32 errors_logged;
924 u8 ioa_data[12];
925 struct ipr_hostrcb_device_data_entry dev[3];
926 }__attribute__((packed, aligned (4)));
927
928 struct ipr_hostrcb_type_13_error {
929 struct ipr_ext_vpd ioa_vpd;
930 struct ipr_ext_vpd cfc_vpd;
931 __be32 errors_detected;
932 __be32 errors_logged;
933 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
934 }__attribute__((packed, aligned (4)));
935
936 struct ipr_hostrcb_type_23_error {
937 struct ipr_ext_vpd ioa_vpd;
938 struct ipr_ext_vpd cfc_vpd;
939 __be32 errors_detected;
940 __be32 errors_logged;
941 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
942 }__attribute__((packed, aligned (4)));
943
944 struct ipr_hostrcb_type_04_error {
945 struct ipr_vpd ioa_vpd;
946 struct ipr_vpd cfc_vpd;
947 u8 ioa_data[12];
948 struct ipr_hostrcb_array_data_entry array_member[10];
949 __be32 exposed_mode_adn;
950 __be32 array_id;
951 struct ipr_vpd incomp_dev_vpd;
952 __be32 ioa_data2;
953 struct ipr_hostrcb_array_data_entry array_member2[8];
954 struct ipr_res_addr last_func_vset_res_addr;
955 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
956 u8 protection_level[8];
957 }__attribute__((packed, aligned (4)));
958
959 struct ipr_hostrcb_type_14_error {
960 struct ipr_ext_vpd ioa_vpd;
961 struct ipr_ext_vpd cfc_vpd;
962 __be32 exposed_mode_adn;
963 __be32 array_id;
964 struct ipr_res_addr last_func_vset_res_addr;
965 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
966 u8 protection_level[8];
967 __be32 num_entries;
968 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
969 }__attribute__((packed, aligned (4)));
970
971 struct ipr_hostrcb_type_24_error {
972 struct ipr_ext_vpd ioa_vpd;
973 struct ipr_ext_vpd cfc_vpd;
974 u8 reserved[2];
975 u8 exposed_mode_adn;
976 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
977 u8 array_id;
978 u8 last_res_path[8];
979 u8 protection_level[8];
980 struct ipr_ext_vpd64 array_vpd;
981 u8 description[16];
982 u8 reserved2[3];
983 u8 num_entries;
984 struct ipr_hostrcb64_array_data_entry array_member[32];
985 }__attribute__((packed, aligned (4)));
986
987 struct ipr_hostrcb_type_07_error {
988 u8 failure_reason[64];
989 struct ipr_vpd vpd;
990 u32 data[222];
991 }__attribute__((packed, aligned (4)));
992
993 struct ipr_hostrcb_type_17_error {
994 u8 failure_reason[64];
995 struct ipr_ext_vpd vpd;
996 u32 data[476];
997 }__attribute__((packed, aligned (4)));
998
999 struct ipr_hostrcb_config_element {
1000 u8 type_status;
1001 #define IPR_PATH_CFG_TYPE_MASK 0xF0
1002 #define IPR_PATH_CFG_NOT_EXIST 0x00
1003 #define IPR_PATH_CFG_IOA_PORT 0x10
1004 #define IPR_PATH_CFG_EXP_PORT 0x20
1005 #define IPR_PATH_CFG_DEVICE_PORT 0x30
1006 #define IPR_PATH_CFG_DEVICE_LUN 0x40
1007
1008 #define IPR_PATH_CFG_STATUS_MASK 0x0F
1009 #define IPR_PATH_CFG_NO_PROB 0x00
1010 #define IPR_PATH_CFG_DEGRADED 0x01
1011 #define IPR_PATH_CFG_FAILED 0x02
1012 #define IPR_PATH_CFG_SUSPECT 0x03
1013 #define IPR_PATH_NOT_DETECTED 0x04
1014 #define IPR_PATH_INCORRECT_CONN 0x05
1015
1016 u8 cascaded_expander;
1017 u8 phy;
1018 u8 link_rate;
1019 #define IPR_PHY_LINK_RATE_MASK 0x0F
1020
1021 __be32 wwid[2];
1022 }__attribute__((packed, aligned (4)));
1023
1024 struct ipr_hostrcb64_config_element {
1025 __be16 length;
1026 u8 descriptor_id;
1027 #define IPR_DESCRIPTOR_MASK 0xC0
1028 #define IPR_DESCRIPTOR_SIS64 0x00
1029
1030 u8 reserved;
1031 u8 type_status;
1032
1033 u8 reserved2[2];
1034 u8 link_rate;
1035
1036 u8 res_path[8];
1037 __be32 wwid[2];
1038 }__attribute__((packed, aligned (8)));
1039
1040 struct ipr_hostrcb_fabric_desc {
1041 __be16 length;
1042 u8 ioa_port;
1043 u8 cascaded_expander;
1044 u8 phy;
1045 u8 path_state;
1046 #define IPR_PATH_ACTIVE_MASK 0xC0
1047 #define IPR_PATH_NO_INFO 0x00
1048 #define IPR_PATH_ACTIVE 0x40
1049 #define IPR_PATH_NOT_ACTIVE 0x80
1050
1051 #define IPR_PATH_STATE_MASK 0x0F
1052 #define IPR_PATH_STATE_NO_INFO 0x00
1053 #define IPR_PATH_HEALTHY 0x01
1054 #define IPR_PATH_DEGRADED 0x02
1055 #define IPR_PATH_FAILED 0x03
1056
1057 __be16 num_entries;
1058 struct ipr_hostrcb_config_element elem[1];
1059 }__attribute__((packed, aligned (4)));
1060
1061 struct ipr_hostrcb64_fabric_desc {
1062 __be16 length;
1063 u8 descriptor_id;
1064
1065 u8 reserved[2];
1066 u8 path_state;
1067
1068 u8 reserved2[2];
1069 u8 res_path[8];
1070 u8 reserved3[6];
1071 __be16 num_entries;
1072 struct ipr_hostrcb64_config_element elem[1];
1073 }__attribute__((packed, aligned (8)));
1074
1075 #define for_each_hrrq(hrrq, ioa_cfg) \
1076 for (hrrq = (ioa_cfg)->hrrq; \
1077 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1078
1079 #define for_each_fabric_cfg(fabric, cfg) \
1080 for (cfg = (fabric)->elem; \
1081 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1082 cfg++)
1083
1084 struct ipr_hostrcb_type_20_error {
1085 u8 failure_reason[64];
1086 u8 reserved[3];
1087 u8 num_entries;
1088 struct ipr_hostrcb_fabric_desc desc[1];
1089 }__attribute__((packed, aligned (4)));
1090
1091 struct ipr_hostrcb_type_30_error {
1092 u8 failure_reason[64];
1093 u8 reserved[3];
1094 u8 num_entries;
1095 struct ipr_hostrcb64_fabric_desc desc[1];
1096 }__attribute__((packed, aligned (4)));
1097
1098 struct ipr_hostrcb_error {
1099 __be32 fd_ioasc;
1100 struct ipr_res_addr fd_res_addr;
1101 __be32 fd_res_handle;
1102 __be32 prc;
1103 union {
1104 struct ipr_hostrcb_type_ff_error type_ff_error;
1105 struct ipr_hostrcb_type_01_error type_01_error;
1106 struct ipr_hostrcb_type_02_error type_02_error;
1107 struct ipr_hostrcb_type_03_error type_03_error;
1108 struct ipr_hostrcb_type_04_error type_04_error;
1109 struct ipr_hostrcb_type_07_error type_07_error;
1110 struct ipr_hostrcb_type_12_error type_12_error;
1111 struct ipr_hostrcb_type_13_error type_13_error;
1112 struct ipr_hostrcb_type_14_error type_14_error;
1113 struct ipr_hostrcb_type_17_error type_17_error;
1114 struct ipr_hostrcb_type_20_error type_20_error;
1115 } u;
1116 }__attribute__((packed, aligned (4)));
1117
1118 struct ipr_hostrcb64_error {
1119 __be32 fd_ioasc;
1120 __be32 ioa_fw_level;
1121 __be32 fd_res_handle;
1122 __be32 prc;
1123 __be64 fd_dev_id;
1124 __be64 fd_lun;
1125 u8 fd_res_path[8];
1126 __be64 time_stamp;
1127 u8 reserved[16];
1128 union {
1129 struct ipr_hostrcb_type_ff_error type_ff_error;
1130 struct ipr_hostrcb_type_12_error type_12_error;
1131 struct ipr_hostrcb_type_17_error type_17_error;
1132 struct ipr_hostrcb_type_23_error type_23_error;
1133 struct ipr_hostrcb_type_24_error type_24_error;
1134 struct ipr_hostrcb_type_30_error type_30_error;
1135 } u;
1136 }__attribute__((packed, aligned (8)));
1137
1138 struct ipr_hostrcb_raw {
1139 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1140 }__attribute__((packed, aligned (4)));
1141
1142 struct ipr_hcam {
1143 u8 op_code;
1144 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1145 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1146
1147 u8 notify_type;
1148 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1149 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1150 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1151 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1152 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1153
1154 u8 notifications_lost;
1155 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1156 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1157
1158 u8 flags;
1159 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1160 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1161
1162 u8 overlay_id;
1163 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1164 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1165 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1166 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1167 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1168 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1169 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1170 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1171 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1172 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1173 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1174 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1175 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1176 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1177 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1178 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1179 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1180
1181 u8 reserved1[3];
1182 __be32 ilid;
1183 __be32 time_since_last_ioa_reset;
1184 __be32 reserved2;
1185 __be32 length;
1186
1187 union {
1188 struct ipr_hostrcb_error error;
1189 struct ipr_hostrcb64_error error64;
1190 struct ipr_hostrcb_cfg_ch_not ccn;
1191 struct ipr_hostrcb_raw raw;
1192 } u;
1193 }__attribute__((packed, aligned (4)));
1194
1195 struct ipr_hostrcb {
1196 struct ipr_hcam hcam;
1197 dma_addr_t hostrcb_dma;
1198 struct list_head queue;
1199 struct ipr_ioa_cfg *ioa_cfg;
1200 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1201 };
1202
1203 /* IPR smart dump table structures */
1204 struct ipr_sdt_entry {
1205 __be32 start_token;
1206 __be32 end_token;
1207 u8 reserved[4];
1208
1209 u8 flags;
1210 #define IPR_SDT_ENDIAN 0x80
1211 #define IPR_SDT_VALID_ENTRY 0x20
1212
1213 u8 resv;
1214 __be16 priority;
1215 }__attribute__((packed, aligned (4)));
1216
1217 struct ipr_sdt_header {
1218 __be32 state;
1219 __be32 num_entries;
1220 __be32 num_entries_used;
1221 __be32 dump_size;
1222 }__attribute__((packed, aligned (4)));
1223
1224 struct ipr_sdt {
1225 struct ipr_sdt_header hdr;
1226 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1227 }__attribute__((packed, aligned (4)));
1228
1229 struct ipr_uc_sdt {
1230 struct ipr_sdt_header hdr;
1231 struct ipr_sdt_entry entry[1];
1232 }__attribute__((packed, aligned (4)));
1233
1234 /*
1235 * Driver types
1236 */
1237 struct ipr_bus_attributes {
1238 u8 bus;
1239 u8 qas_enabled;
1240 u8 bus_width;
1241 u8 reserved;
1242 u32 max_xfer_rate;
1243 };
1244
1245 struct ipr_sata_port {
1246 struct ipr_ioa_cfg *ioa_cfg;
1247 struct ata_port *ap;
1248 struct ipr_resource_entry *res;
1249 struct ipr_ioasa_gata ioasa;
1250 };
1251
1252 struct ipr_resource_entry {
1253 u8 needs_sync_complete:1;
1254 u8 in_erp:1;
1255 u8 add_to_ml:1;
1256 u8 del_from_ml:1;
1257 u8 resetting_device:1;
1258
1259 u32 bus; /* AKA channel */
1260 u32 target; /* AKA id */
1261 u32 lun;
1262 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1263 #define IPR_VSET_VIRTUAL_BUS 0x2
1264 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1265
1266 #define IPR_GET_RES_PHYS_LOC(res) \
1267 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1268
1269 u8 ata_class;
1270
1271 u8 flags;
1272 __be16 res_flags;
1273
1274 u8 type;
1275
1276 u8 qmodel;
1277 struct ipr_std_inq_data std_inq_data;
1278
1279 __be32 res_handle;
1280 __be64 dev_id;
1281 __be64 lun_wwn;
1282 struct scsi_lun dev_lun;
1283 u8 res_path[8];
1284
1285 struct ipr_ioa_cfg *ioa_cfg;
1286 struct scsi_device *sdev;
1287 struct ipr_sata_port *sata_port;
1288 struct list_head queue;
1289 }; /* struct ipr_resource_entry */
1290
1291 struct ipr_resource_hdr {
1292 u16 num_entries;
1293 u16 reserved;
1294 };
1295
1296 struct ipr_misc_cbs {
1297 struct ipr_ioa_vpd ioa_vpd;
1298 struct ipr_inquiry_page0 page0_data;
1299 struct ipr_inquiry_page3 page3_data;
1300 struct ipr_inquiry_cap cap;
1301 struct ipr_mode_pages mode_pages;
1302 struct ipr_supported_device supp_dev;
1303 };
1304
1305 struct ipr_interrupt_offsets {
1306 unsigned long set_interrupt_mask_reg;
1307 unsigned long clr_interrupt_mask_reg;
1308 unsigned long clr_interrupt_mask_reg32;
1309 unsigned long sense_interrupt_mask_reg;
1310 unsigned long sense_interrupt_mask_reg32;
1311 unsigned long clr_interrupt_reg;
1312 unsigned long clr_interrupt_reg32;
1313
1314 unsigned long sense_interrupt_reg;
1315 unsigned long sense_interrupt_reg32;
1316 unsigned long ioarrin_reg;
1317 unsigned long sense_uproc_interrupt_reg;
1318 unsigned long sense_uproc_interrupt_reg32;
1319 unsigned long set_uproc_interrupt_reg;
1320 unsigned long set_uproc_interrupt_reg32;
1321 unsigned long clr_uproc_interrupt_reg;
1322 unsigned long clr_uproc_interrupt_reg32;
1323
1324 unsigned long init_feedback_reg;
1325
1326 unsigned long dump_addr_reg;
1327 unsigned long dump_data_reg;
1328
1329 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1330 unsigned long endian_swap_reg;
1331 };
1332
1333 struct ipr_interrupts {
1334 void __iomem *set_interrupt_mask_reg;
1335 void __iomem *clr_interrupt_mask_reg;
1336 void __iomem *clr_interrupt_mask_reg32;
1337 void __iomem *sense_interrupt_mask_reg;
1338 void __iomem *sense_interrupt_mask_reg32;
1339 void __iomem *clr_interrupt_reg;
1340 void __iomem *clr_interrupt_reg32;
1341
1342 void __iomem *sense_interrupt_reg;
1343 void __iomem *sense_interrupt_reg32;
1344 void __iomem *ioarrin_reg;
1345 void __iomem *sense_uproc_interrupt_reg;
1346 void __iomem *sense_uproc_interrupt_reg32;
1347 void __iomem *set_uproc_interrupt_reg;
1348 void __iomem *set_uproc_interrupt_reg32;
1349 void __iomem *clr_uproc_interrupt_reg;
1350 void __iomem *clr_uproc_interrupt_reg32;
1351
1352 void __iomem *init_feedback_reg;
1353
1354 void __iomem *dump_addr_reg;
1355 void __iomem *dump_data_reg;
1356
1357 void __iomem *endian_swap_reg;
1358 };
1359
1360 struct ipr_chip_cfg_t {
1361 u32 mailbox;
1362 u16 max_cmds;
1363 u8 cache_line_size;
1364 u8 clear_isr;
1365 u32 iopoll_weight;
1366 struct ipr_interrupt_offsets regs;
1367 };
1368
1369 struct ipr_chip_t {
1370 u16 vendor;
1371 u16 device;
1372 u16 intr_type;
1373 #define IPR_USE_LSI 0x00
1374 #define IPR_USE_MSI 0x01
1375 #define IPR_USE_MSIX 0x02
1376 u16 sis_type;
1377 #define IPR_SIS32 0x00
1378 #define IPR_SIS64 0x01
1379 u16 bist_method;
1380 #define IPR_PCI_CFG 0x00
1381 #define IPR_MMIO 0x01
1382 const struct ipr_chip_cfg_t *cfg;
1383 };
1384
1385 enum ipr_shutdown_type {
1386 IPR_SHUTDOWN_NORMAL = 0x00,
1387 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1388 IPR_SHUTDOWN_ABBREV = 0x80,
1389 IPR_SHUTDOWN_NONE = 0x100
1390 };
1391
1392 struct ipr_trace_entry {
1393 u32 time;
1394
1395 u8 op_code;
1396 u8 ata_op_code;
1397 u8 type;
1398 #define IPR_TRACE_START 0x00
1399 #define IPR_TRACE_FINISH 0xff
1400 u8 cmd_index;
1401
1402 __be32 res_handle;
1403 union {
1404 u32 ioasc;
1405 u32 add_data;
1406 u32 res_addr;
1407 } u;
1408 };
1409
1410 struct ipr_sglist {
1411 u32 order;
1412 u32 num_sg;
1413 u32 num_dma_sg;
1414 u32 buffer_len;
1415 struct scatterlist scatterlist[1];
1416 };
1417
1418 enum ipr_sdt_state {
1419 INACTIVE,
1420 WAIT_FOR_DUMP,
1421 GET_DUMP,
1422 READ_DUMP,
1423 ABORT_DUMP,
1424 DUMP_OBTAINED
1425 };
1426
1427 /* Per-controller data */
1428 struct ipr_ioa_cfg {
1429 char eye_catcher[8];
1430 #define IPR_EYECATCHER "iprcfg"
1431
1432 struct list_head queue;
1433
1434 u8 in_reset_reload:1;
1435 u8 in_ioa_bringdown:1;
1436 u8 ioa_unit_checked:1;
1437 u8 dump_taken:1;
1438 u8 allow_ml_add_del:1;
1439 u8 needs_hard_reset:1;
1440 u8 dual_raid:1;
1441 u8 needs_warm_reset:1;
1442 u8 msi_received:1;
1443 u8 sis64:1;
1444 u8 dump_timeout:1;
1445 u8 cfg_locked:1;
1446 u8 clear_isr:1;
1447
1448 u8 revid;
1449
1450 /*
1451 * Bitmaps for SIS64 generated target values
1452 */
1453 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1454 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1455 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1456
1457 u16 type; /* CCIN of the card */
1458
1459 u8 log_level;
1460 #define IPR_MAX_LOG_LEVEL 4
1461 #define IPR_DEFAULT_LOG_LEVEL 2
1462
1463 #define IPR_NUM_TRACE_INDEX_BITS 8
1464 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1465 #define IPR_TRACE_INDEX_MASK (IPR_NUM_TRACE_ENTRIES - 1)
1466 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1467 char trace_start[8];
1468 #define IPR_TRACE_START_LABEL "trace"
1469 struct ipr_trace_entry *trace;
1470 atomic_t trace_index;
1471
1472 char cfg_table_start[8];
1473 #define IPR_CFG_TBL_START "cfg"
1474 union {
1475 struct ipr_config_table *cfg_table;
1476 struct ipr_config_table64 *cfg_table64;
1477 } u;
1478 dma_addr_t cfg_table_dma;
1479 u32 cfg_table_size;
1480 u32 max_devs_supported;
1481
1482 char resource_table_label[8];
1483 #define IPR_RES_TABLE_LABEL "res_tbl"
1484 struct ipr_resource_entry *res_entries;
1485 struct list_head free_res_q;
1486 struct list_head used_res_q;
1487
1488 char ipr_hcam_label[8];
1489 #define IPR_HCAM_LABEL "hcams"
1490 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1491 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1492 struct list_head hostrcb_free_q;
1493 struct list_head hostrcb_pending_q;
1494
1495 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1496 u32 hrrq_num;
1497 atomic_t hrrq_index;
1498 u16 identify_hrrq_index;
1499
1500 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1501
1502 unsigned int transop_timeout;
1503 const struct ipr_chip_cfg_t *chip_cfg;
1504 const struct ipr_chip_t *ipr_chip;
1505
1506 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1507 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1508 void __iomem *ioa_mailbox;
1509 struct ipr_interrupts regs;
1510
1511 u16 saved_pcix_cmd_reg;
1512 u16 reset_retries;
1513
1514 u32 errors_logged;
1515 u32 doorbell;
1516
1517 struct Scsi_Host *host;
1518 struct pci_dev *pdev;
1519 struct ipr_sglist *ucode_sglist;
1520 u8 saved_mode_page_len;
1521
1522 struct work_struct work_q;
1523
1524 wait_queue_head_t reset_wait_q;
1525 wait_queue_head_t msi_wait_q;
1526
1527 struct ipr_dump *dump;
1528 enum ipr_sdt_state sdt_state;
1529
1530 struct ipr_misc_cbs *vpd_cbs;
1531 dma_addr_t vpd_cbs_dma;
1532
1533 struct pci_pool *ipr_cmd_pool;
1534
1535 struct ipr_cmnd *reset_cmd;
1536 int (*reset) (struct ipr_cmnd *);
1537
1538 struct ata_host ata_host;
1539 char ipr_cmd_label[8];
1540 #define IPR_CMD_LABEL "ipr_cmd"
1541 u32 max_cmds;
1542 struct ipr_cmnd **ipr_cmnd_list;
1543 dma_addr_t *ipr_cmnd_list_dma;
1544
1545 u16 intr_flag;
1546 unsigned int nvectors;
1547
1548 struct {
1549 unsigned short vec;
1550 char desc[22];
1551 } vectors_info[IPR_MAX_MSIX_VECTORS];
1552
1553 u32 iopoll_weight;
1554
1555 }; /* struct ipr_ioa_cfg */
1556
1557 struct ipr_cmnd {
1558 struct ipr_ioarcb ioarcb;
1559 union {
1560 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1561 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1562 struct ipr_ata64_ioadl ata_ioadl;
1563 } i;
1564 union {
1565 struct ipr_ioasa ioasa;
1566 struct ipr_ioasa64 ioasa64;
1567 } s;
1568 struct list_head queue;
1569 struct scsi_cmnd *scsi_cmd;
1570 struct ata_queued_cmd *qc;
1571 struct completion completion;
1572 struct timer_list timer;
1573 void (*fast_done) (struct ipr_cmnd *);
1574 void (*done) (struct ipr_cmnd *);
1575 int (*job_step) (struct ipr_cmnd *);
1576 int (*job_step_failed) (struct ipr_cmnd *);
1577 u16 cmd_index;
1578 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1579 dma_addr_t sense_buffer_dma;
1580 unsigned short dma_use_sg;
1581 dma_addr_t dma_addr;
1582 struct ipr_cmnd *sibling;
1583 union {
1584 enum ipr_shutdown_type shutdown_type;
1585 struct ipr_hostrcb *hostrcb;
1586 unsigned long time_left;
1587 unsigned long scratch;
1588 struct ipr_resource_entry *res;
1589 struct scsi_device *sdev;
1590 } u;
1591
1592 struct completion *eh_comp;
1593 struct ipr_hrr_queue *hrrq;
1594 struct ipr_ioa_cfg *ioa_cfg;
1595 };
1596
1597 struct ipr_ses_table_entry {
1598 char product_id[17];
1599 char compare_product_id_byte[17];
1600 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1601 };
1602
1603 struct ipr_dump_header {
1604 u32 eye_catcher;
1605 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1606 u32 len;
1607 u32 num_entries;
1608 u32 first_entry_offset;
1609 u32 status;
1610 #define IPR_DUMP_STATUS_SUCCESS 0
1611 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1612 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1613 u32 os;
1614 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1615 u32 driver_name;
1616 #define IPR_DUMP_DRIVER_NAME 0x49505232
1617 }__attribute__((packed, aligned (4)));
1618
1619 struct ipr_dump_entry_header {
1620 u32 eye_catcher;
1621 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1622 u32 len;
1623 u32 num_elems;
1624 u32 offset;
1625 u32 data_type;
1626 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1627 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1628 u32 id;
1629 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1630 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1631 #define IPR_DUMP_TRACE_ID 0x54524143
1632 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1633 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1634 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1635 #define IPR_DUMP_PEND_OPS 0x414F5053
1636 u32 status;
1637 }__attribute__((packed, aligned (4)));
1638
1639 struct ipr_dump_location_entry {
1640 struct ipr_dump_entry_header hdr;
1641 u8 location[20];
1642 }__attribute__((packed));
1643
1644 struct ipr_dump_trace_entry {
1645 struct ipr_dump_entry_header hdr;
1646 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1647 }__attribute__((packed, aligned (4)));
1648
1649 struct ipr_dump_version_entry {
1650 struct ipr_dump_entry_header hdr;
1651 u8 version[sizeof(IPR_DRIVER_VERSION)];
1652 };
1653
1654 struct ipr_dump_ioa_type_entry {
1655 struct ipr_dump_entry_header hdr;
1656 u32 type;
1657 u32 fw_version;
1658 };
1659
1660 struct ipr_driver_dump {
1661 struct ipr_dump_header hdr;
1662 struct ipr_dump_version_entry version_entry;
1663 struct ipr_dump_location_entry location_entry;
1664 struct ipr_dump_ioa_type_entry ioa_type_entry;
1665 struct ipr_dump_trace_entry trace_entry;
1666 }__attribute__((packed));
1667
1668 struct ipr_ioa_dump {
1669 struct ipr_dump_entry_header hdr;
1670 struct ipr_sdt sdt;
1671 __be32 **ioa_data;
1672 u32 reserved;
1673 u32 next_page_index;
1674 u32 page_offset;
1675 u32 format;
1676 }__attribute__((packed, aligned (4)));
1677
1678 struct ipr_dump {
1679 struct kref kref;
1680 struct ipr_ioa_cfg *ioa_cfg;
1681 struct ipr_driver_dump driver_dump;
1682 struct ipr_ioa_dump ioa_dump;
1683 };
1684
1685 struct ipr_error_table_t {
1686 u32 ioasc;
1687 int log_ioasa;
1688 int log_hcam;
1689 char *error;
1690 };
1691
1692 struct ipr_software_inq_lid_info {
1693 __be32 load_id;
1694 __be32 timestamp[3];
1695 }__attribute__((packed, aligned (4)));
1696
1697 struct ipr_ucode_image_header {
1698 __be32 header_length;
1699 __be32 lid_table_offset;
1700 u8 major_release;
1701 u8 card_type;
1702 u8 minor_release[2];
1703 u8 reserved[20];
1704 char eyecatcher[16];
1705 __be32 num_lids;
1706 struct ipr_software_inq_lid_info lid[1];
1707 }__attribute__((packed, aligned (4)));
1708
1709 /*
1710 * Macros
1711 */
1712 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1713
1714 #ifdef CONFIG_SCSI_IPR_TRACE
1715 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1716 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1717 #else
1718 #define ipr_create_trace_file(kobj, attr) 0
1719 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1720 #endif
1721
1722 #ifdef CONFIG_SCSI_IPR_DUMP
1723 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1724 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1725 #else
1726 #define ipr_create_dump_file(kobj, attr) 0
1727 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1728 #endif
1729
1730 /*
1731 * Error logging macros
1732 */
1733 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1734 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1735 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1736
1737 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1738 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1739 bus, target, lun, ##__VA_ARGS__)
1740
1741 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1742 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1743
1744 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1745 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1746 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1747
1748 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1749 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1750
1751 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1752 { \
1753 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1754 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1755 } else { \
1756 ipr_err(fmt": %d:%d:%d:%d\n", \
1757 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1758 (res).bus, (res).target, (res).lun); \
1759 } \
1760 }
1761
1762 #define ipr_hcam_err(hostrcb, fmt, ...) \
1763 { \
1764 if (ipr_is_device(hostrcb)) { \
1765 if ((hostrcb)->ioa_cfg->sis64) { \
1766 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1767 ipr_format_res_path(hostrcb->ioa_cfg, \
1768 hostrcb->hcam.u.error64.fd_res_path, \
1769 hostrcb->rp_buffer, \
1770 sizeof(hostrcb->rp_buffer)), \
1771 __VA_ARGS__); \
1772 } else { \
1773 ipr_ra_err((hostrcb)->ioa_cfg, \
1774 (hostrcb)->hcam.u.error.fd_res_addr, \
1775 fmt, __VA_ARGS__); \
1776 } \
1777 } else { \
1778 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1779 } \
1780 }
1781
1782 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1783 __FILE__, __func__, __LINE__)
1784
1785 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1786 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1787
1788 #define ipr_err_separator \
1789 ipr_err("----------------------------------------------------------\n")
1790
1791
1792 /*
1793 * Inlines
1794 */
1795
1796 /**
1797 * ipr_is_ioa_resource - Determine if a resource is the IOA
1798 * @res: resource entry struct
1799 *
1800 * Return value:
1801 * 1 if IOA / 0 if not IOA
1802 **/
1803 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1804 {
1805 return res->type == IPR_RES_TYPE_IOAFP;
1806 }
1807
1808 /**
1809 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1810 * @res: resource entry struct
1811 *
1812 * Return value:
1813 * 1 if AF DASD / 0 if not AF DASD
1814 **/
1815 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1816 {
1817 return res->type == IPR_RES_TYPE_AF_DASD ||
1818 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1819 }
1820
1821 /**
1822 * ipr_is_vset_device - Determine if a resource is a VSET
1823 * @res: resource entry struct
1824 *
1825 * Return value:
1826 * 1 if VSET / 0 if not VSET
1827 **/
1828 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1829 {
1830 return res->type == IPR_RES_TYPE_VOLUME_SET;
1831 }
1832
1833 /**
1834 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1835 * @res: resource entry struct
1836 *
1837 * Return value:
1838 * 1 if GSCSI / 0 if not GSCSI
1839 **/
1840 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1841 {
1842 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1843 }
1844
1845 /**
1846 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1847 * @res: resource entry struct
1848 *
1849 * Return value:
1850 * 1 if SCSI disk / 0 if not SCSI disk
1851 **/
1852 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1853 {
1854 if (ipr_is_af_dasd_device(res) ||
1855 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1856 return 1;
1857 else
1858 return 0;
1859 }
1860
1861 /**
1862 * ipr_is_gata - Determine if a resource is a generic ATA resource
1863 * @res: resource entry struct
1864 *
1865 * Return value:
1866 * 1 if GATA / 0 if not GATA
1867 **/
1868 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1869 {
1870 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1871 }
1872
1873 /**
1874 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1875 * @res: resource entry struct
1876 *
1877 * Return value:
1878 * 1 if NACA queueing model / 0 if not NACA queueing model
1879 **/
1880 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1881 {
1882 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1883 return 1;
1884 return 0;
1885 }
1886
1887 /**
1888 * ipr_is_device - Determine if the hostrcb structure is related to a device
1889 * @hostrcb: host resource control blocks struct
1890 *
1891 * Return value:
1892 * 1 if AF / 0 if not AF
1893 **/
1894 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1895 {
1896 struct ipr_res_addr *res_addr;
1897 u8 *res_path;
1898
1899 if (hostrcb->ioa_cfg->sis64) {
1900 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1901 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1902 res_path[0] == 0x81) && res_path[2] != 0xFF)
1903 return 1;
1904 } else {
1905 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1906
1907 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1908 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1909 return 1;
1910 }
1911 return 0;
1912 }
1913
1914 /**
1915 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1916 * @sdt_word: SDT address
1917 *
1918 * Return value:
1919 * 1 if format 2 / 0 if not
1920 **/
1921 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1922 {
1923 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1924
1925 switch (bar_sel) {
1926 case IPR_SDT_FMT2_BAR0_SEL:
1927 case IPR_SDT_FMT2_BAR1_SEL:
1928 case IPR_SDT_FMT2_BAR2_SEL:
1929 case IPR_SDT_FMT2_BAR3_SEL:
1930 case IPR_SDT_FMT2_BAR4_SEL:
1931 case IPR_SDT_FMT2_BAR5_SEL:
1932 case IPR_SDT_FMT2_EXP_ROM_SEL:
1933 return 1;
1934 };
1935
1936 return 0;
1937 }
1938
1939 #ifndef writeq
1940 static inline void writeq(u64 val, void __iomem *addr)
1941 {
1942 writel(((u32) (val >> 32)), addr);
1943 writel(((u32) (val)), (addr + 4));
1944 }
1945 #endif
1946
1947 #endif /* _IPR_H */
Linux with added FPC-III support