drivers/staging/xillybus/xillybus.h

   1 /*
   2  * linux/drivers/misc/xillybus.h
   3  *
   4  * Copyright 2011 Xillybus Ltd, http://xillybus.com
   5  *
   6  * Header file for the Xillybus FPGA/host framework.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the smems of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  */
  12
  13 #ifndef __XILLYBUS_H
  14 #define __XILLYBUS_H
  15
  16 #include <linux/list.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/sched.h>
  21 #include <linux/cdev.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mutex.h>
  24 #include <linux/workqueue.h>
  25
  26 struct xilly_endpoint_hardware;
  27
  28 struct xilly_page {
  29         struct list_head node;
  30         unsigned long addr;
  31         unsigned int order;
  32 };
  33
  34 struct xilly_dma {
  35         struct list_head node;
  36         struct pci_dev *pdev;
  37         struct device *dev;
  38         dma_addr_t dma_addr;
  39         size_t size;
  40         int direction;
  41 };
  42
  43 struct xilly_buffer {
  44         void *addr;
  45         dma_addr_t dma_addr;
  46         int end_offset; /* Counting elements, not bytes */
  47 };
  48
  49 struct xilly_cleanup {
  50         struct list_head to_kfree;
  51         struct list_head to_pagefree;
  52         struct list_head to_unmap;
  53 };
  54
  55 struct xilly_idt_handle {
  56         unsigned char *chandesc;
  57         unsigned char *idt;
  58         int entries;
  59 };
  60
  61 /*
  62  * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
  63  * wr_* buffers are those consumed by read(), since the FPGA writes to them
  64  * and vice versa.
  65  */
  66
  67 struct xilly_channel {
  68         struct xilly_endpoint *endpoint;
  69         int chan_num;
  70         int log2_element_size;
  71         int seekable;
  72
  73         struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
  74         int num_wr_buffers;
  75         unsigned int wr_buf_size; /* In bytes */
  76         int wr_fpga_buf_idx;
  77         int wr_host_buf_idx;
  78         int wr_host_buf_pos;
  79         int wr_empty;
  80         int wr_ready; /* Significant only when wr_empty == 1 */
  81         int wr_sleepy;
  82         int wr_eof;
  83         int wr_hangup;
  84         spinlock_t wr_spinlock;
  85         struct mutex wr_mutex;
  86         wait_queue_head_t wr_wait;
  87         wait_queue_head_t wr_ready_wait;
  88         int wr_ref_count;
  89         int wr_synchronous;
  90         int wr_allow_partial;
  91         int wr_exclusive_open;
  92         int wr_supports_nonempty;
  93
  94         struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
  95         int num_rd_buffers;
  96         unsigned int rd_buf_size; /* In bytes */
  97         int rd_fpga_buf_idx;
  98         int rd_host_buf_pos;
  99         int rd_host_buf_idx;
 100         int rd_full;
 101         spinlock_t rd_spinlock;
 102         struct mutex rd_mutex;
 103         wait_queue_head_t rd_wait;
 104         int rd_ref_count;
 105         int rd_allow_partial;
 106         int rd_synchronous;
 107         int rd_exclusive_open;
 108         struct delayed_work rd_workitem;
 109         unsigned char rd_leftovers[4];
 110 };
 111
 112 struct xilly_endpoint {
 113         /*
 114          * One of pdev and dev is always NULL, and the other is a valid
 115          * pointer, depending on the type of device
 116          */
 117         struct pci_dev *pdev;
 118         struct device *dev;
 119         struct resource res; /* OF devices only */
 120         struct xilly_endpoint_hardware *ephw;
 121
 122         struct list_head ep_list;
 123         int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
 124         __iomem u32 *registers;
 125         int fatal_error;
 126
 127         struct mutex register_mutex;
 128         wait_queue_head_t ep_wait;
 129
 130         /* List of memory allocations, to make release easy */
 131         struct xilly_cleanup cleanup;
 132
 133         /* Channels and message handling */
 134         struct cdev cdev;
 135
 136         int major;
 137         int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */
 138
 139         int num_channels; /* EXCLUDING message buffer */
 140         struct xilly_channel **channels;
 141         int msg_counter;
 142         int failed_messages;
 143         int idtlen;
 144
 145         u32 *msgbuf_addr;
 146         dma_addr_t msgbuf_dma_addr;
 147         unsigned int msg_buf_size;
 148 };
 149
 150 struct xilly_endpoint_hardware {
 151         struct module *owner;
 152         void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *,
 153                                     dma_addr_t,
 154                                     size_t,
 155                                     int);
 156         void (*hw_sync_sgl_for_device)(struct xilly_endpoint *,
 157                                        dma_addr_t,
 158                                        size_t,
 159                                        int);
 160         dma_addr_t (*map_single)(struct xilly_cleanup *,
 161                                  struct xilly_endpoint *,
 162                                  void *,
 163                                  size_t,
 164                                  int);
 165         void (*unmap_single)(struct xilly_dma *entry);
 166 };
 167
 168 irqreturn_t xillybus_isr(int irq, void *data);
 169
 170 void xillybus_do_cleanup(struct xilly_cleanup *mem,
 171                          struct xilly_endpoint *endpoint);
 172
 173 struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
 174                                               struct device *dev,
 175                                               struct xilly_endpoint_hardware
 176                                               *ephw);
 177
 178 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
 179
 180 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
 181
 182 #endif /* __XILLYBUS_H */