drivers/usb/chipidea/ci.h

   1 /*
   2  * ci.h - common structures, functions, and macros of the ChipIdea driver
   3  *
   4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5  *
   6  * Author: David Lopo
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  14 #define __DRIVERS_USB_CHIPIDEA_CI_H
  15
  16 #include <linux/list.h>
  17 #include <linux/irqreturn.h>
  18 #include <linux/usb.h>
  19 #include <linux/usb/gadget.h>
  20
  21 /******************************************************************************
  22  * DEFINE
  23  *****************************************************************************/
  24 #define TD_PAGE_COUNT      5
  25 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
  26 #define ENDPT_MAX          32
  27
  28 /******************************************************************************
  29  * STRUCTURES
  30  *****************************************************************************/
  31 /**
  32  * struct ci_hw_ep - endpoint representation
  33  * @ep: endpoint structure for gadget drivers
  34  * @dir: endpoint direction (TX/RX)
  35  * @num: endpoint number
  36  * @type: endpoint type
  37  * @name: string description of the endpoint
  38  * @qh: queue head for this endpoint
  39  * @wedge: is the endpoint wedged
  40  * @ci: pointer to the controller
  41  * @lock: pointer to controller's spinlock
  42  * @td_pool: pointer to controller's TD pool
  43  */
  44 struct ci_hw_ep {
  45         struct usb_ep                           ep;
  46         u8                                      dir;
  47         u8                                      num;
  48         u8                                      type;
  49         char                                    name[16];
  50         struct {
  51                 struct list_head        queue;
  52                 struct ci_hw_qh         *ptr;
  53                 dma_addr_t              dma;
  54         }                                       qh;
  55         int                                     wedge;
  56
  57         /* global resources */
  58         struct ci_hdrc                          *ci;
  59         spinlock_t                              *lock;
  60         struct dma_pool                         *td_pool;
  61         struct td_node                          *pending_td;
  62 };
  63
  64 enum ci_role {
  65         CI_ROLE_HOST = 0,
  66         CI_ROLE_GADGET,
  67         CI_ROLE_END,
  68 };
  69
  70 /**
  71  * struct ci_role_driver - host/gadget role driver
  72  * start: start this role
  73  * stop: stop this role
  74  * irq: irq handler for this role
  75  * name: role name string (host/gadget)
  76  */
  77 struct ci_role_driver {
  78         int             (*start)(struct ci_hdrc *);
  79         void            (*stop)(struct ci_hdrc *);
  80         irqreturn_t     (*irq)(struct ci_hdrc *);
  81         const char      *name;
  82 };
  83
  84 /**
  85  * struct hw_bank - hardware register mapping representation
  86  * @lpm: set if the device is LPM capable
  87  * @phys: physical address of the controller's registers
  88  * @abs: absolute address of the beginning of register window
  89  * @cap: capability registers
  90  * @op: operational registers
  91  * @size: size of the register window
  92  * @regmap: register lookup table
  93  */
  94 struct hw_bank {
  95         unsigned        lpm;
  96         resource_size_t phys;
  97         void __iomem    *abs;
  98         void __iomem    *cap;
  99         void __iomem    *op;
 100         size_t          size;
 101         void __iomem    **regmap;
 102 };
 103
 104 /**
 105  * struct ci_hdrc - chipidea device representation
 106  * @dev: pointer to parent device
 107  * @lock: access synchronization
 108  * @hw_bank: hardware register mapping
 109  * @irq: IRQ number
 110  * @roles: array of supported roles for this controller
 111  * @role: current role
 112  * @is_otg: if the device is otg-capable
 113  * @work: work for role changing
 114  * @wq: workqueue thread
 115  * @qh_pool: allocation pool for queue heads
 116  * @td_pool: allocation pool for transfer descriptors
 117  * @gadget: device side representation for peripheral controller
 118  * @driver: gadget driver
 119  * @hw_ep_max: total number of endpoints supported by hardware
 120  * @ci_hw_ep: array of endpoints
 121  * @ep0_dir: ep0 direction
 122  * @ep0out: pointer to ep0 OUT endpoint
 123  * @ep0in: pointer to ep0 IN endpoint
 124  * @status: ep0 status request
 125  * @setaddr: if we should set the address on status completion
 126  * @address: usb address received from the host
 127  * @remote_wakeup: host-enabled remote wakeup
 128  * @suspended: suspended by host
 129  * @test_mode: the selected test mode
 130  * @platdata: platform specific information supplied by parent device
 131  * @vbus_active: is VBUS active
 132  * @transceiver: pointer to USB PHY, if any
 133  * @hcd: pointer to usb_hcd for ehci host driver
 134  * @debugfs: root dentry for this controller in debugfs
 135  * @id_event: indicates there is an id event, and handled at ci_otg_work
 136  * @b_sess_valid_event: indicates there is a vbus event, and handled
 137  * at ci_otg_work
 138  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 139  */
 140 struct ci_hdrc {
 141         struct device                   *dev;
 142         spinlock_t                      lock;
 143         struct hw_bank                  hw_bank;
 144         int                             irq;
 145         struct ci_role_driver           *roles[CI_ROLE_END];
 146         enum ci_role                    role;
 147         bool                            is_otg;
 148         struct work_struct              work;
 149         struct workqueue_struct         *wq;
 150
 151         struct dma_pool                 *qh_pool;
 152         struct dma_pool                 *td_pool;
 153
 154         struct usb_gadget               gadget;
 155         struct usb_gadget_driver        *driver;
 156         unsigned                        hw_ep_max;
 157         struct ci_hw_ep                 ci_hw_ep[ENDPT_MAX];
 158         u32                             ep0_dir;
 159         struct ci_hw_ep                 *ep0out, *ep0in;
 160
 161         struct usb_request              *status;
 162         bool                            setaddr;
 163         u8                              address;
 164         u8                              remote_wakeup;
 165         u8                              suspended;
 166         u8                              test_mode;
 167
 168         struct ci_hdrc_platform_data    *platdata;
 169         int                             vbus_active;
 170         /* FIXME: some day, we'll not use global phy */
 171         bool                            global_phy;
 172         struct usb_phy                  *transceiver;
 173         struct usb_hcd                  *hcd;
 174         struct dentry                   *debugfs;
 175         bool                            id_event;
 176         bool                            b_sess_valid_event;
 177         bool                            imx28_write_fix;
 178 };
 179
 180 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
 181 {
 182         BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
 183         return ci->roles[ci->role];
 184 }
 185
 186 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
 187 {
 188         int ret;
 189
 190         if (role >= CI_ROLE_END)
 191                 return -EINVAL;
 192
 193         if (!ci->roles[role])
 194                 return -ENXIO;
 195
 196         ret = ci->roles[role]->start(ci);
 197         if (!ret)
 198                 ci->role = role;
 199         return ret;
 200 }
 201
 202 static inline void ci_role_stop(struct ci_hdrc *ci)
 203 {
 204         enum ci_role role = ci->role;
 205
 206         if (role == CI_ROLE_END)
 207                 return;
 208
 209         ci->role = CI_ROLE_END;
 210
 211         ci->roles[role]->stop(ci);
 212 }
 213
 214 /******************************************************************************
 215  * REGISTERS
 216  *****************************************************************************/
 217 /* register size */
 218 #define REG_BITS   (32)
 219
 220 /* register indices */
 221 enum ci_hw_regs {
 222         CAP_CAPLENGTH,
 223         CAP_HCCPARAMS,
 224         CAP_DCCPARAMS,
 225         CAP_TESTMODE,
 226         CAP_LAST = CAP_TESTMODE,
 227         OP_USBCMD,
 228         OP_USBSTS,
 229         OP_USBINTR,
 230         OP_DEVICEADDR,
 231         OP_ENDPTLISTADDR,
 232         OP_PORTSC,
 233         OP_DEVLC,
 234         OP_OTGSC,
 235         OP_USBMODE,
 236         OP_ENDPTSETUPSTAT,
 237         OP_ENDPTPRIME,
 238         OP_ENDPTFLUSH,
 239         OP_ENDPTSTAT,
 240         OP_ENDPTCOMPLETE,
 241         OP_ENDPTCTRL,
 242         /* endptctrl1..15 follow */
 243         OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
 244 };
 245
 246 /**
 247  * hw_read: reads from a hw register
 248  * @reg:  register index
 249  * @mask: bitfield mask
 250  *
 251  * This function returns register contents
 252  */
 253 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
 254 {
 255         return ioread32(ci->hw_bank.regmap[reg]) & mask;
 256 }
 257
 258 #ifdef CONFIG_SOC_IMX28
 259 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 260 {
 261         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 262 }
 263 #else
 264 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
 265 {
 266 }
 267 #endif
 268
 269 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
 270                 void __iomem *addr)
 271 {
 272         if (ci->imx28_write_fix)
 273                 imx28_ci_writel(val, addr);
 274         else
 275                 iowrite32(val, addr);
 276 }
 277
 278 /**
 279  * hw_write: writes to a hw register
 280  * @reg:  register index
 281  * @mask: bitfield mask
 282  * @data: new value
 283  */
 284 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 285                             u32 mask, u32 data)
 286 {
 287         if (~mask)
 288                 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
 289                         | (data & mask);
 290
 291         __hw_write(ci, data, ci->hw_bank.regmap[reg]);
 292 }
 293
 294 /**
 295  * hw_test_and_clear: tests & clears a hw register
 296  * @reg:  register index
 297  * @mask: bitfield mask
 298  *
 299  * This function returns register contents
 300  */
 301 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
 302                                     u32 mask)
 303 {
 304         u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
 305
 306         __hw_write(ci, val, ci->hw_bank.regmap[reg]);
 307         return val;
 308 }
 309
 310 /**
 311  * hw_test_and_write: tests & writes a hw register
 312  * @reg:  register index
 313  * @mask: bitfield mask
 314  * @data: new value
 315  *
 316  * This function returns register contents
 317  */
 318 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
 319                                     u32 mask, u32 data)
 320 {
 321         u32 val = hw_read(ci, reg, ~0);
 322
 323         hw_write(ci, reg, mask, data);
 324         return (val & mask) >> __ffs(mask);
 325 }
 326
 327 int hw_device_reset(struct ci_hdrc *ci, u32 mode);
 328
 329 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
 330
 331 u8 hw_port_test_get(struct ci_hdrc *ci);
 332
 333 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
 334                                 u32 value, unsigned int timeout_ms);
 335
 336 #endif  /* __DRIVERS_USB_CHIPIDEA_CI_H */