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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / usb / chipidea / core.c
blob7e8dceb4c63436dc5d54df6a07d4f116e24dd7ed
1 /*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
45 * - OTG
46 * - Interrupt Traffic
47 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
50 */
51 #include <linux/delay.h>
52 #include <linux/device.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/platform_device.h>
55 #include <linux/module.h>
56 #include <linux/idr.h>
57 #include <linux/interrupt.h>
58 #include <linux/io.h>
59 #include <linux/kernel.h>
60 #include <linux/slab.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/usb/ch9.h>
63 #include <linux/usb/gadget.h>
64 #include <linux/usb/otg.h>
65 #include <linux/usb/chipidea.h>
66 #include <linux/usb/of.h>
67 #include <linux/phy.h>
68 #include <linux/regulator/consumer.h>
69
70 #include "ci.h"
71 #include "udc.h"
72 #include "bits.h"
73 #include "host.h"
74 #include "debug.h"
75 #include "otg.h"
76
77 /* Controller register map */
78 static uintptr_t ci_regs_nolpm[] = {
79 [CAP_CAPLENGTH] = 0x000UL,
80 [CAP_HCCPARAMS] = 0x008UL,
81 [CAP_DCCPARAMS] = 0x024UL,
82 [CAP_TESTMODE] = 0x038UL,
83 [OP_USBCMD] = 0x000UL,
84 [OP_USBSTS] = 0x004UL,
85 [OP_USBINTR] = 0x008UL,
86 [OP_DEVICEADDR] = 0x014UL,
87 [OP_ENDPTLISTADDR] = 0x018UL,
88 [OP_PORTSC] = 0x044UL,
89 [OP_DEVLC] = 0x084UL,
90 [OP_OTGSC] = 0x064UL,
91 [OP_USBMODE] = 0x068UL,
92 [OP_ENDPTSETUPSTAT] = 0x06CUL,
93 [OP_ENDPTPRIME] = 0x070UL,
94 [OP_ENDPTFLUSH] = 0x074UL,
95 [OP_ENDPTSTAT] = 0x078UL,
96 [OP_ENDPTCOMPLETE] = 0x07CUL,
97 [OP_ENDPTCTRL] = 0x080UL,
98 };
99
100 static uintptr_t ci_regs_lpm[] = {
101 [CAP_CAPLENGTH] = 0x000UL,
102 [CAP_HCCPARAMS] = 0x008UL,
103 [CAP_DCCPARAMS] = 0x024UL,
104 [CAP_TESTMODE] = 0x0FCUL,
105 [OP_USBCMD] = 0x000UL,
106 [OP_USBSTS] = 0x004UL,
107 [OP_USBINTR] = 0x008UL,
108 [OP_DEVICEADDR] = 0x014UL,
109 [OP_ENDPTLISTADDR] = 0x018UL,
110 [OP_PORTSC] = 0x044UL,
111 [OP_DEVLC] = 0x084UL,
112 [OP_OTGSC] = 0x0C4UL,
113 [OP_USBMODE] = 0x0C8UL,
114 [OP_ENDPTSETUPSTAT] = 0x0D8UL,
115 [OP_ENDPTPRIME] = 0x0DCUL,
116 [OP_ENDPTFLUSH] = 0x0E0UL,
117 [OP_ENDPTSTAT] = 0x0E4UL,
118 [OP_ENDPTCOMPLETE] = 0x0E8UL,
119 [OP_ENDPTCTRL] = 0x0ECUL,
120 };
121
122 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
123 {
124 int i;
125
126 kfree(ci->hw_bank.regmap);
127
128 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
129 GFP_KERNEL);
130 if (!ci->hw_bank.regmap)
131 return -ENOMEM;
132
133 for (i = 0; i < OP_ENDPTCTRL; i++)
134 ci->hw_bank.regmap[i] =
135 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
136 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
137
138 for (; i <= OP_LAST; i++)
139 ci->hw_bank.regmap[i] = ci->hw_bank.op +
140 4 * (i - OP_ENDPTCTRL) +
141 (is_lpm
142 ? ci_regs_lpm[OP_ENDPTCTRL]
143 : ci_regs_nolpm[OP_ENDPTCTRL]);
144
145 return 0;
146 }
147
148 /**
149 * hw_port_test_set: writes port test mode (execute without interruption)
150 * @mode: new value
151 *
152 * This function returns an error code
153 */
154 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
155 {
156 const u8 TEST_MODE_MAX = 7;
157
158 if (mode > TEST_MODE_MAX)
159 return -EINVAL;
160
161 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
162 return 0;
163 }
164
165 /**
166 * hw_port_test_get: reads port test mode value
167 *
168 * This function returns port test mode value
169 */
170 u8 hw_port_test_get(struct ci_hdrc *ci)
171 {
172 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
173 }
174
175 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
176 {
177 u32 reg;
178
179 /* bank is a module variable */
180 ci->hw_bank.abs = base;
181
182 ci->hw_bank.cap = ci->hw_bank.abs;
183 ci->hw_bank.cap += ci->platdata->capoffset;
184 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
185
186 hw_alloc_regmap(ci, false);
187 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
188 __ffs(HCCPARAMS_LEN);
189 ci->hw_bank.lpm = reg;
190 hw_alloc_regmap(ci, !!reg);
191 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
192 ci->hw_bank.size += OP_LAST;
193 ci->hw_bank.size /= sizeof(u32);
194
195 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
196 __ffs(DCCPARAMS_DEN);
197 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
198
199 if (ci->hw_ep_max > ENDPT_MAX)
200 return -ENODEV;
201
202 /* Disable all interrupts bits */
203 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
204
205 /* Clear all interrupts status bits*/
206 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
207
208 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
209 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
210
211 /* setup lock mode ? */
212
213 /* ENDPTSETUPSTAT is '0' by default */
214
215 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
216
217 return 0;
218 }
219
220 static void hw_phymode_configure(struct ci_hdrc *ci)
221 {
222 u32 portsc, lpm, sts;
223
224 switch (ci->platdata->phy_mode) {
225 case USBPHY_INTERFACE_MODE_UTMI:
226 portsc = PORTSC_PTS(PTS_UTMI);
227 lpm = DEVLC_PTS(PTS_UTMI);
228 break;
229 case USBPHY_INTERFACE_MODE_UTMIW:
230 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
231 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
232 break;
233 case USBPHY_INTERFACE_MODE_ULPI:
234 portsc = PORTSC_PTS(PTS_ULPI);
235 lpm = DEVLC_PTS(PTS_ULPI);
236 break;
237 case USBPHY_INTERFACE_MODE_SERIAL:
238 portsc = PORTSC_PTS(PTS_SERIAL);
239 lpm = DEVLC_PTS(PTS_SERIAL);
240 sts = 1;
241 break;
242 case USBPHY_INTERFACE_MODE_HSIC:
243 portsc = PORTSC_PTS(PTS_HSIC);
244 lpm = DEVLC_PTS(PTS_HSIC);
245 break;
246 default:
247 return;
248 }
249
250 if (ci->hw_bank.lpm) {
251 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
252 hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
253 } else {
254 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
255 hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
256 }
257 }
258
259 /**
260 * hw_device_reset: resets chip (execute without interruption)
261 * @ci: the controller
262 *
263 * This function returns an error code
264 */
265 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
266 {
267 /* should flush & stop before reset */
268 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
269 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
270
271 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
272 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
273 udelay(10); /* not RTOS friendly */
274
275 if (ci->platdata->notify_event)
276 ci->platdata->notify_event(ci,
277 CI_HDRC_CONTROLLER_RESET_EVENT);
278
279 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
280 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
281
282 /* USBMODE should be configured step by step */
283 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
284 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
285 /* HW >= 2.3 */
286 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
287
288 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
289 pr_err("cannot enter in %s mode", ci_role(ci)->name);
290 pr_err("lpm = %i", ci->hw_bank.lpm);
291 return -ENODEV;
292 }
293
294 return 0;
295 }
296
297 /**
298 * hw_wait_reg: wait the register value
299 *
300 * Sometimes, it needs to wait register value before going on.
301 * Eg, when switch to device mode, the vbus value should be lower
302 * than OTGSC_BSV before connects to host.
303 *
304 * @ci: the controller
305 * @reg: register index
306 * @mask: mast bit
307 * @value: the bit value to wait
308 * @timeout_ms: timeout in millisecond
309 *
310 * This function returns an error code if timeout
311 */
312 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
313 u32 value, unsigned int timeout_ms)
314 {
315 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
316
317 while (hw_read(ci, reg, mask) != value) {
318 if (time_after(jiffies, elapse)) {
319 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
320 mask, reg);
321 return -ETIMEDOUT;
322 }
323 msleep(20);
324 }
325
326 return 0;
327 }
328
329 static irqreturn_t ci_irq(int irq, void *data)
330 {
331 struct ci_hdrc *ci = data;
332 irqreturn_t ret = IRQ_NONE;
333 u32 otgsc = 0;
334
335 if (ci->is_otg)
336 otgsc = hw_read(ci, OP_OTGSC, ~0);
337
338 /*
339 * Handle id change interrupt, it indicates device/host function
340 * switch.
341 */
342 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
343 ci->id_event = true;
344 ci_clear_otg_interrupt(ci, OTGSC_IDIS);
345 disable_irq_nosync(ci->irq);
346 queue_work(ci->wq, &ci->work);
347 return IRQ_HANDLED;
348 }
349
350 /*
351 * Handle vbus change interrupt, it indicates device connection
352 * and disconnection events.
353 */
354 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
355 ci->b_sess_valid_event = true;
356 ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
357 disable_irq_nosync(ci->irq);
358 queue_work(ci->wq, &ci->work);
359 return IRQ_HANDLED;
360 }
361
362 /* Handle device/host interrupt */
363 if (ci->role != CI_ROLE_END)
364 ret = ci_role(ci)->irq(ci);
365
366 return ret;
367 }
368
369 static int ci_get_platdata(struct device *dev,
370 struct ci_hdrc_platform_data *platdata)
371 {
372 /* Get the vbus regulator */
373 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
374 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
375 return -EPROBE_DEFER;
376 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
377 platdata->reg_vbus = NULL; /* no vbus regualator is needed */
378 } else if (IS_ERR(platdata->reg_vbus)) {
379 dev_err(dev, "Getting regulator error: %ld\n",
380 PTR_ERR(platdata->reg_vbus));
381 return PTR_ERR(platdata->reg_vbus);
382 }
383
384 return 0;
385 }
386
387 static DEFINE_IDA(ci_ida);
388
389 struct platform_device *ci_hdrc_add_device(struct device *dev,
390 struct resource *res, int nres,
391 struct ci_hdrc_platform_data *platdata)
392 {
393 struct platform_device *pdev;
394 int id, ret;
395
396 ret = ci_get_platdata(dev, platdata);
397 if (ret)
398 return ERR_PTR(ret);
399
400 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
401 if (id < 0)
402 return ERR_PTR(id);
403
404 pdev = platform_device_alloc("ci_hdrc", id);
405 if (!pdev) {
406 ret = -ENOMEM;
407 goto put_id;
408 }
409
410 pdev->dev.parent = dev;
411 pdev->dev.dma_mask = dev->dma_mask;
412 pdev->dev.dma_parms = dev->dma_parms;
413 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
414
415 ret = platform_device_add_resources(pdev, res, nres);
416 if (ret)
417 goto err;
418
419 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
420 if (ret)
421 goto err;
422
423 ret = platform_device_add(pdev);
424 if (ret)
425 goto err;
426
427 return pdev;
428
429 err:
430 platform_device_put(pdev);
431 put_id:
432 ida_simple_remove(&ci_ida, id);
433 return ERR_PTR(ret);
434 }
435 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
436
437 void ci_hdrc_remove_device(struct platform_device *pdev)
438 {
439 int id = pdev->id;
440 platform_device_unregister(pdev);
441 ida_simple_remove(&ci_ida, id);
442 }
443 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
444
445 static inline void ci_role_destroy(struct ci_hdrc *ci)
446 {
447 ci_hdrc_gadget_destroy(ci);
448 ci_hdrc_host_destroy(ci);
449 if (ci->is_otg)
450 ci_hdrc_otg_destroy(ci);
451 }
452
453 static void ci_get_otg_capable(struct ci_hdrc *ci)
454 {
455 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
456 ci->is_otg = false;
457 else
458 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
459 DCCPARAMS_DC | DCCPARAMS_HC)
460 == (DCCPARAMS_DC | DCCPARAMS_HC));
461 if (ci->is_otg) {
462 dev_dbg(ci->dev, "It is OTG capable controller\n");
463 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
464 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
465 }
466 }
467
468 static int ci_hdrc_probe(struct platform_device *pdev)
469 {
470 struct device *dev = &pdev->dev;
471 struct ci_hdrc *ci;
472 struct resource *res;
473 void __iomem *base;
474 int ret;
475 enum usb_dr_mode dr_mode;
476 struct device_node *of_node = dev->of_node ?: dev->parent->of_node;
477
478 if (!dev->platform_data) {
479 dev_err(dev, "platform data missing\n");
480 return -ENODEV;
481 }
482
483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
484 base = devm_ioremap_resource(dev, res);
485 if (IS_ERR(base))
486 return PTR_ERR(base);
487
488 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
489 if (!ci) {
490 dev_err(dev, "can't allocate device\n");
491 return -ENOMEM;
492 }
493
494 ci->dev = dev;
495 ci->platdata = dev->platform_data;
496 if (ci->platdata->phy)
497 ci->transceiver = ci->platdata->phy;
498 else
499 ci->global_phy = true;
500 ci->imx28_write_fix = !!(ci->platdata->flags &
501 CI_HDRC_IMX28_WRITE_FIX);
502
503 ret = hw_device_init(ci, base);
504 if (ret < 0) {
505 dev_err(dev, "can't initialize hardware\n");
506 return -ENODEV;
507 }
508
509 ci->hw_bank.phys = res->start;
510
511 ci->irq = platform_get_irq(pdev, 0);
512 if (ci->irq < 0) {
513 dev_err(dev, "missing IRQ\n");
514 return -ENODEV;
515 }
516
517 ci_get_otg_capable(ci);
518
519 if (!ci->platdata->phy_mode)
520 ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
521
522 hw_phymode_configure(ci);
523
524 if (!ci->platdata->dr_mode)
525 ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);
526
527 if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
528 ci->platdata->dr_mode = USB_DR_MODE_OTG;
529
530 dr_mode = ci->platdata->dr_mode;
531 /* initialize role(s) before the interrupt is requested */
532 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
533 ret = ci_hdrc_host_init(ci);
534 if (ret)
535 dev_info(dev, "doesn't support host\n");
536 }
537
538 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
539 ret = ci_hdrc_gadget_init(ci);
540 if (ret)
541 dev_info(dev, "doesn't support gadget\n");
542 }
543
544 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
545 dev_err(dev, "no supported roles\n");
546 return -ENODEV;
547 }
548
549 if (ci->is_otg) {
550 ret = ci_hdrc_otg_init(ci);
551 if (ret) {
552 dev_err(dev, "init otg fails, ret = %d\n", ret);
553 goto stop;
554 }
555 }
556
557 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
558 if (ci->is_otg) {
559 /*
560 * ID pin needs 1ms debouce time,
561 * we delay 2ms for safe.
562 */
563 mdelay(2);
564 ci->role = ci_otg_role(ci);
565 ci_enable_otg_interrupt(ci, OTGSC_IDIE);
566 } else {
567 /*
568 * If the controller is not OTG capable, but support
569 * role switch, the defalt role is gadget, and the
570 * user can switch it through debugfs.
571 */
572 ci->role = CI_ROLE_GADGET;
573 }
574 } else {
575 ci->role = ci->roles[CI_ROLE_HOST]
576 ? CI_ROLE_HOST
577 : CI_ROLE_GADGET;
578 }
579
580 /* only update vbus status for peripheral */
581 if (ci->role == CI_ROLE_GADGET)
582 ci_handle_vbus_change(ci);
583
584 ret = ci_role_start(ci, ci->role);
585 if (ret) {
586 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
587 goto stop;
588 }
589
590 platform_set_drvdata(pdev, ci);
591 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
592 ci);
593 if (ret)
594 goto stop;
595
596 ret = dbg_create_files(ci);
597 if (!ret)
598 return 0;
599
600 free_irq(ci->irq, ci);
601 stop:
602 ci_role_destroy(ci);
603
604 return ret;
605 }
606
607 static int ci_hdrc_remove(struct platform_device *pdev)
608 {
609 struct ci_hdrc *ci = platform_get_drvdata(pdev);
610
611 dbg_remove_files(ci);
612 free_irq(ci->irq, ci);
613 ci_role_destroy(ci);
614 kfree(ci->hw_bank.regmap);
615
616 return 0;
617 }
618
619 static struct platform_driver ci_hdrc_driver = {
620 .probe = ci_hdrc_probe,
621 .remove = ci_hdrc_remove,
622 .driver = {
623 .name = "ci_hdrc",
624 },
625 };
626
627 module_platform_driver(ci_hdrc_driver);
628
629 MODULE_ALIAS("platform:ci_hdrc");
630 MODULE_LICENSE("GPL v2");
631 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
632 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Linux with added FPC-III support