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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / usb / host / ohci-hcd.c
blob3770fcb55e28762220bda6fde76944609d91640f
1 /*
2 * Open Host Controller Interface (OHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
8 *
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
13 *
14 *
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
19 *
20 * This file is licenced under the GPL.
21 */
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
42
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
47
48
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
61
62 #ifdef __hppa__
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
64 #define IR_DISABLE
65 #endif
66
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
69 #define IR_DISABLE
70 #endif
71
72 /*-------------------------------------------------------------------------*/
73
74 static const char hcd_name [] = "ohci_hcd";
75
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
77
78 #include "ohci.h"
79 #include "pci-quirks.h"
80
81 static void ohci_dump(struct ohci_hcd *ohci);
82 static void ohci_stop(struct usb_hcd *hcd);
83
84 #include "ohci-hub.c"
85 #include "ohci-dbg.c"
86 #include "ohci-mem.c"
87 #include "ohci-q.c"
88
89
90 /*
91 * On architectures with edge-triggered interrupts we must never return
92 * IRQ_NONE.
93 */
94 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
95 #define IRQ_NOTMINE IRQ_HANDLED
96 #else
97 #define IRQ_NOTMINE IRQ_NONE
98 #endif
99
100
101 /* Some boards misreport power switching/overcurrent */
102 static bool distrust_firmware = 1;
103 module_param (distrust_firmware, bool, 0);
104 MODULE_PARM_DESC (distrust_firmware,
105 "true to distrust firmware power/overcurrent setup");
106
107 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
108 static bool no_handshake = 0;
109 module_param (no_handshake, bool, 0);
110 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
111
112 /*-------------------------------------------------------------------------*/
113
114 /*
115 * queue up an urb for anything except the root hub
116 */
117 static int ohci_urb_enqueue (
118 struct usb_hcd *hcd,
119 struct urb *urb,
120 gfp_t mem_flags
121 ) {
122 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
123 struct ed *ed;
124 urb_priv_t *urb_priv;
125 unsigned int pipe = urb->pipe;
126 int i, size = 0;
127 unsigned long flags;
128 int retval = 0;
129
130 #ifdef OHCI_VERBOSE_DEBUG
131 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
132 #endif
133
134 /* every endpoint has a ed, locate and maybe (re)initialize it */
135 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
136 return -ENOMEM;
137
138 /* for the private part of the URB we need the number of TDs (size) */
139 switch (ed->type) {
140 case PIPE_CONTROL:
141 /* td_submit_urb() doesn't yet handle these */
142 if (urb->transfer_buffer_length > 4096)
143 return -EMSGSIZE;
144
145 /* 1 TD for setup, 1 for ACK, plus ... */
146 size = 2;
147 /* FALLTHROUGH */
148 // case PIPE_INTERRUPT:
149 // case PIPE_BULK:
150 default:
151 /* one TD for every 4096 Bytes (can be up to 8K) */
152 size += urb->transfer_buffer_length / 4096;
153 /* ... and for any remaining bytes ... */
154 if ((urb->transfer_buffer_length % 4096) != 0)
155 size++;
156 /* ... and maybe a zero length packet to wrap it up */
157 if (size == 0)
158 size++;
159 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
160 && (urb->transfer_buffer_length
161 % usb_maxpacket (urb->dev, pipe,
162 usb_pipeout (pipe))) == 0)
163 size++;
164 break;
165 case PIPE_ISOCHRONOUS: /* number of packets from URB */
166 size = urb->number_of_packets;
167 break;
168 }
169
170 /* allocate the private part of the URB */
171 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
172 mem_flags);
173 if (!urb_priv)
174 return -ENOMEM;
175 INIT_LIST_HEAD (&urb_priv->pending);
176 urb_priv->length = size;
177 urb_priv->ed = ed;
178
179 /* allocate the TDs (deferring hash chain updates) */
180 for (i = 0; i < size; i++) {
181 urb_priv->td [i] = td_alloc (ohci, mem_flags);
182 if (!urb_priv->td [i]) {
183 urb_priv->length = i;
184 urb_free_priv (ohci, urb_priv);
185 return -ENOMEM;
186 }
187 }
188
189 spin_lock_irqsave (&ohci->lock, flags);
190
191 /* don't submit to a dead HC */
192 if (!HCD_HW_ACCESSIBLE(hcd)) {
193 retval = -ENODEV;
194 goto fail;
195 }
196 if (ohci->rh_state != OHCI_RH_RUNNING) {
197 retval = -ENODEV;
198 goto fail;
199 }
200 retval = usb_hcd_link_urb_to_ep(hcd, urb);
201 if (retval)
202 goto fail;
203
204 /* schedule the ed if needed */
205 if (ed->state == ED_IDLE) {
206 retval = ed_schedule (ohci, ed);
207 if (retval < 0) {
208 usb_hcd_unlink_urb_from_ep(hcd, urb);
209 goto fail;
210 }
211 if (ed->type == PIPE_ISOCHRONOUS) {
212 u16 frame = ohci_frame_no(ohci);
213
214 /* delay a few frames before the first TD */
215 frame += max_t (u16, 8, ed->interval);
216 frame &= ~(ed->interval - 1);
217 frame |= ed->branch;
218 urb->start_frame = frame;
219 ed->last_iso = frame + ed->interval * (size - 1);
220 }
221 } else if (ed->type == PIPE_ISOCHRONOUS) {
222 u16 next = ohci_frame_no(ohci) + 1;
223 u16 frame = ed->last_iso + ed->interval;
224 u16 length = ed->interval * (size - 1);
225
226 /* Behind the scheduling threshold? */
227 if (unlikely(tick_before(frame, next))) {
228
229 /* URB_ISO_ASAP: Round up to the first available slot */
230 if (urb->transfer_flags & URB_ISO_ASAP) {
231 frame += (next - frame + ed->interval - 1) &
232 -ed->interval;
233
234 /*
235 * Not ASAP: Use the next slot in the stream,
236 * no matter what.
237 */
238 } else {
239 /*
240 * Some OHCI hardware doesn't handle late TDs
241 * correctly. After retiring them it proceeds
242 * to the next ED instead of the next TD.
243 * Therefore we have to omit the late TDs
244 * entirely.
245 */
246 urb_priv->td_cnt = DIV_ROUND_UP(
247 (u16) (next - frame),
248 ed->interval);
249 if (urb_priv->td_cnt >= urb_priv->length) {
250 ++urb_priv->td_cnt; /* Mark it */
251 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
252 urb, frame, length,
253 next);
254 }
255 }
256 }
257 urb->start_frame = frame;
258 ed->last_iso = frame + length;
259 }
260
261 /* fill the TDs and link them to the ed; and
262 * enable that part of the schedule, if needed
263 * and update count of queued periodic urbs
264 */
265 urb->hcpriv = urb_priv;
266 td_submit_urb (ohci, urb);
267
268 fail:
269 if (retval)
270 urb_free_priv (ohci, urb_priv);
271 spin_unlock_irqrestore (&ohci->lock, flags);
272 return retval;
273 }
274
275 /*
276 * decouple the URB from the HC queues (TDs, urb_priv).
277 * reporting is always done
278 * asynchronously, and we might be dealing with an urb that's
279 * partially transferred, or an ED with other urbs being unlinked.
280 */
281 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
282 {
283 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
284 unsigned long flags;
285 int rc;
286
287 #ifdef OHCI_VERBOSE_DEBUG
288 urb_print(urb, "UNLINK", 1, status);
289 #endif
290
291 spin_lock_irqsave (&ohci->lock, flags);
292 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
293 if (rc) {
294 ; /* Do nothing */
295 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
296 urb_priv_t *urb_priv;
297
298 /* Unless an IRQ completed the unlink while it was being
299 * handed to us, flag it for unlink and giveback, and force
300 * some upcoming INTR_SF to call finish_unlinks()
301 */
302 urb_priv = urb->hcpriv;
303 if (urb_priv) {
304 if (urb_priv->ed->state == ED_OPER)
305 start_ed_unlink (ohci, urb_priv->ed);
306 }
307 } else {
308 /*
309 * with HC dead, we won't respect hc queue pointers
310 * any more ... just clean up every urb's memory.
311 */
312 if (urb->hcpriv)
313 finish_urb(ohci, urb, status);
314 }
315 spin_unlock_irqrestore (&ohci->lock, flags);
316 return rc;
317 }
318
319 /*-------------------------------------------------------------------------*/
320
321 /* frees config/altsetting state for endpoints,
322 * including ED memory, dummy TD, and bulk/intr data toggle
323 */
324
325 static void
326 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
327 {
328 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
329 unsigned long flags;
330 struct ed *ed = ep->hcpriv;
331 unsigned limit = 1000;
332
333 /* ASSERT: any requests/urbs are being unlinked */
334 /* ASSERT: nobody can be submitting urbs for this any more */
335
336 if (!ed)
337 return;
338
339 rescan:
340 spin_lock_irqsave (&ohci->lock, flags);
341
342 if (ohci->rh_state != OHCI_RH_RUNNING) {
343 sanitize:
344 ed->state = ED_IDLE;
345 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
346 ohci->eds_scheduled--;
347 finish_unlinks (ohci, 0);
348 }
349
350 switch (ed->state) {
351 case ED_UNLINK: /* wait for hw to finish? */
352 /* major IRQ delivery trouble loses INTR_SF too... */
353 if (limit-- == 0) {
354 ohci_warn(ohci, "ED unlink timeout\n");
355 if (quirk_zfmicro(ohci)) {
356 ohci_warn(ohci, "Attempting ZF TD recovery\n");
357 ohci->ed_to_check = ed;
358 ohci->zf_delay = 2;
359 }
360 goto sanitize;
361 }
362 spin_unlock_irqrestore (&ohci->lock, flags);
363 schedule_timeout_uninterruptible(1);
364 goto rescan;
365 case ED_IDLE: /* fully unlinked */
366 if (list_empty (&ed->td_list)) {
367 td_free (ohci, ed->dummy);
368 ed_free (ohci, ed);
369 break;
370 }
371 /* else FALL THROUGH */
372 default:
373 /* caller was supposed to have unlinked any requests;
374 * that's not our job. can't recover; must leak ed.
375 */
376 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
377 ed, ep->desc.bEndpointAddress, ed->state,
378 list_empty (&ed->td_list) ? "" : " (has tds)");
379 td_free (ohci, ed->dummy);
380 break;
381 }
382 ep->hcpriv = NULL;
383 spin_unlock_irqrestore (&ohci->lock, flags);
384 }
385
386 static int ohci_get_frame (struct usb_hcd *hcd)
387 {
388 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
389
390 return ohci_frame_no(ohci);
391 }
392
393 static void ohci_usb_reset (struct ohci_hcd *ohci)
394 {
395 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
396 ohci->hc_control &= OHCI_CTRL_RWC;
397 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
398 ohci->rh_state = OHCI_RH_HALTED;
399 }
400
401 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
402 * other cases where the next software may expect clean state from the
403 * "firmware". this is bus-neutral, unlike shutdown() methods.
404 */
405 static void
406 ohci_shutdown (struct usb_hcd *hcd)
407 {
408 struct ohci_hcd *ohci;
409
410 ohci = hcd_to_ohci (hcd);
411 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
412
413 /* Software reset, after which the controller goes into SUSPEND */
414 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
415 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
416 udelay(10);
417
418 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
419 }
420
421 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
422 {
423 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
424 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
425 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
426 && !list_empty(&ed->td_list);
427 }
428
429 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
430 * an interrupt TD but neglects to add it to the donelist. On systems with
431 * this chipset, we need to periodically check the state of the queues to look
432 * for such "lost" TDs.
433 */
434 static void unlink_watchdog_func(unsigned long _ohci)
435 {
436 unsigned long flags;
437 unsigned max;
438 unsigned seen_count = 0;
439 unsigned i;
440 struct ed **seen = NULL;
441 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
442
443 spin_lock_irqsave(&ohci->lock, flags);
444 max = ohci->eds_scheduled;
445 if (!max)
446 goto done;
447
448 if (ohci->ed_to_check)
449 goto out;
450
451 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
452 if (!seen)
453 goto out;
454
455 for (i = 0; i < NUM_INTS; i++) {
456 struct ed *ed = ohci->periodic[i];
457
458 while (ed) {
459 unsigned temp;
460
461 /* scan this branch of the periodic schedule tree */
462 for (temp = 0; temp < seen_count; temp++) {
463 if (seen[temp] == ed) {
464 /* we've checked it and what's after */
465 ed = NULL;
466 break;
467 }
468 }
469 if (!ed)
470 break;
471 seen[seen_count++] = ed;
472 if (!check_ed(ohci, ed)) {
473 ed = ed->ed_next;
474 continue;
475 }
476
477 /* HC's TD list is empty, but HCD sees at least one
478 * TD that's not been sent through the donelist.
479 */
480 ohci->ed_to_check = ed;
481 ohci->zf_delay = 2;
482
483 /* The HC may wait until the next frame to report the
484 * TD as done through the donelist and INTR_WDH. (We
485 * just *assume* it's not a multi-TD interrupt URB;
486 * those could defer the IRQ more than one frame, using
487 * DI...) Check again after the next INTR_SF.
488 */
489 ohci_writel(ohci, OHCI_INTR_SF,
490 &ohci->regs->intrstatus);
491 ohci_writel(ohci, OHCI_INTR_SF,
492 &ohci->regs->intrenable);
493
494 /* flush those writes */
495 (void) ohci_readl(ohci, &ohci->regs->control);
496
497 goto out;
498 }
499 }
500 out:
501 kfree(seen);
502 if (ohci->eds_scheduled)
503 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
504 done:
505 spin_unlock_irqrestore(&ohci->lock, flags);
506 }
507
508 /*-------------------------------------------------------------------------*
509 * HC functions
510 *-------------------------------------------------------------------------*/
511
512 /* init memory, and kick BIOS/SMM off */
513
514 static int ohci_init (struct ohci_hcd *ohci)
515 {
516 int ret;
517 struct usb_hcd *hcd = ohci_to_hcd(ohci);
518
519 if (distrust_firmware)
520 ohci->flags |= OHCI_QUIRK_HUB_POWER;
521
522 ohci->rh_state = OHCI_RH_HALTED;
523 ohci->regs = hcd->regs;
524
525 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
526 * was never needed for most non-PCI systems ... remove the code?
527 */
528
529 #ifndef IR_DISABLE
530 /* SMM owns the HC? not for long! */
531 if (!no_handshake && ohci_readl (ohci,
532 &ohci->regs->control) & OHCI_CTRL_IR) {
533 u32 temp;
534
535 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
536
537 /* this timeout is arbitrary. we make it long, so systems
538 * depending on usb keyboards may be usable even if the
539 * BIOS/SMM code seems pretty broken.
540 */
541 temp = 500; /* arbitrary: five seconds */
542
543 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
544 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
545 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
546 msleep (10);
547 if (--temp == 0) {
548 ohci_err (ohci, "USB HC takeover failed!"
549 " (BIOS/SMM bug)\n");
550 return -EBUSY;
551 }
552 }
553 ohci_usb_reset (ohci);
554 }
555 #endif
556
557 /* Disable HC interrupts */
558 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
559
560 /* flush the writes, and save key bits like RWC */
561 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
562 ohci->hc_control |= OHCI_CTRL_RWC;
563
564 /* Read the number of ports unless overridden */
565 if (ohci->num_ports == 0)
566 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
567
568 if (ohci->hcca)
569 return 0;
570
571 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
572 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
573 if (!ohci->hcca)
574 return -ENOMEM;
575
576 if ((ret = ohci_mem_init (ohci)) < 0)
577 ohci_stop (hcd);
578 else {
579 create_debug_files (ohci);
580 }
581
582 return ret;
583 }
584
585 /*-------------------------------------------------------------------------*/
586
587 /* Start an OHCI controller, set the BUS operational
588 * resets USB and controller
589 * enable interrupts
590 */
591 static int ohci_run (struct ohci_hcd *ohci)
592 {
593 u32 mask, val;
594 int first = ohci->fminterval == 0;
595 struct usb_hcd *hcd = ohci_to_hcd(ohci);
596
597 ohci->rh_state = OHCI_RH_HALTED;
598
599 /* boot firmware should have set this up (5.1.1.3.1) */
600 if (first) {
601
602 val = ohci_readl (ohci, &ohci->regs->fminterval);
603 ohci->fminterval = val & 0x3fff;
604 if (ohci->fminterval != FI)
605 ohci_dbg (ohci, "fminterval delta %d\n",
606 ohci->fminterval - FI);
607 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
608 /* also: power/overcurrent flags in roothub.a */
609 }
610
611 /* Reset USB nearly "by the book". RemoteWakeupConnected has
612 * to be checked in case boot firmware (BIOS/SMM/...) has set up
613 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
614 * If the bus glue detected wakeup capability then it should
615 * already be enabled; if so we'll just enable it again.
616 */
617 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
618 device_set_wakeup_capable(hcd->self.controller, 1);
619
620 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
621 case OHCI_USB_OPER:
622 val = 0;
623 break;
624 case OHCI_USB_SUSPEND:
625 case OHCI_USB_RESUME:
626 ohci->hc_control &= OHCI_CTRL_RWC;
627 ohci->hc_control |= OHCI_USB_RESUME;
628 val = 10 /* msec wait */;
629 break;
630 // case OHCI_USB_RESET:
631 default:
632 ohci->hc_control &= OHCI_CTRL_RWC;
633 ohci->hc_control |= OHCI_USB_RESET;
634 val = 50 /* msec wait */;
635 break;
636 }
637 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
638 // flush the writes
639 (void) ohci_readl (ohci, &ohci->regs->control);
640 msleep(val);
641
642 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
643
644 /* 2msec timelimit here means no irqs/preempt */
645 spin_lock_irq (&ohci->lock);
646
647 retry:
648 /* HC Reset requires max 10 us delay */
649 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
650 val = 30; /* ... allow extra time */
651 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
652 if (--val == 0) {
653 spin_unlock_irq (&ohci->lock);
654 ohci_err (ohci, "USB HC reset timed out!\n");
655 return -1;
656 }
657 udelay (1);
658 }
659
660 /* now we're in the SUSPEND state ... must go OPERATIONAL
661 * within 2msec else HC enters RESUME
662 *
663 * ... but some hardware won't init fmInterval "by the book"
664 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
665 * this if we write fmInterval after we're OPERATIONAL.
666 * Unclear about ALi, ServerWorks, and others ... this could
667 * easily be a longstanding bug in chip init on Linux.
668 */
669 if (ohci->flags & OHCI_QUIRK_INITRESET) {
670 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
671 // flush those writes
672 (void) ohci_readl (ohci, &ohci->regs->control);
673 }
674
675 /* Tell the controller where the control and bulk lists are
676 * The lists are empty now. */
677 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
678 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
679
680 /* a reset clears this */
681 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
682
683 periodic_reinit (ohci);
684
685 /* some OHCI implementations are finicky about how they init.
686 * bogus values here mean not even enumeration could work.
687 */
688 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
689 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
690 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
691 ohci->flags |= OHCI_QUIRK_INITRESET;
692 ohci_dbg (ohci, "enabling initreset quirk\n");
693 goto retry;
694 }
695 spin_unlock_irq (&ohci->lock);
696 ohci_err (ohci, "init err (%08x %04x)\n",
697 ohci_readl (ohci, &ohci->regs->fminterval),
698 ohci_readl (ohci, &ohci->regs->periodicstart));
699 return -EOVERFLOW;
700 }
701
702 /* use rhsc irqs after khubd is fully initialized */
703 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
704 hcd->uses_new_polling = 1;
705
706 /* start controller operations */
707 ohci->hc_control &= OHCI_CTRL_RWC;
708 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
709 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
710 ohci->rh_state = OHCI_RH_RUNNING;
711
712 /* wake on ConnectStatusChange, matching external hubs */
713 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
714
715 /* Choose the interrupts we care about now, others later on demand */
716 mask = OHCI_INTR_INIT;
717 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
718 ohci_writel (ohci, mask, &ohci->regs->intrenable);
719
720 /* handle root hub init quirks ... */
721 val = roothub_a (ohci);
722 val &= ~(RH_A_PSM | RH_A_OCPM);
723 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
724 /* NSC 87560 and maybe others */
725 val |= RH_A_NOCP;
726 val &= ~(RH_A_POTPGT | RH_A_NPS);
727 ohci_writel (ohci, val, &ohci->regs->roothub.a);
728 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
729 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
730 /* hub power always on; required for AMD-756 and some
731 * Mac platforms. ganged overcurrent reporting, if any.
732 */
733 val |= RH_A_NPS;
734 ohci_writel (ohci, val, &ohci->regs->roothub.a);
735 }
736 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
737 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
738 &ohci->regs->roothub.b);
739 // flush those writes
740 (void) ohci_readl (ohci, &ohci->regs->control);
741
742 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
743 spin_unlock_irq (&ohci->lock);
744
745 // POTPGT delay is bits 24-31, in 2 ms units.
746 mdelay ((val >> 23) & 0x1fe);
747
748 if (quirk_zfmicro(ohci)) {
749 /* Create timer to watch for bad queue state on ZF Micro */
750 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
751 (unsigned long) ohci);
752
753 ohci->eds_scheduled = 0;
754 ohci->ed_to_check = NULL;
755 }
756
757 ohci_dump(ohci);
758
759 return 0;
760 }
761
762 /* ohci_setup routine for generic controller initialization */
763
764 int ohci_setup(struct usb_hcd *hcd)
765 {
766 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
767
768 ohci_hcd_init(ohci);
769
770 return ohci_init(ohci);
771 }
772 EXPORT_SYMBOL_GPL(ohci_setup);
773
774 /* ohci_start routine for generic controller start of all OHCI bus glue */
775 static int ohci_start(struct usb_hcd *hcd)
776 {
777 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
778 int ret;
779
780 ret = ohci_run(ohci);
781 if (ret < 0) {
782 ohci_err(ohci, "can't start\n");
783 ohci_stop(hcd);
784 }
785 return ret;
786 }
787
788 /*-------------------------------------------------------------------------*/
789
790 /* an interrupt happens */
791
792 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
793 {
794 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
795 struct ohci_regs __iomem *regs = ohci->regs;
796 int ints;
797
798 /* Read interrupt status (and flush pending writes). We ignore the
799 * optimization of checking the LSB of hcca->done_head; it doesn't
800 * work on all systems (edge triggering for OHCI can be a factor).
801 */
802 ints = ohci_readl(ohci, &regs->intrstatus);
803
804 /* Check for an all 1's result which is a typical consequence
805 * of dead, unclocked, or unplugged (CardBus...) devices
806 */
807 if (ints == ~(u32)0) {
808 ohci->rh_state = OHCI_RH_HALTED;
809 ohci_dbg (ohci, "device removed!\n");
810 usb_hc_died(hcd);
811 return IRQ_HANDLED;
812 }
813
814 /* We only care about interrupts that are enabled */
815 ints &= ohci_readl(ohci, &regs->intrenable);
816
817 /* interrupt for some other device? */
818 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
819 return IRQ_NOTMINE;
820
821 if (ints & OHCI_INTR_UE) {
822 // e.g. due to PCI Master/Target Abort
823 if (quirk_nec(ohci)) {
824 /* Workaround for a silicon bug in some NEC chips used
825 * in Apple's PowerBooks. Adapted from Darwin code.
826 */
827 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
828
829 ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
830
831 schedule_work (&ohci->nec_work);
832 } else {
833 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
834 ohci->rh_state = OHCI_RH_HALTED;
835 usb_hc_died(hcd);
836 }
837
838 ohci_dump(ohci);
839 ohci_usb_reset (ohci);
840 }
841
842 if (ints & OHCI_INTR_RHSC) {
843 ohci_vdbg(ohci, "rhsc\n");
844 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
845 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
846 &regs->intrstatus);
847
848 /* NOTE: Vendors didn't always make the same implementation
849 * choices for RHSC. Many followed the spec; RHSC triggers
850 * on an edge, like setting and maybe clearing a port status
851 * change bit. With others it's level-triggered, active
852 * until khubd clears all the port status change bits. We'll
853 * always disable it here and rely on polling until khubd
854 * re-enables it.
855 */
856 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
857 usb_hcd_poll_rh_status(hcd);
858 }
859
860 /* For connect and disconnect events, we expect the controller
861 * to turn on RHSC along with RD. But for remote wakeup events
862 * this might not happen.
863 */
864 else if (ints & OHCI_INTR_RD) {
865 ohci_vdbg(ohci, "resume detect\n");
866 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
867 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
868 if (ohci->autostop) {
869 spin_lock (&ohci->lock);
870 ohci_rh_resume (ohci);
871 spin_unlock (&ohci->lock);
872 } else
873 usb_hcd_resume_root_hub(hcd);
874 }
875
876 if (ints & OHCI_INTR_WDH) {
877 spin_lock (&ohci->lock);
878 dl_done_list (ohci);
879 spin_unlock (&ohci->lock);
880 }
881
882 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
883 spin_lock(&ohci->lock);
884 if (ohci->ed_to_check) {
885 struct ed *ed = ohci->ed_to_check;
886
887 if (check_ed(ohci, ed)) {
888 /* HC thinks the TD list is empty; HCD knows
889 * at least one TD is outstanding
890 */
891 if (--ohci->zf_delay == 0) {
892 struct td *td = list_entry(
893 ed->td_list.next,
894 struct td, td_list);
895 ohci_warn(ohci,
896 "Reclaiming orphan TD %p\n",
897 td);
898 takeback_td(ohci, td);
899 ohci->ed_to_check = NULL;
900 }
901 } else
902 ohci->ed_to_check = NULL;
903 }
904 spin_unlock(&ohci->lock);
905 }
906
907 /* could track INTR_SO to reduce available PCI/... bandwidth */
908
909 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
910 * when there's still unlinking to be done (next frame).
911 */
912 spin_lock (&ohci->lock);
913 if (ohci->ed_rm_list)
914 finish_unlinks (ohci, ohci_frame_no(ohci));
915 if ((ints & OHCI_INTR_SF) != 0
916 && !ohci->ed_rm_list
917 && !ohci->ed_to_check
918 && ohci->rh_state == OHCI_RH_RUNNING)
919 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
920 spin_unlock (&ohci->lock);
921
922 if (ohci->rh_state == OHCI_RH_RUNNING) {
923 ohci_writel (ohci, ints, &regs->intrstatus);
924 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
925 // flush those writes
926 (void) ohci_readl (ohci, &ohci->regs->control);
927 }
928
929 return IRQ_HANDLED;
930 }
931
932 /*-------------------------------------------------------------------------*/
933
934 static void ohci_stop (struct usb_hcd *hcd)
935 {
936 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
937
938 ohci_dump(ohci);
939
940 if (quirk_nec(ohci))
941 flush_work(&ohci->nec_work);
942
943 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
944 ohci_usb_reset(ohci);
945 free_irq(hcd->irq, hcd);
946 hcd->irq = 0;
947
948 if (quirk_zfmicro(ohci))
949 del_timer(&ohci->unlink_watchdog);
950 if (quirk_amdiso(ohci))
951 usb_amd_dev_put();
952
953 remove_debug_files (ohci);
954 ohci_mem_cleanup (ohci);
955 if (ohci->hcca) {
956 dma_free_coherent (hcd->self.controller,
957 sizeof *ohci->hcca,
958 ohci->hcca, ohci->hcca_dma);
959 ohci->hcca = NULL;
960 ohci->hcca_dma = 0;
961 }
962 }
963
964 /*-------------------------------------------------------------------------*/
965
966 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
967
968 /* must not be called from interrupt context */
969 int ohci_restart(struct ohci_hcd *ohci)
970 {
971 int temp;
972 int i;
973 struct urb_priv *priv;
974
975 ohci_init(ohci);
976 spin_lock_irq(&ohci->lock);
977 ohci->rh_state = OHCI_RH_HALTED;
978
979 /* Recycle any "live" eds/tds (and urbs). */
980 if (!list_empty (&ohci->pending))
981 ohci_dbg(ohci, "abort schedule...\n");
982 list_for_each_entry (priv, &ohci->pending, pending) {
983 struct urb *urb = priv->td[0]->urb;
984 struct ed *ed = priv->ed;
985
986 switch (ed->state) {
987 case ED_OPER:
988 ed->state = ED_UNLINK;
989 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
990 ed_deschedule (ohci, ed);
991
992 ed->ed_next = ohci->ed_rm_list;
993 ed->ed_prev = NULL;
994 ohci->ed_rm_list = ed;
995 /* FALLTHROUGH */
996 case ED_UNLINK:
997 break;
998 default:
999 ohci_dbg(ohci, "bogus ed %p state %d\n",
1000 ed, ed->state);
1001 }
1002
1003 if (!urb->unlinked)
1004 urb->unlinked = -ESHUTDOWN;
1005 }
1006 finish_unlinks (ohci, 0);
1007 spin_unlock_irq(&ohci->lock);
1008
1009 /* paranoia, in case that didn't work: */
1010
1011 /* empty the interrupt branches */
1012 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1013 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1014
1015 /* no EDs to remove */
1016 ohci->ed_rm_list = NULL;
1017
1018 /* empty control and bulk lists */
1019 ohci->ed_controltail = NULL;
1020 ohci->ed_bulktail = NULL;
1021
1022 if ((temp = ohci_run (ohci)) < 0) {
1023 ohci_err (ohci, "can't restart, %d\n", temp);
1024 return temp;
1025 }
1026 ohci_dbg(ohci, "restart complete\n");
1027 return 0;
1028 }
1029 EXPORT_SYMBOL_GPL(ohci_restart);
1030
1031 #endif
1032
1033 #ifdef CONFIG_PM
1034
1035 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1036 {
1037 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1038 unsigned long flags;
1039
1040 /* Disable irq emission and mark HW unaccessible. Use
1041 * the spinlock to properly synchronize with possible pending
1042 * RH suspend or resume activity.
1043 */
1044 spin_lock_irqsave (&ohci->lock, flags);
1045 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1046 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1047
1048 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1049 spin_unlock_irqrestore (&ohci->lock, flags);
1050
1051 return 0;
1052 }
1053 EXPORT_SYMBOL_GPL(ohci_suspend);
1054
1055
1056 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1057 {
1058 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1059 int port;
1060 bool need_reinit = false;
1061
1062 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1063
1064 /* Make sure resume from hibernation re-enumerates everything */
1065 if (hibernated)
1066 ohci_usb_reset(ohci);
1067
1068 /* See if the controller is already running or has been reset */
1069 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1070 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1071 need_reinit = true;
1072 } else {
1073 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1074 case OHCI_USB_OPER:
1075 case OHCI_USB_RESET:
1076 need_reinit = true;
1077 }
1078 }
1079
1080 /* If needed, reinitialize and suspend the root hub */
1081 if (need_reinit) {
1082 spin_lock_irq(&ohci->lock);
1083 ohci_rh_resume(ohci);
1084 ohci_rh_suspend(ohci, 0);
1085 spin_unlock_irq(&ohci->lock);
1086 }
1087
1088 /* Normally just turn on port power and enable interrupts */
1089 else {
1090 ohci_dbg(ohci, "powerup ports\n");
1091 for (port = 0; port < ohci->num_ports; port++)
1092 ohci_writel(ohci, RH_PS_PPS,
1093 &ohci->regs->roothub.portstatus[port]);
1094
1095 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1096 ohci_readl(ohci, &ohci->regs->intrenable);
1097 msleep(20);
1098 }
1099
1100 usb_hcd_resume_root_hub(hcd);
1101
1102 return 0;
1103 }
1104 EXPORT_SYMBOL_GPL(ohci_resume);
1105
1106 #endif
1107
1108 /*-------------------------------------------------------------------------*/
1109
1110 /*
1111 * Generic structure: This gets copied for platform drivers so that
1112 * individual entries can be overridden as needed.
1113 */
1114
1115 static const struct hc_driver ohci_hc_driver = {
1116 .description = hcd_name,
1117 .product_desc = "OHCI Host Controller",
1118 .hcd_priv_size = sizeof(struct ohci_hcd),
1119
1120 /*
1121 * generic hardware linkage
1122 */
1123 .irq = ohci_irq,
1124 .flags = HCD_MEMORY | HCD_USB11,
1125
1126 /*
1127 * basic lifecycle operations
1128 */
1129 .reset = ohci_setup,
1130 .start = ohci_start,
1131 .stop = ohci_stop,
1132 .shutdown = ohci_shutdown,
1133
1134 /*
1135 * managing i/o requests and associated device resources
1136 */
1137 .urb_enqueue = ohci_urb_enqueue,
1138 .urb_dequeue = ohci_urb_dequeue,
1139 .endpoint_disable = ohci_endpoint_disable,
1140
1141 /*
1142 * scheduling support
1143 */
1144 .get_frame_number = ohci_get_frame,
1145
1146 /*
1147 * root hub support
1148 */
1149 .hub_status_data = ohci_hub_status_data,
1150 .hub_control = ohci_hub_control,
1151 #ifdef CONFIG_PM
1152 .bus_suspend = ohci_bus_suspend,
1153 .bus_resume = ohci_bus_resume,
1154 #endif
1155 .start_port_reset = ohci_start_port_reset,
1156 };
1157
1158 void ohci_init_driver(struct hc_driver *drv,
1159 const struct ohci_driver_overrides *over)
1160 {
1161 /* Copy the generic table to drv and then apply the overrides */
1162 *drv = ohci_hc_driver;
1163
1164 drv->product_desc = over->product_desc;
1165 drv->hcd_priv_size += over->extra_priv_size;
1166 if (over->reset)
1167 drv->reset = over->reset;
1168 }
1169 EXPORT_SYMBOL_GPL(ohci_init_driver);
1170
1171 /*-------------------------------------------------------------------------*/
1172
1173 MODULE_AUTHOR (DRIVER_AUTHOR);
1174 MODULE_DESCRIPTION(DRIVER_DESC);
1175 MODULE_LICENSE ("GPL");
1176
1177 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1178 #include "ohci-sa1111.c"
1179 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1180 #endif
1181
1182 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1183 #include "ohci-s3c2410.c"
1184 #define S3C2410_PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1185 #endif
1186
1187 #ifdef CONFIG_USB_OHCI_EXYNOS
1188 #include "ohci-exynos.c"
1189 #define EXYNOS_PLATFORM_DRIVER exynos_ohci_driver
1190 #endif
1191
1192 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1193 #include "ohci-omap.c"
1194 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1195 #endif
1196
1197 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1198 #include "ohci-omap3.c"
1199 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1200 #endif
1201
1202 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1203 #include "ohci-pxa27x.c"
1204 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1205 #endif
1206
1207 #ifdef CONFIG_ARCH_EP93XX
1208 #include "ohci-ep93xx.c"
1209 #define EP93XX_PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1210 #endif
1211
1212 #ifdef CONFIG_ARCH_AT91
1213 #include "ohci-at91.c"
1214 #define AT91_PLATFORM_DRIVER ohci_hcd_at91_driver
1215 #endif
1216
1217 #ifdef CONFIG_ARCH_LPC32XX
1218 #include "ohci-nxp.c"
1219 #define NXP_PLATFORM_DRIVER usb_hcd_nxp_driver
1220 #endif
1221
1222 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1223 #include "ohci-da8xx.c"
1224 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1225 #endif
1226
1227 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1228 #include "ohci-ppc-of.c"
1229 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1230 #endif
1231
1232 #ifdef CONFIG_PLAT_SPEAR
1233 #include "ohci-spear.c"
1234 #define SPEAR_PLATFORM_DRIVER spear_ohci_hcd_driver
1235 #endif
1236
1237 #ifdef CONFIG_PPC_PS3
1238 #include "ohci-ps3.c"
1239 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1240 #endif
1241
1242 #ifdef CONFIG_MFD_SM501
1243 #include "ohci-sm501.c"
1244 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1245 #endif
1246
1247 #ifdef CONFIG_MFD_TC6393XB
1248 #include "ohci-tmio.c"
1249 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1250 #endif
1251
1252 #ifdef CONFIG_MACH_JZ4740
1253 #include "ohci-jz4740.c"
1254 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1255 #endif
1256
1257 #ifdef CONFIG_USB_OCTEON_OHCI
1258 #include "ohci-octeon.c"
1259 #define PLATFORM_DRIVER ohci_octeon_driver
1260 #endif
1261
1262 #ifdef CONFIG_TILE_USB
1263 #include "ohci-tilegx.c"
1264 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1265 #endif
1266
1267 static int __init ohci_hcd_mod_init(void)
1268 {
1269 int retval = 0;
1270
1271 if (usb_disabled())
1272 return -ENODEV;
1273
1274 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1275 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1276 sizeof (struct ed), sizeof (struct td));
1277 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1278
1279 #ifdef DEBUG
1280 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1281 if (!ohci_debug_root) {
1282 retval = -ENOENT;
1283 goto error_debug;
1284 }
1285 #endif
1286
1287 #ifdef PS3_SYSTEM_BUS_DRIVER
1288 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1289 if (retval < 0)
1290 goto error_ps3;
1291 #endif
1292
1293 #ifdef PLATFORM_DRIVER
1294 retval = platform_driver_register(&PLATFORM_DRIVER);
1295 if (retval < 0)
1296 goto error_platform;
1297 #endif
1298
1299 #ifdef OMAP1_PLATFORM_DRIVER
1300 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1301 if (retval < 0)
1302 goto error_omap1_platform;
1303 #endif
1304
1305 #ifdef OMAP3_PLATFORM_DRIVER
1306 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1307 if (retval < 0)
1308 goto error_omap3_platform;
1309 #endif
1310
1311 #ifdef OF_PLATFORM_DRIVER
1312 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1313 if (retval < 0)
1314 goto error_of_platform;
1315 #endif
1316
1317 #ifdef SA1111_DRIVER
1318 retval = sa1111_driver_register(&SA1111_DRIVER);
1319 if (retval < 0)
1320 goto error_sa1111;
1321 #endif
1322
1323 #ifdef SM501_OHCI_DRIVER
1324 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1325 if (retval < 0)
1326 goto error_sm501;
1327 #endif
1328
1329 #ifdef TMIO_OHCI_DRIVER
1330 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1331 if (retval < 0)
1332 goto error_tmio;
1333 #endif
1334
1335 #ifdef S3C2410_PLATFORM_DRIVER
1336 retval = platform_driver_register(&S3C2410_PLATFORM_DRIVER);
1337 if (retval < 0)
1338 goto error_s3c2410;
1339 #endif
1340
1341 #ifdef EXYNOS_PLATFORM_DRIVER
1342 retval = platform_driver_register(&EXYNOS_PLATFORM_DRIVER);
1343 if (retval < 0)
1344 goto error_exynos;
1345 #endif
1346
1347 #ifdef EP93XX_PLATFORM_DRIVER
1348 retval = platform_driver_register(&EP93XX_PLATFORM_DRIVER);
1349 if (retval < 0)
1350 goto error_ep93xx;
1351 #endif
1352
1353 #ifdef AT91_PLATFORM_DRIVER
1354 retval = platform_driver_register(&AT91_PLATFORM_DRIVER);
1355 if (retval < 0)
1356 goto error_at91;
1357 #endif
1358
1359 #ifdef NXP_PLATFORM_DRIVER
1360 retval = platform_driver_register(&NXP_PLATFORM_DRIVER);
1361 if (retval < 0)
1362 goto error_nxp;
1363 #endif
1364
1365 #ifdef DAVINCI_PLATFORM_DRIVER
1366 retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1367 if (retval < 0)
1368 goto error_davinci;
1369 #endif
1370
1371 #ifdef SPEAR_PLATFORM_DRIVER
1372 retval = platform_driver_register(&SPEAR_PLATFORM_DRIVER);
1373 if (retval < 0)
1374 goto error_spear;
1375 #endif
1376
1377 return retval;
1378
1379 /* Error path */
1380 #ifdef SPEAR_PLATFORM_DRIVER
1381 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1382 error_spear:
1383 #endif
1384 #ifdef DAVINCI_PLATFORM_DRIVER
1385 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1386 error_davinci:
1387 #endif
1388 #ifdef NXP_PLATFORM_DRIVER
1389 platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1390 error_nxp:
1391 #endif
1392 #ifdef AT91_PLATFORM_DRIVER
1393 platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1394 error_at91:
1395 #endif
1396 #ifdef EP93XX_PLATFORM_DRIVER
1397 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1398 error_ep93xx:
1399 #endif
1400 #ifdef EXYNOS_PLATFORM_DRIVER
1401 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1402 error_exynos:
1403 #endif
1404 #ifdef S3C2410_PLATFORM_DRIVER
1405 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1406 error_s3c2410:
1407 #endif
1408 #ifdef TMIO_OHCI_DRIVER
1409 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1410 error_tmio:
1411 #endif
1412 #ifdef SM501_OHCI_DRIVER
1413 platform_driver_unregister(&SM501_OHCI_DRIVER);
1414 error_sm501:
1415 #endif
1416 #ifdef SA1111_DRIVER
1417 sa1111_driver_unregister(&SA1111_DRIVER);
1418 error_sa1111:
1419 #endif
1420 #ifdef OF_PLATFORM_DRIVER
1421 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1422 error_of_platform:
1423 #endif
1424 #ifdef OMAP3_PLATFORM_DRIVER
1425 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1426 error_omap3_platform:
1427 #endif
1428 #ifdef OMAP1_PLATFORM_DRIVER
1429 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1430 error_omap1_platform:
1431 #endif
1432 #ifdef PLATFORM_DRIVER
1433 platform_driver_unregister(&PLATFORM_DRIVER);
1434 error_platform:
1435 #endif
1436 #ifdef PS3_SYSTEM_BUS_DRIVER
1437 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1438 error_ps3:
1439 #endif
1440 #ifdef DEBUG
1441 debugfs_remove(ohci_debug_root);
1442 ohci_debug_root = NULL;
1443 error_debug:
1444 #endif
1445
1446 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1447 return retval;
1448 }
1449 module_init(ohci_hcd_mod_init);
1450
1451 static void __exit ohci_hcd_mod_exit(void)
1452 {
1453 #ifdef SPEAR_PLATFORM_DRIVER
1454 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1455 #endif
1456 #ifdef DAVINCI_PLATFORM_DRIVER
1457 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1458 #endif
1459 #ifdef NXP_PLATFORM_DRIVER
1460 platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1461 #endif
1462 #ifdef AT91_PLATFORM_DRIVER
1463 platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1464 #endif
1465 #ifdef EP93XX_PLATFORM_DRIVER
1466 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1467 #endif
1468 #ifdef EXYNOS_PLATFORM_DRIVER
1469 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1470 #endif
1471 #ifdef S3C2410_PLATFORM_DRIVER
1472 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1473 #endif
1474 #ifdef TMIO_OHCI_DRIVER
1475 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1476 #endif
1477 #ifdef SM501_OHCI_DRIVER
1478 platform_driver_unregister(&SM501_OHCI_DRIVER);
1479 #endif
1480 #ifdef SA1111_DRIVER
1481 sa1111_driver_unregister(&SA1111_DRIVER);
1482 #endif
1483 #ifdef OF_PLATFORM_DRIVER
1484 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1485 #endif
1486 #ifdef OMAP3_PLATFORM_DRIVER
1487 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1488 #endif
1489 #ifdef OMAP1_PLATFORM_DRIVER
1490 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1491 #endif
1492 #ifdef PLATFORM_DRIVER
1493 platform_driver_unregister(&PLATFORM_DRIVER);
1494 #endif
1495 #ifdef PS3_SYSTEM_BUS_DRIVER
1496 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1497 #endif
1498 #ifdef DEBUG
1499 debugfs_remove(ohci_debug_root);
1500 #endif
1501 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1502 }
1503 module_exit(ohci_hcd_mod_exit);
1504
Linux with added FPC-III support