drivers/usb/musb/musb_cppi41.c

   1 #include <linux/device.h>
   2 #include <linux/dma-mapping.h>
   3 #include <linux/dmaengine.h>
   4 #include <linux/sizes.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/of.h>
   7
   8 #include "musb_core.h"
   9
  10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
  11
  12 #define EP_MODE_AUTOREQ_NONE            0
  13 #define EP_MODE_AUTOREQ_ALL_NEOP        1
  14 #define EP_MODE_AUTOREQ_ALWAYS          3
  15
  16 #define EP_MODE_DMA_TRANSPARENT         0
  17 #define EP_MODE_DMA_RNDIS               1
  18 #define EP_MODE_DMA_GEN_RNDIS           3
  19
  20 #define USB_CTRL_TX_MODE        0x70
  21 #define USB_CTRL_RX_MODE        0x74
  22 #define USB_CTRL_AUTOREQ        0xd0
  23 #define USB_TDOWN               0xd8
  24
  25 struct cppi41_dma_channel {
  26         struct dma_channel channel;
  27         struct cppi41_dma_controller *controller;
  28         struct musb_hw_ep *hw_ep;
  29         struct dma_chan *dc;
  30         dma_cookie_t cookie;
  31         u8 port_num;
  32         u8 is_tx;
  33         u8 is_allocated;
  34         u8 usb_toggle;
  35
  36         dma_addr_t buf_addr;
  37         u32 total_len;
  38         u32 prog_len;
  39         u32 transferred;
  40         u32 packet_sz;
  41         struct list_head tx_check;
  42 };
  43
  44 #define MUSB_DMA_NUM_CHANNELS 15
  45
  46 struct cppi41_dma_controller {
  47         struct dma_controller controller;
  48         struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
  49         struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
  50         struct musb *musb;
  51         struct hrtimer early_tx;
  52         struct list_head early_tx_list;
  53         u32 rx_mode;
  54         u32 tx_mode;
  55         u32 auto_req;
  56 };
  57
  58 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  59 {
  60         u16 csr;
  61         u8 toggle;
  62
  63         if (cppi41_channel->is_tx)
  64                 return;
  65         if (!is_host_active(cppi41_channel->controller->musb))
  66                 return;
  67
  68         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  69         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  70
  71         cppi41_channel->usb_toggle = toggle;
  72 }
  73
  74 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  75 {
  76         u16 csr;
  77         u8 toggle;
  78
  79         if (cppi41_channel->is_tx)
  80                 return;
  81         if (!is_host_active(cppi41_channel->controller->musb))
  82                 return;
  83
  84         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  85         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  86
  87         /*
  88          * AM335x Advisory 1.0.13: Due to internal synchronisation error the
  89          * data toggle may reset from DATA1 to DATA0 during receiving data from
  90          * more than one endpoint.
  91          */
  92         if (!toggle && toggle == cppi41_channel->usb_toggle) {
  93                 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
  94                 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
  95                 dev_dbg(cppi41_channel->controller->musb->controller,
  96                                 "Restoring DATA1 toggle.\n");
  97         }
  98
  99         cppi41_channel->usb_toggle = toggle;
 100 }
 101
 102 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
 103 {
 104         u8              epnum = hw_ep->epnum;
 105         struct musb     *musb = hw_ep->musb;
 106         void __iomem    *epio = musb->endpoints[epnum].regs;
 107         u16             csr;
 108
 109         csr = musb_readw(epio, MUSB_TXCSR);
 110         if (csr & MUSB_TXCSR_TXPKTRDY)
 111                 return false;
 112         return true;
 113 }
 114
 115 static void cppi41_dma_callback(void *private_data);
 116
 117 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
 118 {
 119         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 120         struct musb *musb = hw_ep->musb;
 121
 122         if (!cppi41_channel->prog_len) {
 123
 124                 /* done, complete */
 125                 cppi41_channel->channel.actual_len =
 126                         cppi41_channel->transferred;
 127                 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 128                 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
 129         } else {
 130                 /* next iteration, reload */
 131                 struct dma_chan *dc = cppi41_channel->dc;
 132                 struct dma_async_tx_descriptor *dma_desc;
 133                 enum dma_transfer_direction direction;
 134                 u16 csr;
 135                 u32 remain_bytes;
 136                 void __iomem *epio = cppi41_channel->hw_ep->regs;
 137
 138                 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
 139
 140                 remain_bytes = cppi41_channel->total_len;
 141                 remain_bytes -= cppi41_channel->transferred;
 142                 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
 143                 cppi41_channel->prog_len = remain_bytes;
 144
 145                 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
 146                         : DMA_DEV_TO_MEM;
 147                 dma_desc = dmaengine_prep_slave_single(dc,
 148                                 cppi41_channel->buf_addr,
 149                                 remain_bytes,
 150                                 direction,
 151                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 152                 if (WARN_ON(!dma_desc))
 153                         return;
 154
 155                 dma_desc->callback = cppi41_dma_callback;
 156                 dma_desc->callback_param = &cppi41_channel->channel;
 157                 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 158                 dma_async_issue_pending(dc);
 159
 160                 if (!cppi41_channel->is_tx) {
 161                         csr = musb_readw(epio, MUSB_RXCSR);
 162                         csr |= MUSB_RXCSR_H_REQPKT;
 163                         musb_writew(epio, MUSB_RXCSR, csr);
 164                 }
 165         }
 166 }
 167
 168 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
 169 {
 170         struct cppi41_dma_controller *controller;
 171         struct cppi41_dma_channel *cppi41_channel, *n;
 172         struct musb *musb;
 173         unsigned long flags;
 174         enum hrtimer_restart ret = HRTIMER_NORESTART;
 175
 176         controller = container_of(timer, struct cppi41_dma_controller,
 177                         early_tx);
 178         musb = controller->musb;
 179
 180         spin_lock_irqsave(&musb->lock, flags);
 181         list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
 182                         tx_check) {
 183                 bool empty;
 184                 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 185
 186                 empty = musb_is_tx_fifo_empty(hw_ep);
 187                 if (empty) {
 188                         list_del_init(&cppi41_channel->tx_check);
 189                         cppi41_trans_done(cppi41_channel);
 190                 }
 191         }
 192
 193         if (!list_empty(&controller->early_tx_list) &&
 194             !hrtimer_is_queued(&controller->early_tx)) {
 195                 ret = HRTIMER_RESTART;
 196                 hrtimer_forward_now(&controller->early_tx,
 197                                 ktime_set(0, 50 * NSEC_PER_USEC));
 198         }
 199
 200         spin_unlock_irqrestore(&musb->lock, flags);
 201         return ret;
 202 }
 203
 204 static void cppi41_dma_callback(void *private_data)
 205 {
 206         struct dma_channel *channel = private_data;
 207         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 208         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 209         struct musb *musb = hw_ep->musb;
 210         unsigned long flags;
 211         struct dma_tx_state txstate;
 212         u32 transferred;
 213         bool empty;
 214
 215         spin_lock_irqsave(&musb->lock, flags);
 216
 217         dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
 218                         &txstate);
 219         transferred = cppi41_channel->prog_len - txstate.residue;
 220         cppi41_channel->transferred += transferred;
 221
 222         dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
 223                 hw_ep->epnum, cppi41_channel->transferred,
 224                 cppi41_channel->total_len);
 225
 226         update_rx_toggle(cppi41_channel);
 227
 228         if (cppi41_channel->transferred == cppi41_channel->total_len ||
 229                         transferred < cppi41_channel->packet_sz)
 230                 cppi41_channel->prog_len = 0;
 231
 232         empty = musb_is_tx_fifo_empty(hw_ep);
 233         if (empty) {
 234                 cppi41_trans_done(cppi41_channel);
 235         } else {
 236                 struct cppi41_dma_controller *controller;
 237                 /*
 238                  * On AM335x it has been observed that the TX interrupt fires
 239                  * too early that means the TXFIFO is not yet empty but the DMA
 240                  * engine says that it is done with the transfer. We don't
 241                  * receive a FIFO empty interrupt so the only thing we can do is
 242                  * to poll for the bit. On HS it usually takes 2us, on FS around
 243                  * 110us - 150us depending on the transfer size.
 244                  * We spin on HS (no longer than than 25us and setup a timer on
 245                  * FS to check for the bit and complete the transfer.
 246                  */
 247                 controller = cppi41_channel->controller;
 248
 249                 if (musb->g.speed == USB_SPEED_HIGH) {
 250                         unsigned wait = 25;
 251
 252                         do {
 253                                 empty = musb_is_tx_fifo_empty(hw_ep);
 254                                 if (empty)
 255                                         break;
 256                                 wait--;
 257                                 if (!wait)
 258                                         break;
 259                                 udelay(1);
 260                         } while (1);
 261
 262                         empty = musb_is_tx_fifo_empty(hw_ep);
 263                         if (empty) {
 264                                 cppi41_trans_done(cppi41_channel);
 265                                 goto out;
 266                         }
 267                 }
 268                 list_add_tail(&cppi41_channel->tx_check,
 269                                 &controller->early_tx_list);
 270                 if (!hrtimer_is_queued(&controller->early_tx)) {
 271                         unsigned long usecs = cppi41_channel->total_len / 10;
 272
 273                         hrtimer_start_range_ns(&controller->early_tx,
 274                                 ktime_set(0, usecs * NSEC_PER_USEC),
 275                                 40 * NSEC_PER_USEC,
 276                                 HRTIMER_MODE_REL);
 277                 }
 278         }
 279 out:
 280         spin_unlock_irqrestore(&musb->lock, flags);
 281 }
 282
 283 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
 284 {
 285         unsigned shift;
 286
 287         shift = (ep - 1) * 2;
 288         old &= ~(3 << shift);
 289         old |= mode << shift;
 290         return old;
 291 }
 292
 293 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
 294                 unsigned mode)
 295 {
 296         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 297         u32 port;
 298         u32 new_mode;
 299         u32 old_mode;
 300
 301         if (cppi41_channel->is_tx)
 302                 old_mode = controller->tx_mode;
 303         else
 304                 old_mode = controller->rx_mode;
 305         port = cppi41_channel->port_num;
 306         new_mode = update_ep_mode(port, mode, old_mode);
 307
 308         if (new_mode == old_mode)
 309                 return;
 310         if (cppi41_channel->is_tx) {
 311                 controller->tx_mode = new_mode;
 312                 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
 313                                 new_mode);
 314         } else {
 315                 controller->rx_mode = new_mode;
 316                 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
 317                                 new_mode);
 318         }
 319 }
 320
 321 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
 322                 unsigned mode)
 323 {
 324         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 325         u32 port;
 326         u32 new_mode;
 327         u32 old_mode;
 328
 329         old_mode = controller->auto_req;
 330         port = cppi41_channel->port_num;
 331         new_mode = update_ep_mode(port, mode, old_mode);
 332
 333         if (new_mode == old_mode)
 334                 return;
 335         controller->auto_req = new_mode;
 336         musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
 337 }
 338
 339 static bool cppi41_configure_channel(struct dma_channel *channel,
 340                                 u16 packet_sz, u8 mode,
 341                                 dma_addr_t dma_addr, u32 len)
 342 {
 343         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 344         struct dma_chan *dc = cppi41_channel->dc;
 345         struct dma_async_tx_descriptor *dma_desc;
 346         enum dma_transfer_direction direction;
 347         struct musb *musb = cppi41_channel->controller->musb;
 348         unsigned use_gen_rndis = 0;
 349
 350         dev_dbg(musb->controller,
 351                 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
 352                 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
 353                 packet_sz, mode, (unsigned long long) dma_addr,
 354                 len, cppi41_channel->is_tx);
 355
 356         cppi41_channel->buf_addr = dma_addr;
 357         cppi41_channel->total_len = len;
 358         cppi41_channel->transferred = 0;
 359         cppi41_channel->packet_sz = packet_sz;
 360
 361         /*
 362          * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
 363          * than max packet size at a time.
 364          */
 365         if (cppi41_channel->is_tx)
 366                 use_gen_rndis = 1;
 367
 368         if (use_gen_rndis) {
 369                 /* RNDIS mode */
 370                 if (len > packet_sz) {
 371                         musb_writel(musb->ctrl_base,
 372                                 RNDIS_REG(cppi41_channel->port_num), len);
 373                         /* gen rndis */
 374                         cppi41_set_dma_mode(cppi41_channel,
 375                                         EP_MODE_DMA_GEN_RNDIS);
 376
 377                         /* auto req */
 378                         cppi41_set_autoreq_mode(cppi41_channel,
 379                                         EP_MODE_AUTOREQ_ALL_NEOP);
 380                 } else {
 381                         musb_writel(musb->ctrl_base,
 382                                         RNDIS_REG(cppi41_channel->port_num), 0);
 383                         cppi41_set_dma_mode(cppi41_channel,
 384                                         EP_MODE_DMA_TRANSPARENT);
 385                         cppi41_set_autoreq_mode(cppi41_channel,
 386                                         EP_MODE_AUTOREQ_NONE);
 387                 }
 388         } else {
 389                 /* fallback mode */
 390                 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
 391                 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
 392                 len = min_t(u32, packet_sz, len);
 393         }
 394         cppi41_channel->prog_len = len;
 395         direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
 396         dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
 397                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 398         if (!dma_desc)
 399                 return false;
 400
 401         dma_desc->callback = cppi41_dma_callback;
 402         dma_desc->callback_param = channel;
 403         cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 404
 405         save_rx_toggle(cppi41_channel);
 406         dma_async_issue_pending(dc);
 407         return true;
 408 }
 409
 410 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
 411                                 struct musb_hw_ep *hw_ep, u8 is_tx)
 412 {
 413         struct cppi41_dma_controller *controller = container_of(c,
 414                         struct cppi41_dma_controller, controller);
 415         struct cppi41_dma_channel *cppi41_channel = NULL;
 416         u8 ch_num = hw_ep->epnum - 1;
 417
 418         if (ch_num >= MUSB_DMA_NUM_CHANNELS)
 419                 return NULL;
 420
 421         if (is_tx)
 422                 cppi41_channel = &controller->tx_channel[ch_num];
 423         else
 424                 cppi41_channel = &controller->rx_channel[ch_num];
 425
 426         if (!cppi41_channel->dc)
 427                 return NULL;
 428
 429         if (cppi41_channel->is_allocated)
 430                 return NULL;
 431
 432         cppi41_channel->hw_ep = hw_ep;
 433         cppi41_channel->is_allocated = 1;
 434
 435         return &cppi41_channel->channel;
 436 }
 437
 438 static void cppi41_dma_channel_release(struct dma_channel *channel)
 439 {
 440         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 441
 442         if (cppi41_channel->is_allocated) {
 443                 cppi41_channel->is_allocated = 0;
 444                 channel->status = MUSB_DMA_STATUS_FREE;
 445                 channel->actual_len = 0;
 446         }
 447 }
 448
 449 static int cppi41_dma_channel_program(struct dma_channel *channel,
 450                                 u16 packet_sz, u8 mode,
 451                                 dma_addr_t dma_addr, u32 len)
 452 {
 453         int ret;
 454
 455         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 456                 channel->status == MUSB_DMA_STATUS_BUSY);
 457
 458         channel->status = MUSB_DMA_STATUS_BUSY;
 459         channel->actual_len = 0;
 460         ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
 461         if (!ret)
 462                 channel->status = MUSB_DMA_STATUS_FREE;
 463
 464         return ret;
 465 }
 466
 467 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
 468                 void *buf, u32 length)
 469 {
 470         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 471         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 472         struct musb *musb = controller->musb;
 473
 474         if (is_host_active(musb)) {
 475                 WARN_ON(1);
 476                 return 1;
 477         }
 478         if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
 479                 return 0;
 480         if (cppi41_channel->is_tx)
 481                 return 1;
 482         /* AM335x Advisory 1.0.13. No workaround for device RX mode */
 483         return 0;
 484 }
 485
 486 static int cppi41_dma_channel_abort(struct dma_channel *channel)
 487 {
 488         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 489         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 490         struct musb *musb = controller->musb;
 491         void __iomem *epio = cppi41_channel->hw_ep->regs;
 492         int tdbit;
 493         int ret;
 494         unsigned is_tx;
 495         u16 csr;
 496
 497         is_tx = cppi41_channel->is_tx;
 498         dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
 499                         cppi41_channel->port_num, is_tx);
 500
 501         if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
 502                 return 0;
 503
 504         list_del_init(&cppi41_channel->tx_check);
 505         if (is_tx) {
 506                 csr = musb_readw(epio, MUSB_TXCSR);
 507                 csr &= ~MUSB_TXCSR_DMAENAB;
 508                 musb_writew(epio, MUSB_TXCSR, csr);
 509         } else {
 510                 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
 511
 512                 /* delay to drain to cppi dma pipeline for isoch */
 513                 udelay(250);
 514
 515                 csr = musb_readw(epio, MUSB_RXCSR);
 516                 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
 517                 musb_writew(epio, MUSB_RXCSR, csr);
 518
 519                 /* wait to drain cppi dma pipe line */
 520                 udelay(50);
 521
 522                 csr = musb_readw(epio, MUSB_RXCSR);
 523                 if (csr & MUSB_RXCSR_RXPKTRDY) {
 524                         csr |= MUSB_RXCSR_FLUSHFIFO;
 525                         musb_writew(epio, MUSB_RXCSR, csr);
 526                         musb_writew(epio, MUSB_RXCSR, csr);
 527                 }
 528         }
 529
 530         tdbit = 1 << cppi41_channel->port_num;
 531         if (is_tx)
 532                 tdbit <<= 16;
 533
 534         do {
 535                 if (is_tx)
 536                         musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 537                 ret = dmaengine_terminate_all(cppi41_channel->dc);
 538         } while (ret == -EAGAIN);
 539
 540         if (is_tx) {
 541                 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 542
 543                 csr = musb_readw(epio, MUSB_TXCSR);
 544                 if (csr & MUSB_TXCSR_TXPKTRDY) {
 545                         csr |= MUSB_TXCSR_FLUSHFIFO;
 546                         musb_writew(epio, MUSB_TXCSR, csr);
 547                 }
 548         }
 549
 550         cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 551         return 0;
 552 }
 553
 554 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
 555 {
 556         struct dma_chan *dc;
 557         int i;
 558
 559         for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
 560                 dc = ctrl->tx_channel[i].dc;
 561                 if (dc)
 562                         dma_release_channel(dc);
 563                 dc = ctrl->rx_channel[i].dc;
 564                 if (dc)
 565                         dma_release_channel(dc);
 566         }
 567 }
 568
 569 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
 570 {
 571         cppi41_release_all_dma_chans(controller);
 572 }
 573
 574 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
 575 {
 576         struct musb *musb = controller->musb;
 577         struct device *dev = musb->controller;
 578         struct device_node *np = dev->of_node;
 579         struct cppi41_dma_channel *cppi41_channel;
 580         int count;
 581         int i;
 582         int ret;
 583
 584         count = of_property_count_strings(np, "dma-names");
 585         if (count < 0)
 586                 return count;
 587
 588         for (i = 0; i < count; i++) {
 589                 struct dma_chan *dc;
 590                 struct dma_channel *musb_dma;
 591                 const char *str;
 592                 unsigned is_tx;
 593                 unsigned int port;
 594
 595                 ret = of_property_read_string_index(np, "dma-names", i, &str);
 596                 if (ret)
 597                         goto err;
 598                 if (strstarts(str, "tx"))
 599                         is_tx = 1;
 600                 else if (strstarts(str, "rx"))
 601                         is_tx = 0;
 602                 else {
 603                         dev_err(dev, "Wrong dmatype %s\n", str);
 604                         goto err;
 605                 }
 606                 ret = kstrtouint(str + 2, 0, &port);
 607                 if (ret)
 608                         goto err;
 609
 610                 if (port > MUSB_DMA_NUM_CHANNELS || !port)
 611                         goto err;
 612                 if (is_tx)
 613                         cppi41_channel = &controller->tx_channel[port - 1];
 614                 else
 615                         cppi41_channel = &controller->rx_channel[port - 1];
 616
 617                 cppi41_channel->controller = controller;
 618                 cppi41_channel->port_num = port;
 619                 cppi41_channel->is_tx = is_tx;
 620                 INIT_LIST_HEAD(&cppi41_channel->tx_check);
 621
 622                 musb_dma = &cppi41_channel->channel;
 623                 musb_dma->private_data = cppi41_channel;
 624                 musb_dma->status = MUSB_DMA_STATUS_FREE;
 625                 musb_dma->max_len = SZ_4M;
 626
 627                 dc = dma_request_slave_channel(dev, str);
 628                 if (!dc) {
 629                         dev_err(dev, "Falied to request %s.\n", str);
 630                         goto err;
 631                 }
 632                 cppi41_channel->dc = dc;
 633         }
 634         return 0;
 635 err:
 636         cppi41_release_all_dma_chans(controller);
 637         return -EINVAL;
 638 }
 639
 640 void dma_controller_destroy(struct dma_controller *c)
 641 {
 642         struct cppi41_dma_controller *controller = container_of(c,
 643                         struct cppi41_dma_controller, controller);
 644
 645         hrtimer_cancel(&controller->early_tx);
 646         cppi41_dma_controller_stop(controller);
 647         kfree(controller);
 648 }
 649
 650 struct dma_controller *dma_controller_create(struct musb *musb,
 651                                         void __iomem *base)
 652 {
 653         struct cppi41_dma_controller *controller;
 654         int ret;
 655
 656         if (!musb->controller->of_node) {
 657                 dev_err(musb->controller, "Need DT for the DMA engine.\n");
 658                 return NULL;
 659         }
 660
 661         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 662         if (!controller)
 663                 goto kzalloc_fail;
 664
 665         hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 666         controller->early_tx.function = cppi41_recheck_tx_req;
 667         INIT_LIST_HEAD(&controller->early_tx_list);
 668         controller->musb = musb;
 669
 670         controller->controller.channel_alloc = cppi41_dma_channel_allocate;
 671         controller->controller.channel_release = cppi41_dma_channel_release;
 672         controller->controller.channel_program = cppi41_dma_channel_program;
 673         controller->controller.channel_abort = cppi41_dma_channel_abort;
 674         controller->controller.is_compatible = cppi41_is_compatible;
 675
 676         ret = cppi41_dma_controller_start(controller);
 677         if (ret)
 678                 goto plat_get_fail;
 679         return &controller->controller;
 680
 681 plat_get_fail:
 682         kfree(controller);
 683 kzalloc_fail:
 684         return NULL;
 685 }