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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / usb / musb / musb_host.c
blob7be2ad0a10f4bb04fddf7309f177ecb5dd4b8880
1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/init.h>
43 #include <linux/list.h>
44 #include <linux/dma-mapping.h>
45
46 #include "musb_core.h"
47 #include "musb_host.h"
48
49 /* MUSB HOST status 22-mar-2006
50 *
51 * - There's still lots of partial code duplication for fault paths, so
52 * they aren't handled as consistently as they need to be.
53 *
54 * - PIO mostly behaved when last tested.
55 * + including ep0, with all usbtest cases 9, 10
56 * + usbtest 14 (ep0out) doesn't seem to run at all
57 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
58 * configurations, but otherwise double buffering passes basic tests.
59 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
60 *
61 * - DMA (CPPI) ... partially behaves, not currently recommended
62 * + about 1/15 the speed of typical EHCI implementations (PCI)
63 * + RX, all too often reqpkt seems to misbehave after tx
64 * + TX, no known issues (other than evident silicon issue)
65 *
66 * - DMA (Mentor/OMAP) ...has at least toggle update problems
67 *
68 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
69 * starvation ... nothing yet for TX, interrupt, or bulk.
70 *
71 * - Not tested with HNP, but some SRP paths seem to behave.
72 *
73 * NOTE 24-August-2006:
74 *
75 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
76 * extra endpoint for periodic use enabling hub + keybd + mouse. That
77 * mostly works, except that with "usbnet" it's easy to trigger cases
78 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
79 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
80 * although ARP RX wins. (That test was done with a full speed link.)
81 */
82
83
84 /*
85 * NOTE on endpoint usage:
86 *
87 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
88 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
89 * (Yes, bulk _could_ use more of the endpoints than that, and would even
90 * benefit from it.)
91 *
92 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
93 * So far that scheduling is both dumb and optimistic: the endpoint will be
94 * "claimed" until its software queue is no longer refilled. No multiplexing
95 * of transfers between endpoints, or anything clever.
96 */
97
98 struct musb *hcd_to_musb(struct usb_hcd *hcd)
99 {
100 return *(struct musb **) hcd->hcd_priv;
101 }
102
103
104 static void musb_ep_program(struct musb *musb, u8 epnum,
105 struct urb *urb, int is_out,
106 u8 *buf, u32 offset, u32 len);
107
108 /*
109 * Clear TX fifo. Needed to avoid BABBLE errors.
110 */
111 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
112 {
113 struct musb *musb = ep->musb;
114 void __iomem *epio = ep->regs;
115 u16 csr;
116 u16 lastcsr = 0;
117 int retries = 1000;
118
119 csr = musb_readw(epio, MUSB_TXCSR);
120 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
121 if (csr != lastcsr)
122 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
123 lastcsr = csr;
124 csr |= MUSB_TXCSR_FLUSHFIFO;
125 musb_writew(epio, MUSB_TXCSR, csr);
126 csr = musb_readw(epio, MUSB_TXCSR);
127 if (WARN(retries-- < 1,
128 "Could not flush host TX%d fifo: csr: %04x\n",
129 ep->epnum, csr))
130 return;
131 mdelay(1);
132 }
133 }
134
135 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
136 {
137 void __iomem *epio = ep->regs;
138 u16 csr;
139 int retries = 5;
140
141 /* scrub any data left in the fifo */
142 do {
143 csr = musb_readw(epio, MUSB_TXCSR);
144 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
145 break;
146 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
147 csr = musb_readw(epio, MUSB_TXCSR);
148 udelay(10);
149 } while (--retries);
150
151 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
152 ep->epnum, csr);
153
154 /* and reset for the next transfer */
155 musb_writew(epio, MUSB_TXCSR, 0);
156 }
157
158 /*
159 * Start transmit. Caller is responsible for locking shared resources.
160 * musb must be locked.
161 */
162 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
163 {
164 u16 txcsr;
165
166 /* NOTE: no locks here; caller should lock and select EP */
167 if (ep->epnum) {
168 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
169 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
170 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
171 } else {
172 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
173 musb_writew(ep->regs, MUSB_CSR0, txcsr);
174 }
175
176 }
177
178 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
179 {
180 u16 txcsr;
181
182 /* NOTE: no locks here; caller should lock and select EP */
183 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
184 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
185 if (is_cppi_enabled())
186 txcsr |= MUSB_TXCSR_DMAMODE;
187 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
188 }
189
190 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
191 {
192 if (is_in != 0 || ep->is_shared_fifo)
193 ep->in_qh = qh;
194 if (is_in == 0 || ep->is_shared_fifo)
195 ep->out_qh = qh;
196 }
197
198 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
199 {
200 return is_in ? ep->in_qh : ep->out_qh;
201 }
202
203 /*
204 * Start the URB at the front of an endpoint's queue
205 * end must be claimed from the caller.
206 *
207 * Context: controller locked, irqs blocked
208 */
209 static void
210 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
211 {
212 u16 frame;
213 u32 len;
214 void __iomem *mbase = musb->mregs;
215 struct urb *urb = next_urb(qh);
216 void *buf = urb->transfer_buffer;
217 u32 offset = 0;
218 struct musb_hw_ep *hw_ep = qh->hw_ep;
219 unsigned pipe = urb->pipe;
220 u8 address = usb_pipedevice(pipe);
221 int epnum = hw_ep->epnum;
222
223 /* initialize software qh state */
224 qh->offset = 0;
225 qh->segsize = 0;
226
227 /* gather right source of data */
228 switch (qh->type) {
229 case USB_ENDPOINT_XFER_CONTROL:
230 /* control transfers always start with SETUP */
231 is_in = 0;
232 musb->ep0_stage = MUSB_EP0_START;
233 buf = urb->setup_packet;
234 len = 8;
235 break;
236 case USB_ENDPOINT_XFER_ISOC:
237 qh->iso_idx = 0;
238 qh->frame = 0;
239 offset = urb->iso_frame_desc[0].offset;
240 len = urb->iso_frame_desc[0].length;
241 break;
242 default: /* bulk, interrupt */
243 /* actual_length may be nonzero on retry paths */
244 buf = urb->transfer_buffer + urb->actual_length;
245 len = urb->transfer_buffer_length - urb->actual_length;
246 }
247
248 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
249 qh, urb, address, qh->epnum,
250 is_in ? "in" : "out",
251 ({char *s; switch (qh->type) {
252 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
253 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
254 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
255 default: s = "-intr"; break;
256 }; s; }),
257 epnum, buf + offset, len);
258
259 /* Configure endpoint */
260 musb_ep_set_qh(hw_ep, is_in, qh);
261 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
262
263 /* transmit may have more work: start it when it is time */
264 if (is_in)
265 return;
266
267 /* determine if the time is right for a periodic transfer */
268 switch (qh->type) {
269 case USB_ENDPOINT_XFER_ISOC:
270 case USB_ENDPOINT_XFER_INT:
271 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
272 frame = musb_readw(mbase, MUSB_FRAME);
273 /* FIXME this doesn't implement that scheduling policy ...
274 * or handle framecounter wrapping
275 */
276 if (1) { /* Always assume URB_ISO_ASAP */
277 /* REVISIT the SOF irq handler shouldn't duplicate
278 * this code; and we don't init urb->start_frame...
279 */
280 qh->frame = 0;
281 goto start;
282 } else {
283 qh->frame = urb->start_frame;
284 /* enable SOF interrupt so we can count down */
285 dev_dbg(musb->controller, "SOF for %d\n", epnum);
286 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
287 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
288 #endif
289 }
290 break;
291 default:
292 start:
293 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
294 hw_ep->tx_channel ? "dma" : "pio");
295
296 if (!hw_ep->tx_channel)
297 musb_h_tx_start(hw_ep);
298 else if (is_cppi_enabled() || tusb_dma_omap())
299 musb_h_tx_dma_start(hw_ep);
300 }
301 }
302
303 /* Context: caller owns controller lock, IRQs are blocked */
304 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
305 __releases(musb->lock)
306 __acquires(musb->lock)
307 {
308 dev_dbg(musb->controller,
309 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
310 urb, urb->complete, status,
311 usb_pipedevice(urb->pipe),
312 usb_pipeendpoint(urb->pipe),
313 usb_pipein(urb->pipe) ? "in" : "out",
314 urb->actual_length, urb->transfer_buffer_length
315 );
316
317 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
318 spin_unlock(&musb->lock);
319 usb_hcd_giveback_urb(musb->hcd, urb, status);
320 spin_lock(&musb->lock);
321 }
322
323 /* For bulk/interrupt endpoints only */
324 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
325 struct urb *urb)
326 {
327 void __iomem *epio = qh->hw_ep->regs;
328 u16 csr;
329
330 /*
331 * FIXME: the current Mentor DMA code seems to have
332 * problems getting toggle correct.
333 */
334
335 if (is_in)
336 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
337 else
338 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
339
340 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
341 }
342
343 /*
344 * Advance this hardware endpoint's queue, completing the specified URB and
345 * advancing to either the next URB queued to that qh, or else invalidating
346 * that qh and advancing to the next qh scheduled after the current one.
347 *
348 * Context: caller owns controller lock, IRQs are blocked
349 */
350 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
351 struct musb_hw_ep *hw_ep, int is_in)
352 {
353 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
354 struct musb_hw_ep *ep = qh->hw_ep;
355 int ready = qh->is_ready;
356 int status;
357
358 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
359
360 /* save toggle eagerly, for paranoia */
361 switch (qh->type) {
362 case USB_ENDPOINT_XFER_BULK:
363 case USB_ENDPOINT_XFER_INT:
364 musb_save_toggle(qh, is_in, urb);
365 break;
366 case USB_ENDPOINT_XFER_ISOC:
367 if (status == 0 && urb->error_count)
368 status = -EXDEV;
369 break;
370 }
371
372 qh->is_ready = 0;
373 musb_giveback(musb, urb, status);
374 qh->is_ready = ready;
375
376 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
377 * invalidate qh as soon as list_empty(&hep->urb_list)
378 */
379 if (list_empty(&qh->hep->urb_list)) {
380 struct list_head *head;
381 struct dma_controller *dma = musb->dma_controller;
382
383 if (is_in) {
384 ep->rx_reinit = 1;
385 if (ep->rx_channel) {
386 dma->channel_release(ep->rx_channel);
387 ep->rx_channel = NULL;
388 }
389 } else {
390 ep->tx_reinit = 1;
391 if (ep->tx_channel) {
392 dma->channel_release(ep->tx_channel);
393 ep->tx_channel = NULL;
394 }
395 }
396
397 /* Clobber old pointers to this qh */
398 musb_ep_set_qh(ep, is_in, NULL);
399 qh->hep->hcpriv = NULL;
400
401 switch (qh->type) {
402
403 case USB_ENDPOINT_XFER_CONTROL:
404 case USB_ENDPOINT_XFER_BULK:
405 /* fifo policy for these lists, except that NAKing
406 * should rotate a qh to the end (for fairness).
407 */
408 if (qh->mux == 1) {
409 head = qh->ring.prev;
410 list_del(&qh->ring);
411 kfree(qh);
412 qh = first_qh(head);
413 break;
414 }
415
416 case USB_ENDPOINT_XFER_ISOC:
417 case USB_ENDPOINT_XFER_INT:
418 /* this is where periodic bandwidth should be
419 * de-allocated if it's tracked and allocated;
420 * and where we'd update the schedule tree...
421 */
422 kfree(qh);
423 qh = NULL;
424 break;
425 }
426 }
427
428 if (qh != NULL && qh->is_ready) {
429 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
430 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
431 musb_start_urb(musb, is_in, qh);
432 }
433 }
434
435 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
436 {
437 /* we don't want fifo to fill itself again;
438 * ignore dma (various models),
439 * leave toggle alone (may not have been saved yet)
440 */
441 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
442 csr &= ~(MUSB_RXCSR_H_REQPKT
443 | MUSB_RXCSR_H_AUTOREQ
444 | MUSB_RXCSR_AUTOCLEAR);
445
446 /* write 2x to allow double buffering */
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
448 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
449
450 /* flush writebuffer */
451 return musb_readw(hw_ep->regs, MUSB_RXCSR);
452 }
453
454 /*
455 * PIO RX for a packet (or part of it).
456 */
457 static bool
458 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
459 {
460 u16 rx_count;
461 u8 *buf;
462 u16 csr;
463 bool done = false;
464 u32 length;
465 int do_flush = 0;
466 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
467 void __iomem *epio = hw_ep->regs;
468 struct musb_qh *qh = hw_ep->in_qh;
469 int pipe = urb->pipe;
470 void *buffer = urb->transfer_buffer;
471
472 /* musb_ep_select(mbase, epnum); */
473 rx_count = musb_readw(epio, MUSB_RXCOUNT);
474 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
475 urb->transfer_buffer, qh->offset,
476 urb->transfer_buffer_length);
477
478 /* unload FIFO */
479 if (usb_pipeisoc(pipe)) {
480 int status = 0;
481 struct usb_iso_packet_descriptor *d;
482
483 if (iso_err) {
484 status = -EILSEQ;
485 urb->error_count++;
486 }
487
488 d = urb->iso_frame_desc + qh->iso_idx;
489 buf = buffer + d->offset;
490 length = d->length;
491 if (rx_count > length) {
492 if (status == 0) {
493 status = -EOVERFLOW;
494 urb->error_count++;
495 }
496 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
497 do_flush = 1;
498 } else
499 length = rx_count;
500 urb->actual_length += length;
501 d->actual_length = length;
502
503 d->status = status;
504
505 /* see if we are done */
506 done = (++qh->iso_idx >= urb->number_of_packets);
507 } else {
508 /* non-isoch */
509 buf = buffer + qh->offset;
510 length = urb->transfer_buffer_length - qh->offset;
511 if (rx_count > length) {
512 if (urb->status == -EINPROGRESS)
513 urb->status = -EOVERFLOW;
514 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
515 do_flush = 1;
516 } else
517 length = rx_count;
518 urb->actual_length += length;
519 qh->offset += length;
520
521 /* see if we are done */
522 done = (urb->actual_length == urb->transfer_buffer_length)
523 || (rx_count < qh->maxpacket)
524 || (urb->status != -EINPROGRESS);
525 if (done
526 && (urb->status == -EINPROGRESS)
527 && (urb->transfer_flags & URB_SHORT_NOT_OK)
528 && (urb->actual_length
529 < urb->transfer_buffer_length))
530 urb->status = -EREMOTEIO;
531 }
532
533 musb_read_fifo(hw_ep, length, buf);
534
535 csr = musb_readw(epio, MUSB_RXCSR);
536 csr |= MUSB_RXCSR_H_WZC_BITS;
537 if (unlikely(do_flush))
538 musb_h_flush_rxfifo(hw_ep, csr);
539 else {
540 /* REVISIT this assumes AUTOCLEAR is never set */
541 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
542 if (!done)
543 csr |= MUSB_RXCSR_H_REQPKT;
544 musb_writew(epio, MUSB_RXCSR, csr);
545 }
546
547 return done;
548 }
549
550 /* we don't always need to reinit a given side of an endpoint...
551 * when we do, use tx/rx reinit routine and then construct a new CSR
552 * to address data toggle, NYET, and DMA or PIO.
553 *
554 * it's possible that driver bugs (especially for DMA) or aborting a
555 * transfer might have left the endpoint busier than it should be.
556 * the busy/not-empty tests are basically paranoia.
557 */
558 static void
559 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
560 {
561 u16 csr;
562
563 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
564 * That always uses tx_reinit since ep0 repurposes TX register
565 * offsets; the initial SETUP packet is also a kind of OUT.
566 */
567
568 /* if programmed for Tx, put it in RX mode */
569 if (ep->is_shared_fifo) {
570 csr = musb_readw(ep->regs, MUSB_TXCSR);
571 if (csr & MUSB_TXCSR_MODE) {
572 musb_h_tx_flush_fifo(ep);
573 csr = musb_readw(ep->regs, MUSB_TXCSR);
574 musb_writew(ep->regs, MUSB_TXCSR,
575 csr | MUSB_TXCSR_FRCDATATOG);
576 }
577
578 /*
579 * Clear the MODE bit (and everything else) to enable Rx.
580 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
581 */
582 if (csr & MUSB_TXCSR_DMAMODE)
583 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
584 musb_writew(ep->regs, MUSB_TXCSR, 0);
585
586 /* scrub all previous state, clearing toggle */
587 }
588 csr = musb_readw(ep->regs, MUSB_RXCSR);
589 if (csr & MUSB_RXCSR_RXPKTRDY)
590 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
591 musb_readw(ep->regs, MUSB_RXCOUNT));
592
593 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
594
595 /* target addr and (for multipoint) hub addr/port */
596 if (musb->is_multipoint) {
597 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
598 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
599 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
600
601 } else
602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
603
604 /* protocol/endpoint, interval/NAKlimit, i/o size */
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */
608 /* Set RXMAXP with the FIFO size of the endpoint
609 * to disable double buffer mode.
610 */
611 if (musb->double_buffer_not_ok)
612 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
613 else
614 musb_writew(ep->regs, MUSB_RXMAXP,
615 qh->maxpacket | ((qh->hb_mult - 1) << 11));
616
617 ep->rx_reinit = 0;
618 }
619
620 static bool musb_tx_dma_program(struct dma_controller *dma,
621 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
622 struct urb *urb, u32 offset, u32 length)
623 {
624 struct dma_channel *channel = hw_ep->tx_channel;
625 void __iomem *epio = hw_ep->regs;
626 u16 pkt_size = qh->maxpacket;
627 u16 csr;
628 u8 mode;
629
630 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
631 if (length > channel->max_len)
632 length = channel->max_len;
633
634 csr = musb_readw(epio, MUSB_TXCSR);
635 if (length > pkt_size) {
636 mode = 1;
637 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
638 /* autoset shouldn't be set in high bandwidth */
639 /*
640 * Enable Autoset according to table
641 * below
642 * bulk_split hb_mult Autoset_Enable
643 * 0 1 Yes(Normal)
644 * 0 >1 No(High BW ISO)
645 * 1 1 Yes(HS bulk)
646 * 1 >1 Yes(FS bulk)
647 */
648 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
649 can_bulk_split(hw_ep->musb, qh->type)))
650 csr |= MUSB_TXCSR_AUTOSET;
651 } else {
652 mode = 0;
653 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
654 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
655 }
656 channel->desired_mode = mode;
657 musb_writew(epio, MUSB_TXCSR, csr);
658 #else
659 if (!is_cppi_enabled() && !tusb_dma_omap())
660 return false;
661
662 channel->actual_len = 0;
663
664 /*
665 * TX uses "RNDIS" mode automatically but needs help
666 * to identify the zero-length-final-packet case.
667 */
668 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
669 #endif
670
671 qh->segsize = length;
672
673 /*
674 * Ensure the data reaches to main memory before starting
675 * DMA transfer
676 */
677 wmb();
678
679 if (!dma->channel_program(channel, pkt_size, mode,
680 urb->transfer_dma + offset, length)) {
681 dma->channel_release(channel);
682 hw_ep->tx_channel = NULL;
683
684 csr = musb_readw(epio, MUSB_TXCSR);
685 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
686 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
687 return false;
688 }
689 return true;
690 }
691
692 /*
693 * Program an HDRC endpoint as per the given URB
694 * Context: irqs blocked, controller lock held
695 */
696 static void musb_ep_program(struct musb *musb, u8 epnum,
697 struct urb *urb, int is_out,
698 u8 *buf, u32 offset, u32 len)
699 {
700 struct dma_controller *dma_controller;
701 struct dma_channel *dma_channel;
702 u8 dma_ok;
703 void __iomem *mbase = musb->mregs;
704 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
705 void __iomem *epio = hw_ep->regs;
706 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
707 u16 packet_sz = qh->maxpacket;
708 u8 use_dma = 1;
709 u16 csr;
710
711 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
712 "h_addr%02x h_port%02x bytes %d\n",
713 is_out ? "-->" : "<--",
714 epnum, urb, urb->dev->speed,
715 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
716 qh->h_addr_reg, qh->h_port_reg,
717 len);
718
719 musb_ep_select(mbase, epnum);
720
721 if (is_out && !len) {
722 use_dma = 0;
723 csr = musb_readw(epio, MUSB_TXCSR);
724 csr &= ~MUSB_TXCSR_DMAENAB;
725 musb_writew(epio, MUSB_TXCSR, csr);
726 hw_ep->tx_channel = NULL;
727 }
728
729 /* candidate for DMA? */
730 dma_controller = musb->dma_controller;
731 if (use_dma && is_dma_capable() && epnum && dma_controller) {
732 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
733 if (!dma_channel) {
734 dma_channel = dma_controller->channel_alloc(
735 dma_controller, hw_ep, is_out);
736 if (is_out)
737 hw_ep->tx_channel = dma_channel;
738 else
739 hw_ep->rx_channel = dma_channel;
740 }
741 } else
742 dma_channel = NULL;
743
744 /* make sure we clear DMAEnab, autoSet bits from previous run */
745
746 /* OUT/transmit/EP0 or IN/receive? */
747 if (is_out) {
748 u16 csr;
749 u16 int_txe;
750 u16 load_count;
751
752 csr = musb_readw(epio, MUSB_TXCSR);
753
754 /* disable interrupt in case we flush */
755 int_txe = musb->intrtxe;
756 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
757
758 /* general endpoint setup */
759 if (epnum) {
760 /* flush all old state, set default */
761 /*
762 * We could be flushing valid
763 * packets in double buffering
764 * case
765 */
766 if (!hw_ep->tx_double_buffered)
767 musb_h_tx_flush_fifo(hw_ep);
768
769 /*
770 * We must not clear the DMAMODE bit before or in
771 * the same cycle with the DMAENAB bit, so we clear
772 * the latter first...
773 */
774 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
775 | MUSB_TXCSR_AUTOSET
776 | MUSB_TXCSR_DMAENAB
777 | MUSB_TXCSR_FRCDATATOG
778 | MUSB_TXCSR_H_RXSTALL
779 | MUSB_TXCSR_H_ERROR
780 | MUSB_TXCSR_TXPKTRDY
781 );
782 csr |= MUSB_TXCSR_MODE;
783
784 if (!hw_ep->tx_double_buffered) {
785 if (usb_gettoggle(urb->dev, qh->epnum, 1))
786 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
787 | MUSB_TXCSR_H_DATATOGGLE;
788 else
789 csr |= MUSB_TXCSR_CLRDATATOG;
790 }
791
792 musb_writew(epio, MUSB_TXCSR, csr);
793 /* REVISIT may need to clear FLUSHFIFO ... */
794 csr &= ~MUSB_TXCSR_DMAMODE;
795 musb_writew(epio, MUSB_TXCSR, csr);
796 csr = musb_readw(epio, MUSB_TXCSR);
797 } else {
798 /* endpoint 0: just flush */
799 musb_h_ep0_flush_fifo(hw_ep);
800 }
801
802 /* target addr and (for multipoint) hub addr/port */
803 if (musb->is_multipoint) {
804 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
805 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
806 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
807 /* FIXME if !epnum, do the same for RX ... */
808 } else
809 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
810
811 /* protocol/endpoint/interval/NAKlimit */
812 if (epnum) {
813 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
814 if (musb->double_buffer_not_ok) {
815 musb_writew(epio, MUSB_TXMAXP,
816 hw_ep->max_packet_sz_tx);
817 } else if (can_bulk_split(musb, qh->type)) {
818 qh->hb_mult = hw_ep->max_packet_sz_tx
819 / packet_sz;
820 musb_writew(epio, MUSB_TXMAXP, packet_sz
821 | ((qh->hb_mult) - 1) << 11);
822 } else {
823 musb_writew(epio, MUSB_TXMAXP,
824 qh->maxpacket |
825 ((qh->hb_mult - 1) << 11));
826 }
827 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
828 } else {
829 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
830 if (musb->is_multipoint)
831 musb_writeb(epio, MUSB_TYPE0,
832 qh->type_reg);
833 }
834
835 if (can_bulk_split(musb, qh->type))
836 load_count = min((u32) hw_ep->max_packet_sz_tx,
837 len);
838 else
839 load_count = min((u32) packet_sz, len);
840
841 if (dma_channel && musb_tx_dma_program(dma_controller,
842 hw_ep, qh, urb, offset, len))
843 load_count = 0;
844
845 if (load_count) {
846 /* PIO to load FIFO */
847 qh->segsize = load_count;
848 if (!buf) {
849 sg_miter_start(&qh->sg_miter, urb->sg, 1,
850 SG_MITER_ATOMIC
851 | SG_MITER_FROM_SG);
852 if (!sg_miter_next(&qh->sg_miter)) {
853 dev_err(musb->controller,
854 "error: sg"
855 "list empty\n");
856 sg_miter_stop(&qh->sg_miter);
857 goto finish;
858 }
859 buf = qh->sg_miter.addr + urb->sg->offset +
860 urb->actual_length;
861 load_count = min_t(u32, load_count,
862 qh->sg_miter.length);
863 musb_write_fifo(hw_ep, load_count, buf);
864 qh->sg_miter.consumed = load_count;
865 sg_miter_stop(&qh->sg_miter);
866 } else
867 musb_write_fifo(hw_ep, load_count, buf);
868 }
869 finish:
870 /* re-enable interrupt */
871 musb_writew(mbase, MUSB_INTRTXE, int_txe);
872
873 /* IN/receive */
874 } else {
875 u16 csr;
876
877 if (hw_ep->rx_reinit) {
878 musb_rx_reinit(musb, qh, hw_ep);
879
880 /* init new state: toggle and NYET, maybe DMA later */
881 if (usb_gettoggle(urb->dev, qh->epnum, 0))
882 csr = MUSB_RXCSR_H_WR_DATATOGGLE
883 | MUSB_RXCSR_H_DATATOGGLE;
884 else
885 csr = 0;
886 if (qh->type == USB_ENDPOINT_XFER_INT)
887 csr |= MUSB_RXCSR_DISNYET;
888
889 } else {
890 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
891
892 if (csr & (MUSB_RXCSR_RXPKTRDY
893 | MUSB_RXCSR_DMAENAB
894 | MUSB_RXCSR_H_REQPKT))
895 ERR("broken !rx_reinit, ep%d csr %04x\n",
896 hw_ep->epnum, csr);
897
898 /* scrub any stale state, leaving toggle alone */
899 csr &= MUSB_RXCSR_DISNYET;
900 }
901
902 /* kick things off */
903
904 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
905 /* Candidate for DMA */
906 dma_channel->actual_len = 0L;
907 qh->segsize = len;
908
909 /* AUTOREQ is in a DMA register */
910 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
911 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
912
913 /*
914 * Unless caller treats short RX transfers as
915 * errors, we dare not queue multiple transfers.
916 */
917 dma_ok = dma_controller->channel_program(dma_channel,
918 packet_sz, !(urb->transfer_flags &
919 URB_SHORT_NOT_OK),
920 urb->transfer_dma + offset,
921 qh->segsize);
922 if (!dma_ok) {
923 dma_controller->channel_release(dma_channel);
924 hw_ep->rx_channel = dma_channel = NULL;
925 } else
926 csr |= MUSB_RXCSR_DMAENAB;
927 }
928
929 csr |= MUSB_RXCSR_H_REQPKT;
930 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
931 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
932 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
933 }
934 }
935
936 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
937 * the end; avoids starvation for other endpoints.
938 */
939 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
940 int is_in)
941 {
942 struct dma_channel *dma;
943 struct urb *urb;
944 void __iomem *mbase = musb->mregs;
945 void __iomem *epio = ep->regs;
946 struct musb_qh *cur_qh, *next_qh;
947 u16 rx_csr, tx_csr;
948
949 musb_ep_select(mbase, ep->epnum);
950 if (is_in) {
951 dma = is_dma_capable() ? ep->rx_channel : NULL;
952
953 /*
954 * Need to stop the transaction by clearing REQPKT first
955 * then the NAK Timeout bit ref MUSBMHDRC USB 2.0 HIGH-SPEED
956 * DUAL-ROLE CONTROLLER Programmer's Guide, section 9.2.2
957 */
958 rx_csr = musb_readw(epio, MUSB_RXCSR);
959 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
960 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
961 musb_writew(epio, MUSB_RXCSR, rx_csr);
962 rx_csr &= ~MUSB_RXCSR_DATAERROR;
963 musb_writew(epio, MUSB_RXCSR, rx_csr);
964
965 cur_qh = first_qh(&musb->in_bulk);
966 } else {
967 dma = is_dma_capable() ? ep->tx_channel : NULL;
968
969 /* clear nak timeout bit */
970 tx_csr = musb_readw(epio, MUSB_TXCSR);
971 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
972 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
973 musb_writew(epio, MUSB_TXCSR, tx_csr);
974
975 cur_qh = first_qh(&musb->out_bulk);
976 }
977 if (cur_qh) {
978 urb = next_urb(cur_qh);
979 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
980 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
981 musb->dma_controller->channel_abort(dma);
982 urb->actual_length += dma->actual_len;
983 dma->actual_len = 0L;
984 }
985 musb_save_toggle(cur_qh, is_in, urb);
986
987 if (is_in) {
988 /* move cur_qh to end of queue */
989 list_move_tail(&cur_qh->ring, &musb->in_bulk);
990
991 /* get the next qh from musb->in_bulk */
992 next_qh = first_qh(&musb->in_bulk);
993
994 /* set rx_reinit and schedule the next qh */
995 ep->rx_reinit = 1;
996 } else {
997 /* move cur_qh to end of queue */
998 list_move_tail(&cur_qh->ring, &musb->out_bulk);
999
1000 /* get the next qh from musb->out_bulk */
1001 next_qh = first_qh(&musb->out_bulk);
1002
1003 /* set tx_reinit and schedule the next qh */
1004 ep->tx_reinit = 1;
1005 }
1006 musb_start_urb(musb, is_in, next_qh);
1007 }
1008 }
1009
1010 /*
1011 * Service the default endpoint (ep0) as host.
1012 * Return true until it's time to start the status stage.
1013 */
1014 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1015 {
1016 bool more = false;
1017 u8 *fifo_dest = NULL;
1018 u16 fifo_count = 0;
1019 struct musb_hw_ep *hw_ep = musb->control_ep;
1020 struct musb_qh *qh = hw_ep->in_qh;
1021 struct usb_ctrlrequest *request;
1022
1023 switch (musb->ep0_stage) {
1024 case MUSB_EP0_IN:
1025 fifo_dest = urb->transfer_buffer + urb->actual_length;
1026 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1027 urb->actual_length);
1028 if (fifo_count < len)
1029 urb->status = -EOVERFLOW;
1030
1031 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1032
1033 urb->actual_length += fifo_count;
1034 if (len < qh->maxpacket) {
1035 /* always terminate on short read; it's
1036 * rarely reported as an error.
1037 */
1038 } else if (urb->actual_length <
1039 urb->transfer_buffer_length)
1040 more = true;
1041 break;
1042 case MUSB_EP0_START:
1043 request = (struct usb_ctrlrequest *) urb->setup_packet;
1044
1045 if (!request->wLength) {
1046 dev_dbg(musb->controller, "start no-DATA\n");
1047 break;
1048 } else if (request->bRequestType & USB_DIR_IN) {
1049 dev_dbg(musb->controller, "start IN-DATA\n");
1050 musb->ep0_stage = MUSB_EP0_IN;
1051 more = true;
1052 break;
1053 } else {
1054 dev_dbg(musb->controller, "start OUT-DATA\n");
1055 musb->ep0_stage = MUSB_EP0_OUT;
1056 more = true;
1057 }
1058 /* FALLTHROUGH */
1059 case MUSB_EP0_OUT:
1060 fifo_count = min_t(size_t, qh->maxpacket,
1061 urb->transfer_buffer_length -
1062 urb->actual_length);
1063 if (fifo_count) {
1064 fifo_dest = (u8 *) (urb->transfer_buffer
1065 + urb->actual_length);
1066 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
1067 fifo_count,
1068 (fifo_count == 1) ? "" : "s",
1069 fifo_dest);
1070 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1071
1072 urb->actual_length += fifo_count;
1073 more = true;
1074 }
1075 break;
1076 default:
1077 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1078 break;
1079 }
1080
1081 return more;
1082 }
1083
1084 /*
1085 * Handle default endpoint interrupt as host. Only called in IRQ time
1086 * from musb_interrupt().
1087 *
1088 * called with controller irqlocked
1089 */
1090 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1091 {
1092 struct urb *urb;
1093 u16 csr, len;
1094 int status = 0;
1095 void __iomem *mbase = musb->mregs;
1096 struct musb_hw_ep *hw_ep = musb->control_ep;
1097 void __iomem *epio = hw_ep->regs;
1098 struct musb_qh *qh = hw_ep->in_qh;
1099 bool complete = false;
1100 irqreturn_t retval = IRQ_NONE;
1101
1102 /* ep0 only has one queue, "in" */
1103 urb = next_urb(qh);
1104
1105 musb_ep_select(mbase, 0);
1106 csr = musb_readw(epio, MUSB_CSR0);
1107 len = (csr & MUSB_CSR0_RXPKTRDY)
1108 ? musb_readb(epio, MUSB_COUNT0)
1109 : 0;
1110
1111 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1112 csr, qh, len, urb, musb->ep0_stage);
1113
1114 /* if we just did status stage, we are done */
1115 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1116 retval = IRQ_HANDLED;
1117 complete = true;
1118 }
1119
1120 /* prepare status */
1121 if (csr & MUSB_CSR0_H_RXSTALL) {
1122 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1123 status = -EPIPE;
1124
1125 } else if (csr & MUSB_CSR0_H_ERROR) {
1126 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1127 status = -EPROTO;
1128
1129 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1130 dev_dbg(musb->controller, "control NAK timeout\n");
1131
1132 /* NOTE: this code path would be a good place to PAUSE a
1133 * control transfer, if another one is queued, so that
1134 * ep0 is more likely to stay busy. That's already done
1135 * for bulk RX transfers.
1136 *
1137 * if (qh->ring.next != &musb->control), then
1138 * we have a candidate... NAKing is *NOT* an error
1139 */
1140 musb_writew(epio, MUSB_CSR0, 0);
1141 retval = IRQ_HANDLED;
1142 }
1143
1144 if (status) {
1145 dev_dbg(musb->controller, "aborting\n");
1146 retval = IRQ_HANDLED;
1147 if (urb)
1148 urb->status = status;
1149 complete = true;
1150
1151 /* use the proper sequence to abort the transfer */
1152 if (csr & MUSB_CSR0_H_REQPKT) {
1153 csr &= ~MUSB_CSR0_H_REQPKT;
1154 musb_writew(epio, MUSB_CSR0, csr);
1155 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1156 musb_writew(epio, MUSB_CSR0, csr);
1157 } else {
1158 musb_h_ep0_flush_fifo(hw_ep);
1159 }
1160
1161 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1162
1163 /* clear it */
1164 musb_writew(epio, MUSB_CSR0, 0);
1165 }
1166
1167 if (unlikely(!urb)) {
1168 /* stop endpoint since we have no place for its data, this
1169 * SHOULD NEVER HAPPEN! */
1170 ERR("no URB for end 0\n");
1171
1172 musb_h_ep0_flush_fifo(hw_ep);
1173 goto done;
1174 }
1175
1176 if (!complete) {
1177 /* call common logic and prepare response */
1178 if (musb_h_ep0_continue(musb, len, urb)) {
1179 /* more packets required */
1180 csr = (MUSB_EP0_IN == musb->ep0_stage)
1181 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1182 } else {
1183 /* data transfer complete; perform status phase */
1184 if (usb_pipeout(urb->pipe)
1185 || !urb->transfer_buffer_length)
1186 csr = MUSB_CSR0_H_STATUSPKT
1187 | MUSB_CSR0_H_REQPKT;
1188 else
1189 csr = MUSB_CSR0_H_STATUSPKT
1190 | MUSB_CSR0_TXPKTRDY;
1191
1192 /* flag status stage */
1193 musb->ep0_stage = MUSB_EP0_STATUS;
1194
1195 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1196
1197 }
1198 musb_writew(epio, MUSB_CSR0, csr);
1199 retval = IRQ_HANDLED;
1200 } else
1201 musb->ep0_stage = MUSB_EP0_IDLE;
1202
1203 /* call completion handler if done */
1204 if (complete)
1205 musb_advance_schedule(musb, urb, hw_ep, 1);
1206 done:
1207 return retval;
1208 }
1209
1210
1211 #ifdef CONFIG_USB_INVENTRA_DMA
1212
1213 /* Host side TX (OUT) using Mentor DMA works as follows:
1214 submit_urb ->
1215 - if queue was empty, Program Endpoint
1216 - ... which starts DMA to fifo in mode 1 or 0
1217
1218 DMA Isr (transfer complete) -> TxAvail()
1219 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1220 only in musb_cleanup_urb)
1221 - TxPktRdy has to be set in mode 0 or for
1222 short packets in mode 1.
1223 */
1224
1225 #endif
1226
1227 /* Service a Tx-Available or dma completion irq for the endpoint */
1228 void musb_host_tx(struct musb *musb, u8 epnum)
1229 {
1230 int pipe;
1231 bool done = false;
1232 u16 tx_csr;
1233 size_t length = 0;
1234 size_t offset = 0;
1235 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1236 void __iomem *epio = hw_ep->regs;
1237 struct musb_qh *qh = hw_ep->out_qh;
1238 struct urb *urb = next_urb(qh);
1239 u32 status = 0;
1240 void __iomem *mbase = musb->mregs;
1241 struct dma_channel *dma;
1242 bool transfer_pending = false;
1243
1244 musb_ep_select(mbase, epnum);
1245 tx_csr = musb_readw(epio, MUSB_TXCSR);
1246
1247 /* with CPPI, DMA sometimes triggers "extra" irqs */
1248 if (!urb) {
1249 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1250 return;
1251 }
1252
1253 pipe = urb->pipe;
1254 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1255 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1256 dma ? ", dma" : "");
1257
1258 /* check for errors */
1259 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1260 /* dma was disabled, fifo flushed */
1261 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1262
1263 /* stall; record URB status */
1264 status = -EPIPE;
1265
1266 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1267 /* (NON-ISO) dma was disabled, fifo flushed */
1268 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1269
1270 status = -ETIMEDOUT;
1271
1272 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1273 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1274 && !list_is_singular(&musb->out_bulk)) {
1275 dev_dbg(musb->controller,
1276 "NAK timeout on TX%d ep\n", epnum);
1277 musb_bulk_nak_timeout(musb, hw_ep, 0);
1278 } else {
1279 dev_dbg(musb->controller,
1280 "TX end=%d device not responding\n", epnum);
1281 /* NOTE: this code path would be a good place to PAUSE a
1282 * transfer, if there's some other (nonperiodic) tx urb
1283 * that could use this fifo. (dma complicates it...)
1284 * That's already done for bulk RX transfers.
1285 *
1286 * if (bulk && qh->ring.next != &musb->out_bulk), then
1287 * we have a candidate... NAKing is *NOT* an error
1288 */
1289 musb_ep_select(mbase, epnum);
1290 musb_writew(epio, MUSB_TXCSR,
1291 MUSB_TXCSR_H_WZC_BITS
1292 | MUSB_TXCSR_TXPKTRDY);
1293 }
1294 return;
1295 }
1296
1297 done:
1298 if (status) {
1299 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1300 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1301 (void) musb->dma_controller->channel_abort(dma);
1302 }
1303
1304 /* do the proper sequence to abort the transfer in the
1305 * usb core; the dma engine should already be stopped.
1306 */
1307 musb_h_tx_flush_fifo(hw_ep);
1308 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1309 | MUSB_TXCSR_DMAENAB
1310 | MUSB_TXCSR_H_ERROR
1311 | MUSB_TXCSR_H_RXSTALL
1312 | MUSB_TXCSR_H_NAKTIMEOUT
1313 );
1314
1315 musb_ep_select(mbase, epnum);
1316 musb_writew(epio, MUSB_TXCSR, tx_csr);
1317 /* REVISIT may need to clear FLUSHFIFO ... */
1318 musb_writew(epio, MUSB_TXCSR, tx_csr);
1319 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1320
1321 done = true;
1322 }
1323
1324 /* second cppi case */
1325 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1326 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1327 return;
1328 }
1329
1330 if (is_dma_capable() && dma && !status) {
1331 /*
1332 * DMA has completed. But if we're using DMA mode 1 (multi
1333 * packet DMA), we need a terminal TXPKTRDY interrupt before
1334 * we can consider this transfer completed, lest we trash
1335 * its last packet when writing the next URB's data. So we
1336 * switch back to mode 0 to get that interrupt; we'll come
1337 * back here once it happens.
1338 */
1339 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1340 /*
1341 * We shouldn't clear DMAMODE with DMAENAB set; so
1342 * clear them in a safe order. That should be OK
1343 * once TXPKTRDY has been set (and I've never seen
1344 * it being 0 at this moment -- DMA interrupt latency
1345 * is significant) but if it hasn't been then we have
1346 * no choice but to stop being polite and ignore the
1347 * programmer's guide... :-)
1348 *
1349 * Note that we must write TXCSR with TXPKTRDY cleared
1350 * in order not to re-trigger the packet send (this bit
1351 * can't be cleared by CPU), and there's another caveat:
1352 * TXPKTRDY may be set shortly and then cleared in the
1353 * double-buffered FIFO mode, so we do an extra TXCSR
1354 * read for debouncing...
1355 */
1356 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1357 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1358 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1359 MUSB_TXCSR_TXPKTRDY);
1360 musb_writew(epio, MUSB_TXCSR,
1361 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1362 }
1363 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1364 MUSB_TXCSR_TXPKTRDY);
1365 musb_writew(epio, MUSB_TXCSR,
1366 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1367
1368 /*
1369 * There is no guarantee that we'll get an interrupt
1370 * after clearing DMAMODE as we might have done this
1371 * too late (after TXPKTRDY was cleared by controller).
1372 * Re-read TXCSR as we have spoiled its previous value.
1373 */
1374 tx_csr = musb_readw(epio, MUSB_TXCSR);
1375 }
1376
1377 /*
1378 * We may get here from a DMA completion or TXPKTRDY interrupt.
1379 * In any case, we must check the FIFO status here and bail out
1380 * only if the FIFO still has data -- that should prevent the
1381 * "missed" TXPKTRDY interrupts and deal with double-buffered
1382 * FIFO mode too...
1383 */
1384 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1385 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1386 "CSR %04x\n", tx_csr);
1387 return;
1388 }
1389 }
1390
1391 if (!status || dma || usb_pipeisoc(pipe)) {
1392 if (dma)
1393 length = dma->actual_len;
1394 else
1395 length = qh->segsize;
1396 qh->offset += length;
1397
1398 if (usb_pipeisoc(pipe)) {
1399 struct usb_iso_packet_descriptor *d;
1400
1401 d = urb->iso_frame_desc + qh->iso_idx;
1402 d->actual_length = length;
1403 d->status = status;
1404 if (++qh->iso_idx >= urb->number_of_packets) {
1405 done = true;
1406 } else {
1407 d++;
1408 offset = d->offset;
1409 length = d->length;
1410 }
1411 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1412 done = true;
1413 } else {
1414 /* see if we need to send more data, or ZLP */
1415 if (qh->segsize < qh->maxpacket)
1416 done = true;
1417 else if (qh->offset == urb->transfer_buffer_length
1418 && !(urb->transfer_flags
1419 & URB_ZERO_PACKET))
1420 done = true;
1421 if (!done) {
1422 offset = qh->offset;
1423 length = urb->transfer_buffer_length - offset;
1424 transfer_pending = true;
1425 }
1426 }
1427 }
1428
1429 /* urb->status != -EINPROGRESS means request has been faulted,
1430 * so we must abort this transfer after cleanup
1431 */
1432 if (urb->status != -EINPROGRESS) {
1433 done = true;
1434 if (status == 0)
1435 status = urb->status;
1436 }
1437
1438 if (done) {
1439 /* set status */
1440 urb->status = status;
1441 urb->actual_length = qh->offset;
1442 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1443 return;
1444 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1445 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1446 offset, length)) {
1447 if (is_cppi_enabled() || tusb_dma_omap())
1448 musb_h_tx_dma_start(hw_ep);
1449 return;
1450 }
1451 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1452 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1453 return;
1454 }
1455
1456 /*
1457 * PIO: start next packet in this URB.
1458 *
1459 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1460 * (and presumably, FIFO is not half-full) we should write *two*
1461 * packets before updating TXCSR; other docs disagree...
1462 */
1463 if (length > qh->maxpacket)
1464 length = qh->maxpacket;
1465 /* Unmap the buffer so that CPU can use it */
1466 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1467
1468 /*
1469 * We need to map sg if the transfer_buffer is
1470 * NULL.
1471 */
1472 if (!urb->transfer_buffer)
1473 qh->use_sg = true;
1474
1475 if (qh->use_sg) {
1476 /* sg_miter_start is already done in musb_ep_program */
1477 if (!sg_miter_next(&qh->sg_miter)) {
1478 dev_err(musb->controller, "error: sg list empty\n");
1479 sg_miter_stop(&qh->sg_miter);
1480 status = -EINVAL;
1481 goto done;
1482 }
1483 urb->transfer_buffer = qh->sg_miter.addr;
1484 length = min_t(u32, length, qh->sg_miter.length);
1485 musb_write_fifo(hw_ep, length, urb->transfer_buffer);
1486 qh->sg_miter.consumed = length;
1487 sg_miter_stop(&qh->sg_miter);
1488 } else {
1489 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1490 }
1491
1492 qh->segsize = length;
1493
1494 if (qh->use_sg) {
1495 if (offset + length >= urb->transfer_buffer_length)
1496 qh->use_sg = false;
1497 }
1498
1499 musb_ep_select(mbase, epnum);
1500 musb_writew(epio, MUSB_TXCSR,
1501 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1502 }
1503
1504
1505 #ifdef CONFIG_USB_INVENTRA_DMA
1506
1507 /* Host side RX (IN) using Mentor DMA works as follows:
1508 submit_urb ->
1509 - if queue was empty, ProgramEndpoint
1510 - first IN token is sent out (by setting ReqPkt)
1511 LinuxIsr -> RxReady()
1512 /\ => first packet is received
1513 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1514 | -> DMA Isr (transfer complete) -> RxReady()
1515 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1516 | - if urb not complete, send next IN token (ReqPkt)
1517 | | else complete urb.
1518 | |
1519 ---------------------------
1520 *
1521 * Nuances of mode 1:
1522 * For short packets, no ack (+RxPktRdy) is sent automatically
1523 * (even if AutoClear is ON)
1524 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1525 * automatically => major problem, as collecting the next packet becomes
1526 * difficult. Hence mode 1 is not used.
1527 *
1528 * REVISIT
1529 * All we care about at this driver level is that
1530 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1531 * (b) termination conditions are: short RX, or buffer full;
1532 * (c) fault modes include
1533 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1534 * (and that endpoint's dma queue stops immediately)
1535 * - overflow (full, PLUS more bytes in the terminal packet)
1536 *
1537 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1538 * thus be a great candidate for using mode 1 ... for all but the
1539 * last packet of one URB's transfer.
1540 */
1541
1542 #endif
1543
1544 /*
1545 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1546 * and high-bandwidth IN transfer cases.
1547 */
1548 void musb_host_rx(struct musb *musb, u8 epnum)
1549 {
1550 struct urb *urb;
1551 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1552 void __iomem *epio = hw_ep->regs;
1553 struct musb_qh *qh = hw_ep->in_qh;
1554 size_t xfer_len;
1555 void __iomem *mbase = musb->mregs;
1556 int pipe;
1557 u16 rx_csr, val;
1558 bool iso_err = false;
1559 bool done = false;
1560 u32 status;
1561 struct dma_channel *dma;
1562 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1563
1564 musb_ep_select(mbase, epnum);
1565
1566 urb = next_urb(qh);
1567 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1568 status = 0;
1569 xfer_len = 0;
1570
1571 rx_csr = musb_readw(epio, MUSB_RXCSR);
1572 val = rx_csr;
1573
1574 if (unlikely(!urb)) {
1575 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1576 * usbtest #11 (unlinks) triggers it regularly, sometimes
1577 * with fifo full. (Only with DMA??)
1578 */
1579 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1580 musb_readw(epio, MUSB_RXCOUNT));
1581 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1582 return;
1583 }
1584
1585 pipe = urb->pipe;
1586
1587 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1588 epnum, rx_csr, urb->actual_length,
1589 dma ? dma->actual_len : 0);
1590
1591 /* check for errors, concurrent stall & unlink is not really
1592 * handled yet! */
1593 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1594 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1595
1596 /* stall; record URB status */
1597 status = -EPIPE;
1598
1599 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1600 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1601
1602 status = -EPROTO;
1603 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1604
1605 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1606
1607 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1608 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1609
1610 /* NOTE: NAKing is *NOT* an error, so we want to
1611 * continue. Except ... if there's a request for
1612 * another QH, use that instead of starving it.
1613 *
1614 * Devices like Ethernet and serial adapters keep
1615 * reads posted at all times, which will starve
1616 * other devices without this logic.
1617 */
1618 if (usb_pipebulk(urb->pipe)
1619 && qh->mux == 1
1620 && !list_is_singular(&musb->in_bulk)) {
1621 musb_bulk_nak_timeout(musb, hw_ep, 1);
1622 return;
1623 }
1624 musb_ep_select(mbase, epnum);
1625 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1626 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1627 musb_writew(epio, MUSB_RXCSR, rx_csr);
1628
1629 goto finish;
1630 } else {
1631 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1632 /* packet error reported later */
1633 iso_err = true;
1634 }
1635 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1636 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1637 epnum);
1638 status = -EPROTO;
1639 }
1640
1641 /* faults abort the transfer */
1642 if (status) {
1643 /* clean up dma and collect transfer count */
1644 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1645 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1646 (void) musb->dma_controller->channel_abort(dma);
1647 xfer_len = dma->actual_len;
1648 }
1649 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1650 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1651 done = true;
1652 goto finish;
1653 }
1654
1655 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1656 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1657 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1658 goto finish;
1659 }
1660
1661 /* thorough shutdown for now ... given more precise fault handling
1662 * and better queueing support, we might keep a DMA pipeline going
1663 * while processing this irq for earlier completions.
1664 */
1665
1666 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1667
1668 #if !defined(CONFIG_USB_INVENTRA_DMA) && !defined(CONFIG_USB_UX500_DMA)
1669 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1670 /* REVISIT this happened for a while on some short reads...
1671 * the cleanup still needs investigation... looks bad...
1672 * and also duplicates dma cleanup code above ... plus,
1673 * shouldn't this be the "half full" double buffer case?
1674 */
1675 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1676 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1677 (void) musb->dma_controller->channel_abort(dma);
1678 xfer_len = dma->actual_len;
1679 done = true;
1680 }
1681
1682 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1683 xfer_len, dma ? ", dma" : "");
1684 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1685
1686 musb_ep_select(mbase, epnum);
1687 musb_writew(epio, MUSB_RXCSR,
1688 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1689 }
1690 #endif
1691 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1692 xfer_len = dma->actual_len;
1693
1694 val &= ~(MUSB_RXCSR_DMAENAB
1695 | MUSB_RXCSR_H_AUTOREQ
1696 | MUSB_RXCSR_AUTOCLEAR
1697 | MUSB_RXCSR_RXPKTRDY);
1698 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1699
1700 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
1701 if (usb_pipeisoc(pipe)) {
1702 struct usb_iso_packet_descriptor *d;
1703
1704 d = urb->iso_frame_desc + qh->iso_idx;
1705 d->actual_length = xfer_len;
1706
1707 /* even if there was an error, we did the dma
1708 * for iso_frame_desc->length
1709 */
1710 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1711 d->status = 0;
1712
1713 if (++qh->iso_idx >= urb->number_of_packets)
1714 done = true;
1715 else
1716 done = false;
1717
1718 } else {
1719 /* done if urb buffer is full or short packet is recd */
1720 done = (urb->actual_length + xfer_len >=
1721 urb->transfer_buffer_length
1722 || dma->actual_len < qh->maxpacket);
1723 }
1724
1725 /* send IN token for next packet, without AUTOREQ */
1726 if (!done) {
1727 val |= MUSB_RXCSR_H_REQPKT;
1728 musb_writew(epio, MUSB_RXCSR,
1729 MUSB_RXCSR_H_WZC_BITS | val);
1730 }
1731
1732 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1733 done ? "off" : "reset",
1734 musb_readw(epio, MUSB_RXCSR),
1735 musb_readw(epio, MUSB_RXCOUNT));
1736 #else
1737 done = true;
1738 #endif
1739 } else if (urb->status == -EINPROGRESS) {
1740 /* if no errors, be sure a packet is ready for unloading */
1741 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1742 status = -EPROTO;
1743 ERR("Rx interrupt with no errors or packet!\n");
1744
1745 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1746
1747 /* SCRUB (RX) */
1748 /* do the proper sequence to abort the transfer */
1749 musb_ep_select(mbase, epnum);
1750 val &= ~MUSB_RXCSR_H_REQPKT;
1751 musb_writew(epio, MUSB_RXCSR, val);
1752 goto finish;
1753 }
1754
1755 /* we are expecting IN packets */
1756 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
1757 if (dma) {
1758 struct dma_controller *c;
1759 u16 rx_count;
1760 int ret, length;
1761 dma_addr_t buf;
1762
1763 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1764
1765 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n",
1766 epnum, rx_count,
1767 (unsigned long long) urb->transfer_dma
1768 + urb->actual_length,
1769 qh->offset,
1770 urb->transfer_buffer_length);
1771
1772 c = musb->dma_controller;
1773
1774 if (usb_pipeisoc(pipe)) {
1775 int d_status = 0;
1776 struct usb_iso_packet_descriptor *d;
1777
1778 d = urb->iso_frame_desc + qh->iso_idx;
1779
1780 if (iso_err) {
1781 d_status = -EILSEQ;
1782 urb->error_count++;
1783 }
1784 if (rx_count > d->length) {
1785 if (d_status == 0) {
1786 d_status = -EOVERFLOW;
1787 urb->error_count++;
1788 }
1789 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1790 rx_count, d->length);
1791
1792 length = d->length;
1793 } else
1794 length = rx_count;
1795 d->status = d_status;
1796 buf = urb->transfer_dma + d->offset;
1797 } else {
1798 length = rx_count;
1799 buf = urb->transfer_dma +
1800 urb->actual_length;
1801 }
1802
1803 dma->desired_mode = 0;
1804 #ifdef USE_MODE1
1805 /* because of the issue below, mode 1 will
1806 * only rarely behave with correct semantics.
1807 */
1808 if ((urb->transfer_flags &
1809 URB_SHORT_NOT_OK)
1810 && (urb->transfer_buffer_length -
1811 urb->actual_length)
1812 > qh->maxpacket)
1813 dma->desired_mode = 1;
1814 if (rx_count < hw_ep->max_packet_sz_rx) {
1815 length = rx_count;
1816 dma->desired_mode = 0;
1817 } else {
1818 length = urb->transfer_buffer_length;
1819 }
1820 #endif
1821
1822 /* Disadvantage of using mode 1:
1823 * It's basically usable only for mass storage class; essentially all
1824 * other protocols also terminate transfers on short packets.
1825 *
1826 * Details:
1827 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1828 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1829 * to use the extra IN token to grab the last packet using mode 0, then
1830 * the problem is that you cannot be sure when the device will send the
1831 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1832 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1833 * transfer, while sometimes it is recd just a little late so that if you
1834 * try to configure for mode 0 soon after the mode 1 transfer is
1835 * completed, you will find rxcount 0. Okay, so you might think why not
1836 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1837 */
1838
1839 val = musb_readw(epio, MUSB_RXCSR);
1840 val &= ~MUSB_RXCSR_H_REQPKT;
1841
1842 if (dma->desired_mode == 0)
1843 val &= ~MUSB_RXCSR_H_AUTOREQ;
1844 else
1845 val |= MUSB_RXCSR_H_AUTOREQ;
1846 val |= MUSB_RXCSR_DMAENAB;
1847
1848 /* autoclear shouldn't be set in high bandwidth */
1849 if (qh->hb_mult == 1)
1850 val |= MUSB_RXCSR_AUTOCLEAR;
1851
1852 musb_writew(epio, MUSB_RXCSR,
1853 MUSB_RXCSR_H_WZC_BITS | val);
1854
1855 /* REVISIT if when actual_length != 0,
1856 * transfer_buffer_length needs to be
1857 * adjusted first...
1858 */
1859 ret = c->channel_program(
1860 dma, qh->maxpacket,
1861 dma->desired_mode, buf, length);
1862
1863 if (!ret) {
1864 c->channel_release(dma);
1865 hw_ep->rx_channel = NULL;
1866 dma = NULL;
1867 val = musb_readw(epio, MUSB_RXCSR);
1868 val &= ~(MUSB_RXCSR_DMAENAB
1869 | MUSB_RXCSR_H_AUTOREQ
1870 | MUSB_RXCSR_AUTOCLEAR);
1871 musb_writew(epio, MUSB_RXCSR, val);
1872 }
1873 }
1874 #endif /* Mentor DMA */
1875
1876 if (!dma) {
1877 unsigned int received_len;
1878
1879 /* Unmap the buffer so that CPU can use it */
1880 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1881
1882 /*
1883 * We need to map sg if the transfer_buffer is
1884 * NULL.
1885 */
1886 if (!urb->transfer_buffer) {
1887 qh->use_sg = true;
1888 sg_miter_start(&qh->sg_miter, urb->sg, 1,
1889 sg_flags);
1890 }
1891
1892 if (qh->use_sg) {
1893 if (!sg_miter_next(&qh->sg_miter)) {
1894 dev_err(musb->controller, "error: sg list empty\n");
1895 sg_miter_stop(&qh->sg_miter);
1896 status = -EINVAL;
1897 done = true;
1898 goto finish;
1899 }
1900 urb->transfer_buffer = qh->sg_miter.addr;
1901 received_len = urb->actual_length;
1902 qh->offset = 0x0;
1903 done = musb_host_packet_rx(musb, urb, epnum,
1904 iso_err);
1905 /* Calculate the number of bytes received */
1906 received_len = urb->actual_length -
1907 received_len;
1908 qh->sg_miter.consumed = received_len;
1909 sg_miter_stop(&qh->sg_miter);
1910 } else {
1911 done = musb_host_packet_rx(musb, urb,
1912 epnum, iso_err);
1913 }
1914 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1915 }
1916 }
1917
1918 finish:
1919 urb->actual_length += xfer_len;
1920 qh->offset += xfer_len;
1921 if (done) {
1922 if (qh->use_sg)
1923 qh->use_sg = false;
1924
1925 if (urb->status == -EINPROGRESS)
1926 urb->status = status;
1927 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1928 }
1929 }
1930
1931 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1932 * the software schedule associates multiple such nodes with a given
1933 * host side hardware endpoint + direction; scheduling may activate
1934 * that hardware endpoint.
1935 */
1936 static int musb_schedule(
1937 struct musb *musb,
1938 struct musb_qh *qh,
1939 int is_in)
1940 {
1941 int idle;
1942 int best_diff;
1943 int best_end, epnum;
1944 struct musb_hw_ep *hw_ep = NULL;
1945 struct list_head *head = NULL;
1946 u8 toggle;
1947 u8 txtype;
1948 struct urb *urb = next_urb(qh);
1949
1950 /* use fixed hardware for control and bulk */
1951 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1952 head = &musb->control;
1953 hw_ep = musb->control_ep;
1954 goto success;
1955 }
1956
1957 /* else, periodic transfers get muxed to other endpoints */
1958
1959 /*
1960 * We know this qh hasn't been scheduled, so all we need to do
1961 * is choose which hardware endpoint to put it on ...
1962 *
1963 * REVISIT what we really want here is a regular schedule tree
1964 * like e.g. OHCI uses.
1965 */
1966 best_diff = 4096;
1967 best_end = -1;
1968
1969 for (epnum = 1, hw_ep = musb->endpoints + 1;
1970 epnum < musb->nr_endpoints;
1971 epnum++, hw_ep++) {
1972 int diff;
1973
1974 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1975 continue;
1976
1977 if (hw_ep == musb->bulk_ep)
1978 continue;
1979
1980 if (is_in)
1981 diff = hw_ep->max_packet_sz_rx;
1982 else
1983 diff = hw_ep->max_packet_sz_tx;
1984 diff -= (qh->maxpacket * qh->hb_mult);
1985
1986 if (diff >= 0 && best_diff > diff) {
1987
1988 /*
1989 * Mentor controller has a bug in that if we schedule
1990 * a BULK Tx transfer on an endpoint that had earlier
1991 * handled ISOC then the BULK transfer has to start on
1992 * a zero toggle. If the BULK transfer starts on a 1
1993 * toggle then this transfer will fail as the mentor
1994 * controller starts the Bulk transfer on a 0 toggle
1995 * irrespective of the programming of the toggle bits
1996 * in the TXCSR register. Check for this condition
1997 * while allocating the EP for a Tx Bulk transfer. If
1998 * so skip this EP.
1999 */
2000 hw_ep = musb->endpoints + epnum;
2001 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
2002 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
2003 >> 4) & 0x3;
2004 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
2005 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2006 continue;
2007
2008 best_diff = diff;
2009 best_end = epnum;
2010 }
2011 }
2012 /* use bulk reserved ep1 if no other ep is free */
2013 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2014 hw_ep = musb->bulk_ep;
2015 if (is_in)
2016 head = &musb->in_bulk;
2017 else
2018 head = &musb->out_bulk;
2019
2020 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
2021 * multiplexed. This scheme doen't work in high speed to full
2022 * speed scenario as NAK interrupts are not coming from a
2023 * full speed device connected to a high speed device.
2024 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2025 * 4 (8 frame or 8ms) for FS device.
2026 */
2027 if (qh->dev)
2028 qh->intv_reg =
2029 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2030 goto success;
2031 } else if (best_end < 0) {
2032 return -ENOSPC;
2033 }
2034
2035 idle = 1;
2036 qh->mux = 0;
2037 hw_ep = musb->endpoints + best_end;
2038 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
2039 success:
2040 if (head) {
2041 idle = list_empty(head);
2042 list_add_tail(&qh->ring, head);
2043 qh->mux = 1;
2044 }
2045 qh->hw_ep = hw_ep;
2046 qh->hep->hcpriv = qh;
2047 if (idle)
2048 musb_start_urb(musb, is_in, qh);
2049 return 0;
2050 }
2051
2052 static int musb_urb_enqueue(
2053 struct usb_hcd *hcd,
2054 struct urb *urb,
2055 gfp_t mem_flags)
2056 {
2057 unsigned long flags;
2058 struct musb *musb = hcd_to_musb(hcd);
2059 struct usb_host_endpoint *hep = urb->ep;
2060 struct musb_qh *qh;
2061 struct usb_endpoint_descriptor *epd = &hep->desc;
2062 int ret;
2063 unsigned type_reg;
2064 unsigned interval;
2065
2066 /* host role must be active */
2067 if (!is_host_active(musb) || !musb->is_active)
2068 return -ENODEV;
2069
2070 spin_lock_irqsave(&musb->lock, flags);
2071 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2072 qh = ret ? NULL : hep->hcpriv;
2073 if (qh)
2074 urb->hcpriv = qh;
2075 spin_unlock_irqrestore(&musb->lock, flags);
2076
2077 /* DMA mapping was already done, if needed, and this urb is on
2078 * hep->urb_list now ... so we're done, unless hep wasn't yet
2079 * scheduled onto a live qh.
2080 *
2081 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2082 * disabled, testing for empty qh->ring and avoiding qh setup costs
2083 * except for the first urb queued after a config change.
2084 */
2085 if (qh || ret)
2086 return ret;
2087
2088 /* Allocate and initialize qh, minimizing the work done each time
2089 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2090 *
2091 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2092 * for bugs in other kernel code to break this driver...
2093 */
2094 qh = kzalloc(sizeof *qh, mem_flags);
2095 if (!qh) {
2096 spin_lock_irqsave(&musb->lock, flags);
2097 usb_hcd_unlink_urb_from_ep(hcd, urb);
2098 spin_unlock_irqrestore(&musb->lock, flags);
2099 return -ENOMEM;
2100 }
2101
2102 qh->hep = hep;
2103 qh->dev = urb->dev;
2104 INIT_LIST_HEAD(&qh->ring);
2105 qh->is_ready = 1;
2106
2107 qh->maxpacket = usb_endpoint_maxp(epd);
2108 qh->type = usb_endpoint_type(epd);
2109
2110 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2111 * Some musb cores don't support high bandwidth ISO transfers; and
2112 * we don't (yet!) support high bandwidth interrupt transfers.
2113 */
2114 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
2115 if (qh->hb_mult > 1) {
2116 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2117
2118 if (ok)
2119 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2120 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2121 if (!ok) {
2122 ret = -EMSGSIZE;
2123 goto done;
2124 }
2125 qh->maxpacket &= 0x7ff;
2126 }
2127
2128 qh->epnum = usb_endpoint_num(epd);
2129
2130 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2131 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2132
2133 /* precompute rxtype/txtype/type0 register */
2134 type_reg = (qh->type << 4) | qh->epnum;
2135 switch (urb->dev->speed) {
2136 case USB_SPEED_LOW:
2137 type_reg |= 0xc0;
2138 break;
2139 case USB_SPEED_FULL:
2140 type_reg |= 0x80;
2141 break;
2142 default:
2143 type_reg |= 0x40;
2144 }
2145 qh->type_reg = type_reg;
2146
2147 /* Precompute RXINTERVAL/TXINTERVAL register */
2148 switch (qh->type) {
2149 case USB_ENDPOINT_XFER_INT:
2150 /*
2151 * Full/low speeds use the linear encoding,
2152 * high speed uses the logarithmic encoding.
2153 */
2154 if (urb->dev->speed <= USB_SPEED_FULL) {
2155 interval = max_t(u8, epd->bInterval, 1);
2156 break;
2157 }
2158 /* FALLTHROUGH */
2159 case USB_ENDPOINT_XFER_ISOC:
2160 /* ISO always uses logarithmic encoding */
2161 interval = min_t(u8, epd->bInterval, 16);
2162 break;
2163 default:
2164 /* REVISIT we actually want to use NAK limits, hinting to the
2165 * transfer scheduling logic to try some other qh, e.g. try
2166 * for 2 msec first:
2167 *
2168 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2169 *
2170 * The downside of disabling this is that transfer scheduling
2171 * gets VERY unfair for nonperiodic transfers; a misbehaving
2172 * peripheral could make that hurt. That's perfectly normal
2173 * for reads from network or serial adapters ... so we have
2174 * partial NAKlimit support for bulk RX.
2175 *
2176 * The upside of disabling it is simpler transfer scheduling.
2177 */
2178 interval = 0;
2179 }
2180 qh->intv_reg = interval;
2181
2182 /* precompute addressing for external hub/tt ports */
2183 if (musb->is_multipoint) {
2184 struct usb_device *parent = urb->dev->parent;
2185
2186 if (parent != hcd->self.root_hub) {
2187 qh->h_addr_reg = (u8) parent->devnum;
2188
2189 /* set up tt info if needed */
2190 if (urb->dev->tt) {
2191 qh->h_port_reg = (u8) urb->dev->ttport;
2192 if (urb->dev->tt->hub)
2193 qh->h_addr_reg =
2194 (u8) urb->dev->tt->hub->devnum;
2195 if (urb->dev->tt->multi)
2196 qh->h_addr_reg |= 0x80;
2197 }
2198 }
2199 }
2200
2201 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2202 * until we get real dma queues (with an entry for each urb/buffer),
2203 * we only have work to do in the former case.
2204 */
2205 spin_lock_irqsave(&musb->lock, flags);
2206 if (hep->hcpriv || !next_urb(qh)) {
2207 /* some concurrent activity submitted another urb to hep...
2208 * odd, rare, error prone, but legal.
2209 */
2210 kfree(qh);
2211 qh = NULL;
2212 ret = 0;
2213 } else
2214 ret = musb_schedule(musb, qh,
2215 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2216
2217 if (ret == 0) {
2218 urb->hcpriv = qh;
2219 /* FIXME set urb->start_frame for iso/intr, it's tested in
2220 * musb_start_urb(), but otherwise only konicawc cares ...
2221 */
2222 }
2223 spin_unlock_irqrestore(&musb->lock, flags);
2224
2225 done:
2226 if (ret != 0) {
2227 spin_lock_irqsave(&musb->lock, flags);
2228 usb_hcd_unlink_urb_from_ep(hcd, urb);
2229 spin_unlock_irqrestore(&musb->lock, flags);
2230 kfree(qh);
2231 }
2232 return ret;
2233 }
2234
2235
2236 /*
2237 * abort a transfer that's at the head of a hardware queue.
2238 * called with controller locked, irqs blocked
2239 * that hardware queue advances to the next transfer, unless prevented
2240 */
2241 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2242 {
2243 struct musb_hw_ep *ep = qh->hw_ep;
2244 struct musb *musb = ep->musb;
2245 void __iomem *epio = ep->regs;
2246 unsigned hw_end = ep->epnum;
2247 void __iomem *regs = ep->musb->mregs;
2248 int is_in = usb_pipein(urb->pipe);
2249 int status = 0;
2250 u16 csr;
2251
2252 musb_ep_select(regs, hw_end);
2253
2254 if (is_dma_capable()) {
2255 struct dma_channel *dma;
2256
2257 dma = is_in ? ep->rx_channel : ep->tx_channel;
2258 if (dma) {
2259 status = ep->musb->dma_controller->channel_abort(dma);
2260 dev_dbg(musb->controller,
2261 "abort %cX%d DMA for urb %p --> %d\n",
2262 is_in ? 'R' : 'T', ep->epnum,
2263 urb, status);
2264 urb->actual_length += dma->actual_len;
2265 }
2266 }
2267
2268 /* turn off DMA requests, discard state, stop polling ... */
2269 if (ep->epnum && is_in) {
2270 /* giveback saves bulk toggle */
2271 csr = musb_h_flush_rxfifo(ep, 0);
2272
2273 /* REVISIT we still get an irq; should likely clear the
2274 * endpoint's irq status here to avoid bogus irqs.
2275 * clearing that status is platform-specific...
2276 */
2277 } else if (ep->epnum) {
2278 musb_h_tx_flush_fifo(ep);
2279 csr = musb_readw(epio, MUSB_TXCSR);
2280 csr &= ~(MUSB_TXCSR_AUTOSET
2281 | MUSB_TXCSR_DMAENAB
2282 | MUSB_TXCSR_H_RXSTALL
2283 | MUSB_TXCSR_H_NAKTIMEOUT
2284 | MUSB_TXCSR_H_ERROR
2285 | MUSB_TXCSR_TXPKTRDY);
2286 musb_writew(epio, MUSB_TXCSR, csr);
2287 /* REVISIT may need to clear FLUSHFIFO ... */
2288 musb_writew(epio, MUSB_TXCSR, csr);
2289 /* flush cpu writebuffer */
2290 csr = musb_readw(epio, MUSB_TXCSR);
2291 } else {
2292 musb_h_ep0_flush_fifo(ep);
2293 }
2294 if (status == 0)
2295 musb_advance_schedule(ep->musb, urb, ep, is_in);
2296 return status;
2297 }
2298
2299 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2300 {
2301 struct musb *musb = hcd_to_musb(hcd);
2302 struct musb_qh *qh;
2303 unsigned long flags;
2304 int is_in = usb_pipein(urb->pipe);
2305 int ret;
2306
2307 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2308 usb_pipedevice(urb->pipe),
2309 usb_pipeendpoint(urb->pipe),
2310 is_in ? "in" : "out");
2311
2312 spin_lock_irqsave(&musb->lock, flags);
2313 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2314 if (ret)
2315 goto done;
2316
2317 qh = urb->hcpriv;
2318 if (!qh)
2319 goto done;
2320
2321 /*
2322 * Any URB not actively programmed into endpoint hardware can be
2323 * immediately given back; that's any URB not at the head of an
2324 * endpoint queue, unless someday we get real DMA queues. And even
2325 * if it's at the head, it might not be known to the hardware...
2326 *
2327 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2328 * has already been updated. This is a synchronous abort; it'd be
2329 * OK to hold off until after some IRQ, though.
2330 *
2331 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2332 */
2333 if (!qh->is_ready
2334 || urb->urb_list.prev != &qh->hep->urb_list
2335 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2336 int ready = qh->is_ready;
2337
2338 qh->is_ready = 0;
2339 musb_giveback(musb, urb, 0);
2340 qh->is_ready = ready;
2341
2342 /* If nothing else (usually musb_giveback) is using it
2343 * and its URB list has emptied, recycle this qh.
2344 */
2345 if (ready && list_empty(&qh->hep->urb_list)) {
2346 qh->hep->hcpriv = NULL;
2347 list_del(&qh->ring);
2348 kfree(qh);
2349 }
2350 } else
2351 ret = musb_cleanup_urb(urb, qh);
2352 done:
2353 spin_unlock_irqrestore(&musb->lock, flags);
2354 return ret;
2355 }
2356
2357 /* disable an endpoint */
2358 static void
2359 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2360 {
2361 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2362 unsigned long flags;
2363 struct musb *musb = hcd_to_musb(hcd);
2364 struct musb_qh *qh;
2365 struct urb *urb;
2366
2367 spin_lock_irqsave(&musb->lock, flags);
2368
2369 qh = hep->hcpriv;
2370 if (qh == NULL)
2371 goto exit;
2372
2373 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2374
2375 /* Kick the first URB off the hardware, if needed */
2376 qh->is_ready = 0;
2377 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2378 urb = next_urb(qh);
2379
2380 /* make software (then hardware) stop ASAP */
2381 if (!urb->unlinked)
2382 urb->status = -ESHUTDOWN;
2383
2384 /* cleanup */
2385 musb_cleanup_urb(urb, qh);
2386
2387 /* Then nuke all the others ... and advance the
2388 * queue on hw_ep (e.g. bulk ring) when we're done.
2389 */
2390 while (!list_empty(&hep->urb_list)) {
2391 urb = next_urb(qh);
2392 urb->status = -ESHUTDOWN;
2393 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2394 }
2395 } else {
2396 /* Just empty the queue; the hardware is busy with
2397 * other transfers, and since !qh->is_ready nothing
2398 * will activate any of these as it advances.
2399 */
2400 while (!list_empty(&hep->urb_list))
2401 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2402
2403 hep->hcpriv = NULL;
2404 list_del(&qh->ring);
2405 kfree(qh);
2406 }
2407 exit:
2408 spin_unlock_irqrestore(&musb->lock, flags);
2409 }
2410
2411 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2412 {
2413 struct musb *musb = hcd_to_musb(hcd);
2414
2415 return musb_readw(musb->mregs, MUSB_FRAME);
2416 }
2417
2418 static int musb_h_start(struct usb_hcd *hcd)
2419 {
2420 struct musb *musb = hcd_to_musb(hcd);
2421
2422 /* NOTE: musb_start() is called when the hub driver turns
2423 * on port power, or when (OTG) peripheral starts.
2424 */
2425 hcd->state = HC_STATE_RUNNING;
2426 musb->port1_status = 0;
2427 return 0;
2428 }
2429
2430 static void musb_h_stop(struct usb_hcd *hcd)
2431 {
2432 musb_stop(hcd_to_musb(hcd));
2433 hcd->state = HC_STATE_HALT;
2434 }
2435
2436 static int musb_bus_suspend(struct usb_hcd *hcd)
2437 {
2438 struct musb *musb = hcd_to_musb(hcd);
2439 u8 devctl;
2440
2441 if (!is_host_active(musb))
2442 return 0;
2443
2444 switch (musb->xceiv->state) {
2445 case OTG_STATE_A_SUSPEND:
2446 return 0;
2447 case OTG_STATE_A_WAIT_VRISE:
2448 /* ID could be grounded even if there's no device
2449 * on the other end of the cable. NOTE that the
2450 * A_WAIT_VRISE timers are messy with MUSB...
2451 */
2452 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2453 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2454 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2455 break;
2456 default:
2457 break;
2458 }
2459
2460 if (musb->is_active) {
2461 WARNING("trying to suspend as %s while active\n",
2462 usb_otg_state_string(musb->xceiv->state));
2463 return -EBUSY;
2464 } else
2465 return 0;
2466 }
2467
2468 static int musb_bus_resume(struct usb_hcd *hcd)
2469 {
2470 /* resuming child port does the work */
2471 return 0;
2472 }
2473
2474 #ifndef CONFIG_MUSB_PIO_ONLY
2475
2476 #define MUSB_USB_DMA_ALIGN 4
2477
2478 struct musb_temp_buffer {
2479 void *kmalloc_ptr;
2480 void *old_xfer_buffer;
2481 u8 data[0];
2482 };
2483
2484 static void musb_free_temp_buffer(struct urb *urb)
2485 {
2486 enum dma_data_direction dir;
2487 struct musb_temp_buffer *temp;
2488
2489 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2490 return;
2491
2492 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2493
2494 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2495 data);
2496
2497 if (dir == DMA_FROM_DEVICE) {
2498 memcpy(temp->old_xfer_buffer, temp->data,
2499 urb->transfer_buffer_length);
2500 }
2501 urb->transfer_buffer = temp->old_xfer_buffer;
2502 kfree(temp->kmalloc_ptr);
2503
2504 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2505 }
2506
2507 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2508 {
2509 enum dma_data_direction dir;
2510 struct musb_temp_buffer *temp;
2511 void *kmalloc_ptr;
2512 size_t kmalloc_size;
2513
2514 if (urb->num_sgs || urb->sg ||
2515 urb->transfer_buffer_length == 0 ||
2516 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2517 return 0;
2518
2519 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2520
2521 /* Allocate a buffer with enough padding for alignment */
2522 kmalloc_size = urb->transfer_buffer_length +
2523 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2524
2525 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2526 if (!kmalloc_ptr)
2527 return -ENOMEM;
2528
2529 /* Position our struct temp_buffer such that data is aligned */
2530 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2531
2532
2533 temp->kmalloc_ptr = kmalloc_ptr;
2534 temp->old_xfer_buffer = urb->transfer_buffer;
2535 if (dir == DMA_TO_DEVICE)
2536 memcpy(temp->data, urb->transfer_buffer,
2537 urb->transfer_buffer_length);
2538 urb->transfer_buffer = temp->data;
2539
2540 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2541
2542 return 0;
2543 }
2544
2545 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2546 gfp_t mem_flags)
2547 {
2548 struct musb *musb = hcd_to_musb(hcd);
2549 int ret;
2550
2551 /*
2552 * The DMA engine in RTL1.8 and above cannot handle
2553 * DMA addresses that are not aligned to a 4 byte boundary.
2554 * For such engine implemented (un)map_urb_for_dma hooks.
2555 * Do not use these hooks for RTL<1.8
2556 */
2557 if (musb->hwvers < MUSB_HWVERS_1800)
2558 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2559
2560 ret = musb_alloc_temp_buffer(urb, mem_flags);
2561 if (ret)
2562 return ret;
2563
2564 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2565 if (ret)
2566 musb_free_temp_buffer(urb);
2567
2568 return ret;
2569 }
2570
2571 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2572 {
2573 struct musb *musb = hcd_to_musb(hcd);
2574
2575 usb_hcd_unmap_urb_for_dma(hcd, urb);
2576
2577 /* Do not use this hook for RTL<1.8 (see description above) */
2578 if (musb->hwvers < MUSB_HWVERS_1800)
2579 return;
2580
2581 musb_free_temp_buffer(urb);
2582 }
2583 #endif /* !CONFIG_MUSB_PIO_ONLY */
2584
2585 static const struct hc_driver musb_hc_driver = {
2586 .description = "musb-hcd",
2587 .product_desc = "MUSB HDRC host driver",
2588 .hcd_priv_size = sizeof(struct musb *),
2589 .flags = HCD_USB2 | HCD_MEMORY,
2590
2591 /* not using irq handler or reset hooks from usbcore, since
2592 * those must be shared with peripheral code for OTG configs
2593 */
2594
2595 .start = musb_h_start,
2596 .stop = musb_h_stop,
2597
2598 .get_frame_number = musb_h_get_frame_number,
2599
2600 .urb_enqueue = musb_urb_enqueue,
2601 .urb_dequeue = musb_urb_dequeue,
2602 .endpoint_disable = musb_h_disable,
2603
2604 #ifndef CONFIG_MUSB_PIO_ONLY
2605 .map_urb_for_dma = musb_map_urb_for_dma,
2606 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2607 #endif
2608
2609 .hub_status_data = musb_hub_status_data,
2610 .hub_control = musb_hub_control,
2611 .bus_suspend = musb_bus_suspend,
2612 .bus_resume = musb_bus_resume,
2613 /* .start_port_reset = NULL, */
2614 /* .hub_irq_enable = NULL, */
2615 };
2616
2617 int musb_host_alloc(struct musb *musb)
2618 {
2619 struct device *dev = musb->controller;
2620
2621 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2622 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2623 if (!musb->hcd)
2624 return -EINVAL;
2625
2626 *musb->hcd->hcd_priv = (unsigned long) musb;
2627 musb->hcd->self.uses_pio_for_control = 1;
2628 musb->hcd->uses_new_polling = 1;
2629 musb->hcd->has_tt = 1;
2630
2631 return 0;
2632 }
2633
2634 void musb_host_cleanup(struct musb *musb)
2635 {
2636 if (musb->port_mode == MUSB_PORT_MODE_GADGET)
2637 return;
2638 usb_remove_hcd(musb->hcd);
2639 }
2640
2641 void musb_host_free(struct musb *musb)
2642 {
2643 usb_put_hcd(musb->hcd);
2644 }
2645
2646 int musb_host_setup(struct musb *musb, int power_budget)
2647 {
2648 int ret;
2649 struct usb_hcd *hcd = musb->hcd;
2650
2651 MUSB_HST_MODE(musb);
2652 musb->xceiv->otg->default_a = 1;
2653 musb->xceiv->state = OTG_STATE_A_IDLE;
2654
2655 otg_set_host(musb->xceiv->otg, &hcd->self);
2656 hcd->self.otg_port = 1;
2657 musb->xceiv->otg->host = &hcd->self;
2658 hcd->power_budget = 2 * (power_budget ? : 250);
2659
2660 ret = usb_add_hcd(hcd, 0, 0);
2661 if (ret < 0)
2662 return ret;
2663
2664 return 0;
2665 }
2666
2667 void musb_host_resume_root_hub(struct musb *musb)
2668 {
2669 usb_hcd_resume_root_hub(musb->hcd);
2670 }
2671
2672 void musb_host_poke_root_hub(struct musb *musb)
2673 {
2674 MUSB_HST_MODE(musb);
2675 if (musb->hcd->status_urb)
2676 usb_hcd_poll_rh_status(musb->hcd);
2677 else
2678 usb_hcd_resume_root_hub(musb->hcd);
2679 }
Linux with added FPC-III support