drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #include <linux/interrupt.h>
  27
  28 #ifdef pr_fmt
  29 #undef pr_fmt
  30 #endif
  31
  32 #ifdef DSS_SUBSYS_NAME
  33 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
  34 #else
  35 #define pr_fmt(fmt) fmt
  36 #endif
  37
  38 #define DSSDBG(format, ...) \
  39         pr_debug(format, ## __VA_ARGS__)
  40
  41 #ifdef DSS_SUBSYS_NAME
  42 #define DSSERR(format, ...) \
  43         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  44         ## __VA_ARGS__)
  45 #else
  46 #define DSSERR(format, ...) \
  47         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  48 #endif
  49
  50 #ifdef DSS_SUBSYS_NAME
  51 #define DSSINFO(format, ...) \
  52         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  53         ## __VA_ARGS__)
  54 #else
  55 #define DSSINFO(format, ...) \
  56         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  57 #endif
  58
  59 #ifdef DSS_SUBSYS_NAME
  60 #define DSSWARN(format, ...) \
  61         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  62         ## __VA_ARGS__)
  63 #else
  64 #define DSSWARN(format, ...) \
  65         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  66 #endif
  67
  68 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  69    number. For example 7:0 */
  70 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  72 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  73 #define FLD_MOD(orig, val, start, end) \
  74         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  75
  76 enum dss_io_pad_mode {
  77         DSS_IO_PAD_MODE_RESET,
  78         DSS_IO_PAD_MODE_RFBI,
  79         DSS_IO_PAD_MODE_BYPASS,
  80 };
  81
  82 enum dss_hdmi_venc_clk_source_select {
  83         DSS_VENC_TV_CLK = 0,
  84         DSS_HDMI_M_PCLK = 1,
  85 };
  86
  87 enum dss_dsi_content_type {
  88         DSS_DSI_CONTENT_DCS,
  89         DSS_DSI_CONTENT_GENERIC,
  90 };
  91
  92 enum dss_writeback_channel {
  93         DSS_WB_LCD1_MGR =       0,
  94         DSS_WB_LCD2_MGR =       1,
  95         DSS_WB_TV_MGR =         2,
  96         DSS_WB_OVL0 =           3,
  97         DSS_WB_OVL1 =           4,
  98         DSS_WB_OVL2 =           5,
  99         DSS_WB_OVL3 =           6,
 100         DSS_WB_LCD3_MGR =       7,
 101 };
 102
 103 struct dss_clock_info {
 104         /* rates that we get with dividers below */
 105         unsigned long fck;
 106
 107         /* dividers */
 108         u16 fck_div;
 109 };
 110
 111 struct dispc_clock_info {
 112         /* rates that we get with dividers below */
 113         unsigned long lck;
 114         unsigned long pck;
 115
 116         /* dividers */
 117         u16 lck_div;
 118         u16 pck_div;
 119 };
 120
 121 struct dsi_clock_info {
 122         /* rates that we get with dividers below */
 123         unsigned long fint;
 124         unsigned long clkin4ddr;
 125         unsigned long clkin;
 126         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 127                                                  * OMAP4: PLLx_CLK1 */
 128         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 129                                                  * OMAP4: PLLx_CLK2 */
 130         unsigned long lp_clk;
 131
 132         /* dividers */
 133         u16 regn;
 134         u16 regm;
 135         u16 regm_dispc; /* OMAP3: REGM3
 136                          * OMAP4: REGM4 */
 137         u16 regm_dsi;   /* OMAP3: REGM4
 138                          * OMAP4: REGM5 */
 139         u16 lp_clk_div;
 140 };
 141
 142 struct reg_field {
 143         u16 reg;
 144         u8 high;
 145         u8 low;
 146 };
 147
 148 struct dss_lcd_mgr_config {
 149         enum dss_io_pad_mode io_pad_mode;
 150
 151         bool stallmode;
 152         bool fifohandcheck;
 153
 154         struct dispc_clock_info clock_info;
 155
 156         int video_port_width;
 157
 158         int lcden_sig_polarity;
 159 };
 160
 161 struct seq_file;
 162 struct platform_device;
 163
 164 /* core */
 165 struct platform_device *dss_get_core_pdev(void);
 166 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
 167 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
 168 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
 169 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
 170
 171 /* display */
 172 int dss_suspend_all_devices(void);
 173 int dss_resume_all_devices(void);
 174 void dss_disable_all_devices(void);
 175
 176 int display_init_sysfs(struct platform_device *pdev);
 177 void display_uninit_sysfs(struct platform_device *pdev);
 178
 179 /* manager */
 180 int dss_init_overlay_managers(void);
 181 void dss_uninit_overlay_managers(void);
 182 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
 183 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
 184 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
 185                 const struct omap_overlay_manager_info *info);
 186 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
 187                 const struct omap_video_timings *timings);
 188 int dss_mgr_check(struct omap_overlay_manager *mgr,
 189                 struct omap_overlay_manager_info *info,
 190                 const struct omap_video_timings *mgr_timings,
 191                 const struct dss_lcd_mgr_config *config,
 192                 struct omap_overlay_info **overlay_infos);
 193
 194 static inline bool dss_mgr_is_lcd(enum omap_channel id)
 195 {
 196         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
 197                         id == OMAP_DSS_CHANNEL_LCD3)
 198                 return true;
 199         else
 200                 return false;
 201 }
 202
 203 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
 204                 struct platform_device *pdev);
 205 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
 206
 207 /* overlay */
 208 void dss_init_overlays(struct platform_device *pdev);
 209 void dss_uninit_overlays(struct platform_device *pdev);
 210 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 211 int dss_ovl_simple_check(struct omap_overlay *ovl,
 212                 const struct omap_overlay_info *info);
 213 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
 214                 const struct omap_video_timings *mgr_timings);
 215 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
 216                 enum omap_color_mode mode);
 217 int dss_overlay_kobj_init(struct omap_overlay *ovl,
 218                 struct platform_device *pdev);
 219 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
 220
 221 /* DSS */
 222 int dss_init_platform_driver(void) __init;
 223 void dss_uninit_platform_driver(void);
 224
 225 unsigned long dss_get_dispc_clk_rate(void);
 226 int dss_dpi_select_source(enum omap_channel channel);
 227 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 228 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 229 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 230 void dss_dump_clocks(struct seq_file *s);
 231
 232 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 233 void dss_debug_dump_clocks(struct seq_file *s);
 234 #endif
 235
 236 int dss_get_ctx_loss_count(void);
 237
 238 void dss_sdi_init(int datapairs);
 239 int dss_sdi_enable(void);
 240 void dss_sdi_disable(void);
 241
 242 void dss_select_dsi_clk_source(int dsi_module,
 243                 enum omap_dss_clk_source clk_src);
 244 void dss_select_lcd_clk_source(enum omap_channel channel,
 245                 enum omap_dss_clk_source clk_src);
 246 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 247 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 248 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 249
 250 void dss_set_venc_output(enum omap_dss_venc_type type);
 251 void dss_set_dac_pwrdn_bgz(bool enable);
 252
 253 unsigned long dss_get_dpll4_rate(void);
 254 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 255 int dss_set_clock_div(struct dss_clock_info *cinfo);
 256
 257 typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data);
 258 bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data);
 259
 260 /* SDI */
 261 int sdi_init_platform_driver(void) __init;
 262 void sdi_uninit_platform_driver(void) __exit;
 263
 264 /* DSI */
 265
 266 typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
 267                 unsigned long pll, void *data);
 268 typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
 269                 void *data);
 270
 271 #ifdef CONFIG_OMAP2_DSS_DSI
 272
 273 struct dentry;
 274 struct file_operations;
 275
 276 int dsi_init_platform_driver(void) __init;
 277 void dsi_uninit_platform_driver(void) __exit;
 278
 279 int dsi_runtime_get(struct platform_device *dsidev);
 280 void dsi_runtime_put(struct platform_device *dsidev);
 281
 282 void dsi_dump_clocks(struct seq_file *s);
 283
 284 void dsi_irq_handler(void);
 285 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 286
 287 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
 288
 289 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
 290                 unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
 291 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
 292                 unsigned long pll_min, unsigned long pll_max,
 293                 dsi_pll_calc_func func, void *data);
 294
 295 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 296 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 297                 struct dsi_clock_info *cinfo);
 298 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 299                 bool enable_hsdiv);
 300 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 301 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 302 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 303 struct platform_device *dsi_get_dsidev_from_id(int module);
 304 #else
 305 static inline int dsi_runtime_get(struct platform_device *dsidev)
 306 {
 307         return 0;
 308 }
 309 static inline void dsi_runtime_put(struct platform_device *dsidev)
 310 {
 311 }
 312 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 313 {
 314         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 315         return 0;
 316 }
 317 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 318 {
 319         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 320         return 0;
 321 }
 322 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 323                 struct dsi_clock_info *cinfo)
 324 {
 325         WARN("%s: DSI not compiled in\n", __func__);
 326         return -ENODEV;
 327 }
 328 static inline int dsi_pll_init(struct platform_device *dsidev,
 329                 bool enable_hsclk, bool enable_hsdiv)
 330 {
 331         WARN("%s: DSI not compiled in\n", __func__);
 332         return -ENODEV;
 333 }
 334 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 335                 bool disconnect_lanes)
 336 {
 337 }
 338 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 339 {
 340 }
 341 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 342 {
 343 }
 344 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 345 {
 346         return NULL;
 347 }
 348
 349 static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
 350 {
 351         return 0;
 352 }
 353
 354 static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
 355                 unsigned long pll, unsigned long out_min,
 356                 dsi_hsdiv_calc_func func, void *data)
 357 {
 358         return false;
 359 }
 360
 361 static inline bool dsi_pll_calc(struct platform_device *dsidev,
 362                 unsigned long clkin,
 363                 unsigned long pll_min, unsigned long pll_max,
 364                 dsi_pll_calc_func func, void *data)
 365 {
 366         return false;
 367 }
 368
 369 #endif
 370
 371 /* DPI */
 372 int dpi_init_platform_driver(void) __init;
 373 void dpi_uninit_platform_driver(void) __exit;
 374
 375 /* DISPC */
 376 int dispc_init_platform_driver(void) __init;
 377 void dispc_uninit_platform_driver(void) __exit;
 378 void dispc_dump_clocks(struct seq_file *s);
 379
 380 void dispc_enable_sidle(void);
 381 void dispc_disable_sidle(void);
 382
 383 void dispc_lcd_enable_signal(bool enable);
 384 void dispc_pck_free_enable(bool enable);
 385 void dispc_enable_fifomerge(bool enable);
 386 void dispc_enable_gamma_table(bool enable);
 387 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 388
 389 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
 390                 unsigned long pck, void *data);
 391 bool dispc_div_calc(unsigned long dispc,
 392                 unsigned long pck_min, unsigned long pck_max,
 393                 dispc_div_calc_func func, void *data);
 394
 395 bool dispc_mgr_timings_ok(enum omap_channel channel,
 396                 const struct omap_video_timings *timings);
 397 unsigned long dispc_fclk_rate(void);
 398 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 399                 struct dispc_clock_info *cinfo);
 400
 401
 402 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 403 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 404                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 405                 bool manual_update);
 406
 407 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 408 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 409 unsigned long dispc_core_clk_rate(void);
 410 void dispc_mgr_set_clock_div(enum omap_channel channel,
 411                 const struct dispc_clock_info *cinfo);
 412 int dispc_mgr_get_clock_div(enum omap_channel channel,
 413                 struct dispc_clock_info *cinfo);
 414 void dispc_set_tv_pclk(unsigned long pclk);
 415
 416 u32 dispc_wb_get_framedone_irq(void);
 417 bool dispc_wb_go_busy(void);
 418 void dispc_wb_go(void);
 419 void dispc_wb_enable(bool enable);
 420 bool dispc_wb_is_enabled(void);
 421 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
 422 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 423                 bool mem_to_mem, const struct omap_video_timings *timings);
 424
 425 /* VENC */
 426 int venc_init_platform_driver(void) __init;
 427 void venc_uninit_platform_driver(void) __exit;
 428
 429 /* HDMI */
 430 int hdmi_init_platform_driver(void) __init;
 431 void hdmi_uninit_platform_driver(void) __exit;
 432
 433 /* RFBI */
 434 int rfbi_init_platform_driver(void) __init;
 435 void rfbi_uninit_platform_driver(void) __exit;
 436
 437
 438 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 439 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 440 {
 441         int b;
 442         for (b = 0; b < 32; ++b) {
 443                 if (irqstatus & (1 << b))
 444                         irq_arr[b]++;
 445         }
 446 }
 447 #endif
 448
 449 #endif