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mfd: wm8350-i2c: Make sure the i2c regmap functions are compiled
[linux/fpc-iii.git] / drivers / video / omap2 / dss / ti_hdmi_4xxx_ip.c
blob3dfe00956a4f156b8c0261c03186efda84187c87
1 /*
2 * ti_hdmi_4xxx_ip.c
3 *
4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/err.h>
25 #include <linux/io.h>
26 #include <linux/interrupt.h>
27 #include <linux/mutex.h>
28 #include <linux/delay.h>
29 #include <linux/string.h>
30 #include <linux/seq_file.h>
31 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
32 #include <sound/asound.h>
33 #include <sound/asoundef.h>
34 #endif
35
36 #include "ti_hdmi_4xxx_ip.h"
37 #include "dss.h"
38 #include "dss_features.h"
39
40 #define HDMI_IRQ_LINK_CONNECT (1 << 25)
41 #define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
42
43 static inline void hdmi_write_reg(void __iomem *base_addr,
44 const u16 idx, u32 val)
45 {
46 __raw_writel(val, base_addr + idx);
47 }
48
49 static inline u32 hdmi_read_reg(void __iomem *base_addr,
50 const u16 idx)
51 {
52 return __raw_readl(base_addr + idx);
53 }
54
55 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
56 {
57 return ip_data->base_wp;
58 }
59
60 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
61 {
62 return ip_data->base_wp + ip_data->phy_offset;
63 }
64
65 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
66 {
67 return ip_data->base_wp + ip_data->pll_offset;
68 }
69
70 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
71 {
72 return ip_data->base_wp + ip_data->core_av_offset;
73 }
74
75 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
76 {
77 return ip_data->base_wp + ip_data->core_sys_offset;
78 }
79
80 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
81 const u16 idx,
82 int b2, int b1, u32 val)
83 {
84 u32 t = 0;
85 while (val != REG_GET(base_addr, idx, b2, b1)) {
86 udelay(1);
87 if (t++ > 10000)
88 return !val;
89 }
90 return val;
91 }
92
93 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
94 {
95 u32 r;
96 void __iomem *pll_base = hdmi_pll_base(ip_data);
97 struct hdmi_pll_info *fmt = &ip_data->pll_data;
98
99 /* PLL start always use manual mode */
100 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
101
102 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
103 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
104 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
105
106 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
107
108 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
109
110 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
111 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
112 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
113 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
114
115 if (fmt->dcofreq) {
116 /* divider programming for frequency beyond 1000Mhz */
117 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
118 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
119 } else {
120 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
121 }
122
123 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
124
125 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
126 r = FLD_MOD(r, fmt->regm2, 24, 18);
127 r = FLD_MOD(r, fmt->regmf, 17, 0);
128
129 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
130
131 /* go now */
132 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
133
134 /* wait for bit change */
135 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
136 0, 0, 1) != 1) {
137 pr_err("PLL GO bit not set\n");
138 return -ETIMEDOUT;
139 }
140
141 /* Wait till the lock bit is set in PLL status */
142 if (hdmi_wait_for_bit_change(pll_base,
143 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
144 pr_err("cannot lock PLL\n");
145 pr_err("CFG1 0x%x\n",
146 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
147 pr_err("CFG2 0x%x\n",
148 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
149 pr_err("CFG4 0x%x\n",
150 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
151 return -ETIMEDOUT;
152 }
153
154 pr_debug("PLL locked!\n");
155
156 return 0;
157 }
158
159 /* PHY_PWR_CMD */
160 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
161 {
162 /* Return if already the state */
163 if (REG_GET(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, 5, 4) == val)
164 return 0;
165
166 /* Command for power control of HDMI PHY */
167 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
168
169 /* Status of the power control of HDMI PHY */
170 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
171 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
172 pr_err("Failed to set PHY power mode to %d\n", val);
173 return -ETIMEDOUT;
174 }
175
176 return 0;
177 }
178
179 /* PLL_PWR_CMD */
180 static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
181 {
182 /* Command for power control of HDMI PLL */
183 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
184
185 /* wait till PHY_PWR_STATUS is set */
186 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
187 1, 0, val) != val) {
188 pr_err("Failed to set PLL_PWR_STATUS\n");
189 return -ETIMEDOUT;
190 }
191
192 return 0;
193 }
194
195 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
196 {
197 /* SYSRESET controlled by power FSM */
198 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
199
200 /* READ 0x0 reset is in progress */
201 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
202 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
203 pr_err("Failed to sysreset PLL\n");
204 return -ETIMEDOUT;
205 }
206
207 return 0;
208 }
209
210 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
211 {
212 u16 r = 0;
213
214 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
215 if (r)
216 return r;
217
218 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
219 if (r)
220 return r;
221
222 r = hdmi_pll_reset(ip_data);
223 if (r)
224 return r;
225
226 r = hdmi_pll_init(ip_data);
227 if (r)
228 return r;
229
230 return 0;
231 }
232
233 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
234 {
235 hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
236 }
237
238 static irqreturn_t hdmi_irq_handler(int irq, void *data)
239 {
240 struct hdmi_ip_data *ip_data = data;
241 void __iomem *wp_base = hdmi_wp_base(ip_data);
242 u32 irqstatus;
243
244 irqstatus = hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS);
245 hdmi_write_reg(wp_base, HDMI_WP_IRQSTATUS, irqstatus);
246 /* flush posted write */
247 hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS);
248
249 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
250 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
251 /*
252 * If we get both connect and disconnect interrupts at the same
253 * time, turn off the PHY, clear interrupts, and restart, which
254 * raises connect interrupt if a cable is connected, or nothing
255 * if cable is not connected.
256 */
257 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
258
259 hdmi_write_reg(wp_base, HDMI_WP_IRQSTATUS,
260 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
261 /* flush posted write */
262 hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS);
263
264 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
265 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
266 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
267 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
268 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
269 }
270
271 return IRQ_HANDLED;
272 }
273
274 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
275 {
276 u16 r = 0;
277 void __iomem *phy_base = hdmi_phy_base(ip_data);
278
279 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQENABLE_CLR,
280 0xffffffff);
281
282 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQSTATUS,
283 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
284
285 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
286 if (r)
287 return r;
288
289 /*
290 * Read address 0 in order to get the SCP reset done completed
291 * Dummy access performed to make sure reset is done
292 */
293 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
294
295 /*
296 * Write to phy address 0 to configure the clock
297 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
298 */
299 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
300
301 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
302 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
303
304 /* Setup max LDO voltage */
305 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
306
307 /* Write to phy address 3 to change the polarity control */
308 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
309
310 r = request_threaded_irq(ip_data->irq, NULL, hdmi_irq_handler,
311 IRQF_ONESHOT, "OMAP HDMI", ip_data);
312 if (r) {
313 DSSERR("HDMI IRQ request failed\n");
314 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
315 return r;
316 }
317
318 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQENABLE_SET,
319 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
320
321 return 0;
322 }
323
324 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
325 {
326 free_irq(ip_data->irq, ip_data);
327
328 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
329 }
330
331 static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
332 {
333 void __iomem *base = hdmi_core_sys_base(ip_data);
334
335 /* Turn on CLK for DDC */
336 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
337
338 /* IN_PROG */
339 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
340 /* Abort transaction */
341 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
342 /* IN_PROG */
343 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
344 4, 4, 0) != 0) {
345 DSSERR("Timeout aborting DDC transaction\n");
346 return -ETIMEDOUT;
347 }
348 }
349
350 /* Clk SCL Devices */
351 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
352
353 /* HDMI_CORE_DDC_STATUS_IN_PROG */
354 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
355 4, 4, 0) != 0) {
356 DSSERR("Timeout starting SCL clock\n");
357 return -ETIMEDOUT;
358 }
359
360 /* Clear FIFO */
361 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
362
363 /* HDMI_CORE_DDC_STATUS_IN_PROG */
364 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
365 4, 4, 0) != 0) {
366 DSSERR("Timeout clearing DDC fifo\n");
367 return -ETIMEDOUT;
368 }
369
370 return 0;
371 }
372
373 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
374 u8 *pedid, int ext)
375 {
376 void __iomem *base = hdmi_core_sys_base(ip_data);
377 u32 i;
378 char checksum;
379 u32 offset = 0;
380
381 /* HDMI_CORE_DDC_STATUS_IN_PROG */
382 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
383 4, 4, 0) != 0) {
384 DSSERR("Timeout waiting DDC to be ready\n");
385 return -ETIMEDOUT;
386 }
387
388 if (ext % 2 != 0)
389 offset = 0x80;
390
391 /* Load Segment Address Register */
392 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
393
394 /* Load Slave Address Register */
395 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
396
397 /* Load Offset Address Register */
398 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
399
400 /* Load Byte Count */
401 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
402 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
403
404 /* Set DDC_CMD */
405 if (ext)
406 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
407 else
408 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
409
410 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
411 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
412 pr_err("I2C Bus Low?\n");
413 return -EIO;
414 }
415 /* HDMI_CORE_DDC_STATUS_NO_ACK */
416 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
417 pr_err("I2C No Ack\n");
418 return -EIO;
419 }
420
421 for (i = 0; i < 0x80; ++i) {
422 int t;
423
424 /* IN_PROG */
425 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
426 DSSERR("operation stopped when reading edid\n");
427 return -EIO;
428 }
429
430 t = 0;
431 /* FIFO_EMPTY */
432 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
433 if (t++ > 10000) {
434 DSSERR("timeout reading edid\n");
435 return -ETIMEDOUT;
436 }
437 udelay(1);
438 }
439
440 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
441 }
442
443 checksum = 0;
444 for (i = 0; i < 0x80; ++i)
445 checksum += pedid[i];
446
447 if (checksum != 0) {
448 pr_err("E-EDID checksum failed!!\n");
449 return -EIO;
450 }
451
452 return 0;
453 }
454
455 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
456 u8 *edid, int len)
457 {
458 int r, l;
459
460 if (len < 128)
461 return -EINVAL;
462
463 r = hdmi_core_ddc_init(ip_data);
464 if (r)
465 return r;
466
467 r = hdmi_core_ddc_edid(ip_data, edid, 0);
468 if (r)
469 return r;
470
471 l = 128;
472
473 if (len >= 128 * 2 && edid[0x7e] > 0) {
474 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
475 if (r)
476 return r;
477 l += 128;
478 }
479
480 return l;
481 }
482
483 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
484 struct hdmi_core_infoframe_avi *avi_cfg,
485 struct hdmi_core_packet_enable_repeat *repeat_cfg)
486 {
487 pr_debug("Enter hdmi_core_init\n");
488
489 /* video core */
490 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
491 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
492 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
493 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
494 video_cfg->hdmi_dvi = HDMI_DVI;
495 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
496
497 /* info frame */
498 avi_cfg->db1_format = 0;
499 avi_cfg->db1_active_info = 0;
500 avi_cfg->db1_bar_info_dv = 0;
501 avi_cfg->db1_scan_info = 0;
502 avi_cfg->db2_colorimetry = 0;
503 avi_cfg->db2_aspect_ratio = 0;
504 avi_cfg->db2_active_fmt_ar = 0;
505 avi_cfg->db3_itc = 0;
506 avi_cfg->db3_ec = 0;
507 avi_cfg->db3_q_range = 0;
508 avi_cfg->db3_nup_scaling = 0;
509 avi_cfg->db4_videocode = 0;
510 avi_cfg->db5_pixel_repeat = 0;
511 avi_cfg->db6_7_line_eoftop = 0 ;
512 avi_cfg->db8_9_line_sofbottom = 0;
513 avi_cfg->db10_11_pixel_eofleft = 0;
514 avi_cfg->db12_13_pixel_sofright = 0;
515
516 /* packet enable and repeat */
517 repeat_cfg->audio_pkt = 0;
518 repeat_cfg->audio_pkt_repeat = 0;
519 repeat_cfg->avi_infoframe = 0;
520 repeat_cfg->avi_infoframe_repeat = 0;
521 repeat_cfg->gen_cntrl_pkt = 0;
522 repeat_cfg->gen_cntrl_pkt_repeat = 0;
523 repeat_cfg->generic_pkt = 0;
524 repeat_cfg->generic_pkt_repeat = 0;
525 }
526
527 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
528 {
529 pr_debug("Enter hdmi_core_powerdown_disable\n");
530 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
531 }
532
533 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
534 {
535 pr_debug("Enter hdmi_core_swreset_release\n");
536 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
537 }
538
539 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
540 {
541 pr_debug("Enter hdmi_core_swreset_assert\n");
542 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
543 }
544
545 /* HDMI_CORE_VIDEO_CONFIG */
546 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
547 struct hdmi_core_video_config *cfg)
548 {
549 u32 r = 0;
550 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
551
552 /* sys_ctrl1 default configuration not tunable */
553 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
554 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
555 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
556 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
557 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
558 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
559
560 REG_FLD_MOD(core_sys_base,
561 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
562
563 /* Vid_Mode */
564 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
565
566 /* dither truncation configuration */
567 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
568 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
569 r = FLD_MOD(r, 1, 5, 5);
570 } else {
571 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
572 r = FLD_MOD(r, 0, 5, 5);
573 }
574 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
575
576 /* HDMI_Ctrl */
577 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
578 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
579 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
580 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
581 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
582
583 /* TMDS_CTRL */
584 REG_FLD_MOD(core_sys_base,
585 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
586 }
587
588 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
589 {
590 u32 val;
591 char sum = 0, checksum = 0;
592 void __iomem *av_base = hdmi_av_base(ip_data);
593 struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg;
594
595 sum += 0x82 + 0x002 + 0x00D;
596 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
597 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
598 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
599
600 val = (info_avi.db1_format << 5) |
601 (info_avi.db1_active_info << 4) |
602 (info_avi.db1_bar_info_dv << 2) |
603 (info_avi.db1_scan_info);
604 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
605 sum += val;
606
607 val = (info_avi.db2_colorimetry << 6) |
608 (info_avi.db2_aspect_ratio << 4) |
609 (info_avi.db2_active_fmt_ar);
610 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
611 sum += val;
612
613 val = (info_avi.db3_itc << 7) |
614 (info_avi.db3_ec << 4) |
615 (info_avi.db3_q_range << 2) |
616 (info_avi.db3_nup_scaling);
617 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
618 sum += val;
619
620 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
621 info_avi.db4_videocode);
622 sum += info_avi.db4_videocode;
623
624 val = info_avi.db5_pixel_repeat;
625 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
626 sum += val;
627
628 val = info_avi.db6_7_line_eoftop & 0x00FF;
629 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
630 sum += val;
631
632 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
633 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
634 sum += val;
635
636 val = info_avi.db8_9_line_sofbottom & 0x00FF;
637 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
638 sum += val;
639
640 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
641 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
642 sum += val;
643
644 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
645 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
646 sum += val;
647
648 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
649 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
650 sum += val;
651
652 val = info_avi.db12_13_pixel_sofright & 0x00FF;
653 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
654 sum += val;
655
656 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
657 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
658 sum += val;
659
660 checksum = 0x100 - sum;
661 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
662 }
663
664 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
665 struct hdmi_core_packet_enable_repeat repeat_cfg)
666 {
667 /* enable/repeat the infoframe */
668 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
669 (repeat_cfg.audio_pkt << 5) |
670 (repeat_cfg.audio_pkt_repeat << 4) |
671 (repeat_cfg.avi_infoframe << 1) |
672 (repeat_cfg.avi_infoframe_repeat));
673
674 /* enable/repeat the packet */
675 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
676 (repeat_cfg.gen_cntrl_pkt << 3) |
677 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
678 (repeat_cfg.generic_pkt << 1) |
679 (repeat_cfg.generic_pkt_repeat));
680 }
681
682 static void hdmi_wp_init(struct omap_video_timings *timings,
683 struct hdmi_video_format *video_fmt)
684 {
685 pr_debug("Enter hdmi_wp_init\n");
686
687 timings->hbp = 0;
688 timings->hfp = 0;
689 timings->hsw = 0;
690 timings->vbp = 0;
691 timings->vfp = 0;
692 timings->vsw = 0;
693
694 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
695 video_fmt->y_res = 0;
696 video_fmt->x_res = 0;
697
698 }
699
700 int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data)
701 {
702 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, true, 31, 31);
703 return 0;
704 }
705
706 void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data)
707 {
708 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, false, 31, 31);
709 }
710
711 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
712 struct omap_video_timings *timings, struct hdmi_config *param)
713 {
714 pr_debug("Enter hdmi_wp_video_init_format\n");
715
716 video_fmt->y_res = param->timings.y_res;
717 video_fmt->x_res = param->timings.x_res;
718
719 timings->hbp = param->timings.hbp;
720 timings->hfp = param->timings.hfp;
721 timings->hsw = param->timings.hsw;
722 timings->vbp = param->timings.vbp;
723 timings->vfp = param->timings.vfp;
724 timings->vsw = param->timings.vsw;
725 }
726
727 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
728 struct hdmi_video_format *video_fmt)
729 {
730 u32 l = 0;
731
732 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
733 video_fmt->packing_mode, 10, 8);
734
735 l |= FLD_VAL(video_fmt->y_res, 31, 16);
736 l |= FLD_VAL(video_fmt->x_res, 15, 0);
737 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
738 }
739
740 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
741 {
742 u32 r;
743 bool vsync_pol, hsync_pol;
744 pr_debug("Enter hdmi_wp_video_config_interface\n");
745
746 vsync_pol = ip_data->cfg.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
747 hsync_pol = ip_data->cfg.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
748
749 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
750 r = FLD_MOD(r, vsync_pol, 7, 7);
751 r = FLD_MOD(r, hsync_pol, 6, 6);
752 r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
753 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
754 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
755 }
756
757 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
758 struct omap_video_timings *timings)
759 {
760 u32 timing_h = 0;
761 u32 timing_v = 0;
762
763 pr_debug("Enter hdmi_wp_video_config_timing\n");
764
765 timing_h |= FLD_VAL(timings->hbp, 31, 20);
766 timing_h |= FLD_VAL(timings->hfp, 19, 8);
767 timing_h |= FLD_VAL(timings->hsw, 7, 0);
768 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
769
770 timing_v |= FLD_VAL(timings->vbp, 31, 20);
771 timing_v |= FLD_VAL(timings->vfp, 19, 8);
772 timing_v |= FLD_VAL(timings->vsw, 7, 0);
773 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
774 }
775
776 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
777 {
778 /* HDMI */
779 struct omap_video_timings video_timing;
780 struct hdmi_video_format video_format;
781 /* HDMI core */
782 struct hdmi_core_infoframe_avi *avi_cfg = &ip_data->avi_cfg;
783 struct hdmi_core_video_config v_core_cfg;
784 struct hdmi_core_packet_enable_repeat repeat_cfg;
785 struct hdmi_config *cfg = &ip_data->cfg;
786
787 hdmi_wp_init(&video_timing, &video_format);
788
789 hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg);
790
791 hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
792
793 hdmi_wp_video_config_timing(ip_data, &video_timing);
794
795 /* video config */
796 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
797
798 hdmi_wp_video_config_format(ip_data, &video_format);
799
800 hdmi_wp_video_config_interface(ip_data);
801
802 /*
803 * configure core video part
804 * set software reset in the core
805 */
806 hdmi_core_swreset_assert(ip_data);
807
808 /* power down off */
809 hdmi_core_powerdown_disable(ip_data);
810
811 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
812 v_core_cfg.hdmi_dvi = cfg->cm.mode;
813
814 hdmi_core_video_config(ip_data, &v_core_cfg);
815
816 /* release software reset in the core */
817 hdmi_core_swreset_release(ip_data);
818
819 /*
820 * configure packet
821 * info frame video see doc CEA861-D page 65
822 */
823 avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
824 avi_cfg->db1_active_info =
825 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
826 avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
827 avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
828 avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
829 avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
830 avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
831 avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
832 avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
833 avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
834 avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
835 avi_cfg->db4_videocode = cfg->cm.code;
836 avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
837 avi_cfg->db6_7_line_eoftop = 0;
838 avi_cfg->db8_9_line_sofbottom = 0;
839 avi_cfg->db10_11_pixel_eofleft = 0;
840 avi_cfg->db12_13_pixel_sofright = 0;
841
842 hdmi_core_aux_infoframe_avi_config(ip_data);
843
844 /* enable/repeat the infoframe */
845 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
846 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
847 /* wakeup */
848 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
849 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
850 hdmi_core_av_packet_config(ip_data, repeat_cfg);
851 }
852
853 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
854 {
855 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
856 hdmi_read_reg(hdmi_wp_base(ip_data), r))
857
858 DUMPREG(HDMI_WP_REVISION);
859 DUMPREG(HDMI_WP_SYSCONFIG);
860 DUMPREG(HDMI_WP_IRQSTATUS_RAW);
861 DUMPREG(HDMI_WP_IRQSTATUS);
862 DUMPREG(HDMI_WP_PWR_CTRL);
863 DUMPREG(HDMI_WP_IRQENABLE_SET);
864 DUMPREG(HDMI_WP_VIDEO_CFG);
865 DUMPREG(HDMI_WP_VIDEO_SIZE);
866 DUMPREG(HDMI_WP_VIDEO_TIMING_H);
867 DUMPREG(HDMI_WP_VIDEO_TIMING_V);
868 DUMPREG(HDMI_WP_WP_CLK);
869 DUMPREG(HDMI_WP_AUDIO_CFG);
870 DUMPREG(HDMI_WP_AUDIO_CFG2);
871 DUMPREG(HDMI_WP_AUDIO_CTRL);
872 DUMPREG(HDMI_WP_AUDIO_DATA);
873 }
874
875 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
876 {
877 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
878 hdmi_read_reg(hdmi_pll_base(ip_data), r))
879
880 DUMPPLL(PLLCTRL_PLL_CONTROL);
881 DUMPPLL(PLLCTRL_PLL_STATUS);
882 DUMPPLL(PLLCTRL_PLL_GO);
883 DUMPPLL(PLLCTRL_CFG1);
884 DUMPPLL(PLLCTRL_CFG2);
885 DUMPPLL(PLLCTRL_CFG3);
886 DUMPPLL(PLLCTRL_CFG4);
887 }
888
889 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
890 {
891 int i;
892
893 #define CORE_REG(i, name) name(i)
894 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
895 hdmi_read_reg(hdmi_core_sys_base(ip_data), r))
896 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
897 hdmi_read_reg(hdmi_av_base(ip_data), r))
898 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
899 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
900 hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r)))
901
902 DUMPCORE(HDMI_CORE_SYS_VND_IDL);
903 DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
904 DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
905 DUMPCORE(HDMI_CORE_SYS_DEV_REV);
906 DUMPCORE(HDMI_CORE_SYS_SRST);
907 DUMPCORE(HDMI_CORE_CTRL1);
908 DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
909 DUMPCORE(HDMI_CORE_SYS_DE_DLY);
910 DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
911 DUMPCORE(HDMI_CORE_SYS_DE_TOP);
912 DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
913 DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
914 DUMPCORE(HDMI_CORE_SYS_DE_LINL);
915 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
916 DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
917 DUMPCORE(HDMI_CORE_SYS_VID_MODE);
918 DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
919 DUMPCORE(HDMI_CORE_SYS_INTR1);
920 DUMPCORE(HDMI_CORE_SYS_INTR2);
921 DUMPCORE(HDMI_CORE_SYS_INTR3);
922 DUMPCORE(HDMI_CORE_SYS_INTR4);
923 DUMPCORE(HDMI_CORE_SYS_UMASK1);
924 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
925
926 DUMPCORE(HDMI_CORE_DDC_ADDR);
927 DUMPCORE(HDMI_CORE_DDC_SEGM);
928 DUMPCORE(HDMI_CORE_DDC_OFFSET);
929 DUMPCORE(HDMI_CORE_DDC_COUNT1);
930 DUMPCORE(HDMI_CORE_DDC_COUNT2);
931 DUMPCORE(HDMI_CORE_DDC_STATUS);
932 DUMPCORE(HDMI_CORE_DDC_CMD);
933 DUMPCORE(HDMI_CORE_DDC_DATA);
934
935 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
936 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
937 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
938 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
939 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
940 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
941 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
942 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
943 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
944 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
945 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
946 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
947 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
948 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
949 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
950 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
951 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
952 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
953 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
954 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
955 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
956 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
957 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
958 DUMPCOREAV(HDMI_CORE_AV_ASRC);
959 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
960 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
961 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
962 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
963 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
964 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
965 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
966 DUMPCOREAV(HDMI_CORE_AV_DPD);
967 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
968 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
969 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
970 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
971 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
972 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
973
974 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
975 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
976
977 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
978 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
979 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
980 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
981
982 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
983 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
984
985 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
986 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
987 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
988 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
989
990 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
991 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
992
993 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
994 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
995 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
996 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
997
998 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
999 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
1000
1001 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
1002 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
1003
1004 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
1005
1006 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
1007 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
1008
1009 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
1010 }
1011
1012 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
1013 {
1014 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
1015 hdmi_read_reg(hdmi_phy_base(ip_data), r))
1016
1017 DUMPPHY(HDMI_TXPHY_TX_CTRL);
1018 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
1019 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
1020 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
1021 }
1022
1023 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
1024 static void ti_hdmi_4xxx_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1025 struct hdmi_audio_format *aud_fmt)
1026 {
1027 u32 r;
1028
1029 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1030
1031 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1032 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1033 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1034 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1035 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1036 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1037 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1038 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1039 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1040 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1041 }
1042
1043 static void ti_hdmi_4xxx_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1044 struct hdmi_audio_dma *aud_dma)
1045 {
1046 u32 r;
1047
1048 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1049
1050 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1051 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1052 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1053 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1054
1055 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1056 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1057 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1058 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1059 }
1060
1061 static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data,
1062 struct hdmi_core_audio_config *cfg)
1063 {
1064 u32 r;
1065 void __iomem *av_base = hdmi_av_base(ip_data);
1066
1067 /*
1068 * Parameters for generation of Audio Clock Recovery packets
1069 */
1070 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1071 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1072 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1073
1074 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1075 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1076 REG_FLD_MOD(av_base,
1077 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1078 REG_FLD_MOD(av_base,
1079 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1080 } else {
1081 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1082 cfg->aud_par_busclk, 7, 0);
1083 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1084 (cfg->aud_par_busclk >> 8), 7, 0);
1085 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1086 (cfg->aud_par_busclk >> 16), 7, 0);
1087 }
1088
1089 /* Set ACR clock divisor */
1090 REG_FLD_MOD(av_base,
1091 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1092
1093 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1094 /*
1095 * Use TMDS clock for ACR packets. For devices that use
1096 * the MCLK, this is the first part of the MCLK initialization.
1097 */
1098 r = FLD_MOD(r, 0, 2, 2);
1099
1100 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1101 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1102 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1103
1104 /* For devices using MCLK, this completes its initialization. */
1105 if (cfg->use_mclk)
1106 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
1107
1108 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1109 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1110 cfg->fs_override, 1, 1);
1111
1112 /*
1113 * Set IEC-60958-3 channel status word. It is passed to the IP
1114 * just as it is received. The user of the driver is responsible
1115 * for its contents.
1116 */
1117 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
1118 cfg->iec60958_cfg->status[0]);
1119 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
1120 cfg->iec60958_cfg->status[1]);
1121 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
1122 cfg->iec60958_cfg->status[2]);
1123 /* yes, this is correct: status[3] goes to CHST4 register */
1124 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
1125 cfg->iec60958_cfg->status[3]);
1126 /* yes, this is correct: status[4] goes to CHST5 register */
1127 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
1128 cfg->iec60958_cfg->status[4]);
1129
1130 /* set I2S parameters */
1131 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1132 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1133 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1134 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1135 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1136 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1137 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1138
1139 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1140 cfg->i2s_cfg.in_length_bits, 3, 0);
1141
1142 /* Audio channels and mode parameters */
1143 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1144 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1145 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1146 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1147 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1148 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1149 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1150
1151 /* Audio channel mappings */
1152 /* TODO: Make channel mapping dynamic. For now, map channels
1153 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
1154 * HDMI speaker order is different. See CEA-861 Section 6.6.2.
1155 */
1156 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
1157 REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
1158 }
1159
1160 static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data,
1161 struct snd_cea_861_aud_if *info_aud)
1162 {
1163 u8 sum = 0, checksum = 0;
1164 void __iomem *av_base = hdmi_av_base(ip_data);
1165
1166 /*
1167 * Set audio info frame type, version and length as
1168 * described in HDMI 1.4a Section 8.2.2 specification.
1169 * Checksum calculation is defined in Section 5.3.5.
1170 */
1171 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1172 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1173 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1174 sum += 0x84 + 0x001 + 0x00a;
1175
1176 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
1177 info_aud->db1_ct_cc);
1178 sum += info_aud->db1_ct_cc;
1179
1180 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
1181 info_aud->db2_sf_ss);
1182 sum += info_aud->db2_sf_ss;
1183
1184 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
1185 sum += info_aud->db3;
1186
1187 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
1188 sum += info_aud->db4_ca;
1189
1190 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
1191 info_aud->db5_dminh_lsv);
1192 sum += info_aud->db5_dminh_lsv;
1193
1194 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1195 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1196 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1197 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1198 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1199
1200 checksum = 0x100 - sum;
1201 hdmi_write_reg(av_base,
1202 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1203
1204 /*
1205 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1206 * is available.
1207 */
1208 }
1209
1210 int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
1211 struct omap_dss_audio *audio)
1212 {
1213 struct hdmi_audio_format audio_format;
1214 struct hdmi_audio_dma audio_dma;
1215 struct hdmi_core_audio_config core;
1216 int err, n, cts, channel_count;
1217 unsigned int fs_nr;
1218 bool word_length_16b = false;
1219
1220 if (!audio || !audio->iec || !audio->cea || !ip_data)
1221 return -EINVAL;
1222
1223 core.iec60958_cfg = audio->iec;
1224 /*
1225 * In the IEC-60958 status word, check if the audio sample word length
1226 * is 16-bit as several optimizations can be performed in such case.
1227 */
1228 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
1229 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
1230 word_length_16b = true;
1231
1232 /* I2S configuration. See Phillips' specification */
1233 if (word_length_16b)
1234 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1235 else
1236 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1237 /*
1238 * The I2S input word length is twice the lenght given in the IEC-60958
1239 * status word. If the word size is greater than
1240 * 20 bits, increment by one.
1241 */
1242 core.i2s_cfg.in_length_bits = audio->iec->status[4]
1243 & IEC958_AES4_CON_WORDLEN;
1244 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
1245 core.i2s_cfg.in_length_bits++;
1246 core.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
1247 core.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
1248 core.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
1249 core.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
1250
1251 /* convert sample frequency to a number */
1252 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
1253 case IEC958_AES3_CON_FS_32000:
1254 fs_nr = 32000;
1255 break;
1256 case IEC958_AES3_CON_FS_44100:
1257 fs_nr = 44100;
1258 break;
1259 case IEC958_AES3_CON_FS_48000:
1260 fs_nr = 48000;
1261 break;
1262 case IEC958_AES3_CON_FS_88200:
1263 fs_nr = 88200;
1264 break;
1265 case IEC958_AES3_CON_FS_96000:
1266 fs_nr = 96000;
1267 break;
1268 case IEC958_AES3_CON_FS_176400:
1269 fs_nr = 176400;
1270 break;
1271 case IEC958_AES3_CON_FS_192000:
1272 fs_nr = 192000;
1273 break;
1274 default:
1275 return -EINVAL;
1276 }
1277
1278 err = hdmi_compute_acr(fs_nr, &n, &cts);
1279
1280 /* Audio clock regeneration settings */
1281 core.n = n;
1282 core.cts = cts;
1283 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
1284 core.aud_par_busclk = 0;
1285 core.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
1286 core.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
1287 } else {
1288 core.aud_par_busclk = (((128 * 31) - 1) << 8);
1289 core.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
1290 core.use_mclk = true;
1291 }
1292
1293 if (core.use_mclk)
1294 core.mclk_mode = HDMI_AUDIO_MCLK_128FS;
1295
1296 /* Audio channels settings */
1297 channel_count = (audio->cea->db1_ct_cc &
1298 CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
1299
1300 switch (channel_count) {
1301 case 2:
1302 audio_format.active_chnnls_msk = 0x03;
1303 break;
1304 case 3:
1305 audio_format.active_chnnls_msk = 0x07;
1306 break;
1307 case 4:
1308 audio_format.active_chnnls_msk = 0x0f;
1309 break;
1310 case 5:
1311 audio_format.active_chnnls_msk = 0x1f;
1312 break;
1313 case 6:
1314 audio_format.active_chnnls_msk = 0x3f;
1315 break;
1316 case 7:
1317 audio_format.active_chnnls_msk = 0x7f;
1318 break;
1319 case 8:
1320 audio_format.active_chnnls_msk = 0xff;
1321 break;
1322 default:
1323 return -EINVAL;
1324 }
1325
1326 /*
1327 * the HDMI IP needs to enable four stereo channels when transmitting
1328 * more than 2 audio channels
1329 */
1330 if (channel_count == 2) {
1331 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
1332 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
1333 core.layout = HDMI_AUDIO_LAYOUT_2CH;
1334 } else {
1335 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
1336 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
1337 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
1338 HDMI_AUDIO_I2S_SD3_EN;
1339 core.layout = HDMI_AUDIO_LAYOUT_8CH;
1340 }
1341
1342 core.en_spdif = false;
1343 /* use sample frequency from channel status word */
1344 core.fs_override = true;
1345 /* enable ACR packets */
1346 core.en_acr_pkt = true;
1347 /* disable direct streaming digital audio */
1348 core.en_dsd_audio = false;
1349 /* use parallel audio interface */
1350 core.en_parallel_aud_input = true;
1351
1352 /* DMA settings */
1353 if (word_length_16b)
1354 audio_dma.transfer_size = 0x10;
1355 else
1356 audio_dma.transfer_size = 0x20;
1357 audio_dma.block_size = 0xC0;
1358 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1359 audio_dma.fifo_threshold = 0x20; /* in number of samples */
1360
1361 /* audio FIFO format settings */
1362 if (word_length_16b) {
1363 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
1364 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
1365 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1366 } else {
1367 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
1368 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
1369 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1370 }
1371 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
1372 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
1373 /* disable start/stop signals of IEC 60958 blocks */
1374 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
1375
1376 /* configure DMA and audio FIFO format*/
1377 ti_hdmi_4xxx_wp_audio_config_dma(ip_data, &audio_dma);
1378 ti_hdmi_4xxx_wp_audio_config_format(ip_data, &audio_format);
1379
1380 /* configure the core*/
1381 ti_hdmi_4xxx_core_audio_config(ip_data, &core);
1382
1383 /* configure CEA 861 audio infoframe*/
1384 ti_hdmi_4xxx_core_audio_infoframe_cfg(ip_data, audio->cea);
1385
1386 return 0;
1387 }
1388
1389 int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data)
1390 {
1391 REG_FLD_MOD(hdmi_wp_base(ip_data),
1392 HDMI_WP_AUDIO_CTRL, true, 31, 31);
1393 return 0;
1394 }
1395
1396 void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data)
1397 {
1398 REG_FLD_MOD(hdmi_wp_base(ip_data),
1399 HDMI_WP_AUDIO_CTRL, false, 31, 31);
1400 }
1401
1402 int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data)
1403 {
1404 REG_FLD_MOD(hdmi_av_base(ip_data),
1405 HDMI_CORE_AV_AUD_MODE, true, 0, 0);
1406 REG_FLD_MOD(hdmi_wp_base(ip_data),
1407 HDMI_WP_AUDIO_CTRL, true, 30, 30);
1408 return 0;
1409 }
1410
1411 void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data)
1412 {
1413 REG_FLD_MOD(hdmi_av_base(ip_data),
1414 HDMI_CORE_AV_AUD_MODE, false, 0, 0);
1415 REG_FLD_MOD(hdmi_wp_base(ip_data),
1416 HDMI_WP_AUDIO_CTRL, false, 30, 30);
1417 }
1418
1419 int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size)
1420 {
1421 if (!offset || !size)
1422 return -EINVAL;
1423 *offset = HDMI_WP_AUDIO_DATA;
1424 *size = 4;
1425 return 0;
1426 }
1427 #endif
Linux with added FPC-III support