include/media/omap3isp.h

   1 /*
   2  * omap3isp.h
   3  *
   4  * TI OMAP3 ISP - Platform data
   5  *
   6  * Copyright (C) 2011 Nokia Corporation
   7  *
   8  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   9  *           Sakari Ailus <sakari.ailus@iki.fi>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23  * 02110-1301 USA
  24  */
  25
  26 #ifndef __MEDIA_OMAP3ISP_H__
  27 #define __MEDIA_OMAP3ISP_H__
  28
  29 struct i2c_board_info;
  30 struct isp_device;
  31
  32 enum isp_interface_type {
  33         ISP_INTERFACE_PARALLEL,
  34         ISP_INTERFACE_CSI2A_PHY2,
  35         ISP_INTERFACE_CCP2B_PHY1,
  36         ISP_INTERFACE_CCP2B_PHY2,
  37         ISP_INTERFACE_CSI2C_PHY1,
  38 };
  39
  40 enum {
  41         ISP_LANE_SHIFT_0 = 0,
  42         ISP_LANE_SHIFT_2 = 1,
  43         ISP_LANE_SHIFT_4 = 2,
  44         ISP_LANE_SHIFT_6 = 3,
  45 };
  46
  47 /**
  48  * struct isp_parallel_platform_data - Parallel interface platform data
  49  * @data_lane_shift: Data lane shifter
  50  *              ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
  51  *              ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
  52  *              ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
  53  *              ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
  54  * @clk_pol: Pixel clock polarity
  55  *              0 - Sample on rising edge, 1 - Sample on falling edge
  56  * @hs_pol: Horizontal synchronization polarity
  57  *              0 - Active high, 1 - Active low
  58  * @vs_pol: Vertical synchronization polarity
  59  *              0 - Active high, 1 - Active low
  60  * @data_pol: Data polarity
  61  *              0 - Normal, 1 - One's complement
  62  */
  63 struct isp_parallel_platform_data {
  64         unsigned int data_lane_shift:2;
  65         unsigned int clk_pol:1;
  66         unsigned int hs_pol:1;
  67         unsigned int vs_pol:1;
  68         unsigned int data_pol:1;
  69 };
  70
  71 enum {
  72         ISP_CCP2_PHY_DATA_CLOCK = 0,
  73         ISP_CCP2_PHY_DATA_STROBE = 1,
  74 };
  75
  76 enum {
  77         ISP_CCP2_MODE_MIPI = 0,
  78         ISP_CCP2_MODE_CCP2 = 1,
  79 };
  80
  81 /**
  82  * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
  83  * @pos: position of the lane
  84  * @pol: polarity of the lane
  85  */
  86 struct isp_csiphy_lane {
  87         u8 pos;
  88         u8 pol;
  89 };
  90
  91 #define ISP_CSIPHY1_NUM_DATA_LANES      1
  92 #define ISP_CSIPHY2_NUM_DATA_LANES      2
  93
  94 /**
  95  * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
  96  * @data: Configuration of one or two data lanes
  97  * @clk: Clock lane configuration
  98  */
  99 struct isp_csiphy_lanes_cfg {
 100         struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
 101         struct isp_csiphy_lane clk;
 102 };
 103
 104 /**
 105  * struct isp_ccp2_platform_data - CCP2 interface platform data
 106  * @strobe_clk_pol: Strobe/clock polarity
 107  *              0 - Non Inverted, 1 - Inverted
 108  * @crc: Enable the cyclic redundancy check
 109  * @ccp2_mode: Enable CCP2 compatibility mode
 110  *              ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
 111  *              ISP_CCP2_MODE_CCP2 - CCP2 mode
 112  * @phy_layer: Physical layer selection
 113  *              ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
 114  *              ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
 115  * @vpclk_div: Video port output clock control
 116  */
 117 struct isp_ccp2_platform_data {
 118         unsigned int strobe_clk_pol:1;
 119         unsigned int crc:1;
 120         unsigned int ccp2_mode:1;
 121         unsigned int phy_layer:1;
 122         unsigned int vpclk_div:2;
 123         struct isp_csiphy_lanes_cfg lanecfg;
 124 };
 125
 126 /**
 127  * struct isp_csi2_platform_data - CSI2 interface platform data
 128  * @crc: Enable the cyclic redundancy check
 129  * @vpclk_div: Video port output clock control
 130  */
 131 struct isp_csi2_platform_data {
 132         unsigned crc:1;
 133         unsigned vpclk_div:2;
 134         struct isp_csiphy_lanes_cfg lanecfg;
 135 };
 136
 137 struct isp_subdev_i2c_board_info {
 138         struct i2c_board_info *board_info;
 139         int i2c_adapter_id;
 140 };
 141
 142 struct isp_v4l2_subdevs_group {
 143         struct isp_subdev_i2c_board_info *subdevs;
 144         enum isp_interface_type interface;
 145         union {
 146                 struct isp_parallel_platform_data parallel;
 147                 struct isp_ccp2_platform_data ccp2;
 148                 struct isp_csi2_platform_data csi2;
 149         } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
 150 };
 151
 152 struct isp_platform_xclk {
 153         const char *dev_id;
 154         const char *con_id;
 155 };
 156
 157 struct isp_platform_data {
 158         struct isp_platform_xclk xclks[2];
 159         struct isp_v4l2_subdevs_group *subdevs;
 160         void (*set_constraints)(struct isp_device *isp, bool enable);
 161 };
 162
 163 #endif  /* __MEDIA_OMAP3ISP_H__ */