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ath9k_hw: rename ath9k_hw_rf_free() to ath9k_hw_rf_free_ext_banks()
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / hw.c
blob4c3ff2e429e7149baed772e940ebc2314dda5546
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value);
33 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
34 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35
36 MODULE_AUTHOR("Atheros Communications");
37 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
38 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
39 MODULE_LICENSE("Dual BSD/GPL");
40
41 static int __init ath9k_init(void)
42 {
43 return 0;
44 }
45 module_init(ath9k_init);
46
47 static void __exit ath9k_exit(void)
48 {
49 return;
50 }
51 module_exit(ath9k_exit);
52
53 /********************/
54 /* Helper Functions */
55 /********************/
56
57 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
58 {
59 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
60
61 if (!ah->curchan) /* should really check for CCK instead */
62 return clks / ATH9K_CLOCK_RATE_CCK;
63 if (conf->channel->band == IEEE80211_BAND_2GHZ)
64 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
65
66 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
67 }
68
69 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
70 {
71 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
72
73 if (conf_is_ht40(conf))
74 return ath9k_hw_mac_usec(ah, clks) / 2;
75 else
76 return ath9k_hw_mac_usec(ah, clks);
77 }
78
79 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
80 {
81 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
82
83 if (!ah->curchan) /* should really check for CCK instead */
84 return usecs *ATH9K_CLOCK_RATE_CCK;
85 if (conf->channel->band == IEEE80211_BAND_2GHZ)
86 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
87 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
88 }
89
90 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
91 {
92 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
93
94 if (conf_is_ht40(conf))
95 return ath9k_hw_mac_clks(ah, usecs) * 2;
96 else
97 return ath9k_hw_mac_clks(ah, usecs);
98 }
99
100 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
101 {
102 int i;
103
104 BUG_ON(timeout < AH_TIME_QUANTUM);
105
106 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
107 if ((REG_READ(ah, reg) & mask) == val)
108 return true;
109
110 udelay(AH_TIME_QUANTUM);
111 }
112
113 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
114 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
115 timeout, reg, REG_READ(ah, reg), mask, val);
116
117 return false;
118 }
119 EXPORT_SYMBOL(ath9k_hw_wait);
120
121 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
122 {
123 u32 retval;
124 int i;
125
126 for (i = 0, retval = 0; i < n; i++) {
127 retval = (retval << 1) | (val & 1);
128 val >>= 1;
129 }
130 return retval;
131 }
132
133 bool ath9k_get_channel_edges(struct ath_hw *ah,
134 u16 flags, u16 *low,
135 u16 *high)
136 {
137 struct ath9k_hw_capabilities *pCap = &ah->caps;
138
139 if (flags & CHANNEL_5GHZ) {
140 *low = pCap->low_5ghz_chan;
141 *high = pCap->high_5ghz_chan;
142 return true;
143 }
144 if ((flags & CHANNEL_2GHZ)) {
145 *low = pCap->low_2ghz_chan;
146 *high = pCap->high_2ghz_chan;
147 return true;
148 }
149 return false;
150 }
151
152 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
153 const struct ath_rate_table *rates,
154 u32 frameLen, u16 rateix,
155 bool shortPreamble)
156 {
157 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
158 u32 kbps;
159
160 kbps = rates->info[rateix].ratekbps;
161
162 if (kbps == 0)
163 return 0;
164
165 switch (rates->info[rateix].phy) {
166 case WLAN_RC_PHY_CCK:
167 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
168 if (shortPreamble && rates->info[rateix].short_preamble)
169 phyTime >>= 1;
170 numBits = frameLen << 3;
171 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
172 break;
173 case WLAN_RC_PHY_OFDM:
174 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
175 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
176 numBits = OFDM_PLCP_BITS + (frameLen << 3);
177 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
178 txTime = OFDM_SIFS_TIME_QUARTER
179 + OFDM_PREAMBLE_TIME_QUARTER
180 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
181 } else if (ah->curchan &&
182 IS_CHAN_HALF_RATE(ah->curchan)) {
183 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
184 numBits = OFDM_PLCP_BITS + (frameLen << 3);
185 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
186 txTime = OFDM_SIFS_TIME_HALF +
187 OFDM_PREAMBLE_TIME_HALF
188 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
189 } else {
190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
194 + (numSymbols * OFDM_SYMBOL_TIME);
195 }
196 break;
197 default:
198 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
199 "Unknown phy %u (rate ix %u)\n",
200 rates->info[rateix].phy, rateix);
201 txTime = 0;
202 break;
203 }
204
205 return txTime;
206 }
207 EXPORT_SYMBOL(ath9k_hw_computetxtime);
208
209 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
210 struct ath9k_channel *chan,
211 struct chan_centers *centers)
212 {
213 int8_t extoff;
214
215 if (!IS_CHAN_HT40(chan)) {
216 centers->ctl_center = centers->ext_center =
217 centers->synth_center = chan->channel;
218 return;
219 }
220
221 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
222 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
223 centers->synth_center =
224 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
225 extoff = 1;
226 } else {
227 centers->synth_center =
228 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
229 extoff = -1;
230 }
231
232 centers->ctl_center =
233 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
234 /* 25 MHz spacing is supported by hw but not on upper layers */
235 centers->ext_center =
236 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 }
238
239 /******************/
240 /* Chip Revisions */
241 /******************/
242
243 static void ath9k_hw_read_revisions(struct ath_hw *ah)
244 {
245 u32 val;
246
247 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
248
249 if (val == 0xFF) {
250 val = REG_READ(ah, AR_SREV);
251 ah->hw_version.macVersion =
252 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
253 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
254 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
255 } else {
256 if (!AR_SREV_9100(ah))
257 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
258
259 ah->hw_version.macRev = val & AR_SREV_REVISION;
260
261 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
262 ah->is_pciexpress = true;
263 }
264 }
265
266 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
267 {
268 u32 val;
269 int i;
270
271 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
272
273 for (i = 0; i < 8; i++)
274 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
275 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
276 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
277
278 return ath9k_hw_reverse_bits(val, 8);
279 }
280
281 /************************************/
282 /* HW Attach, Detach, Init Routines */
283 /************************************/
284
285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
286 {
287 if (AR_SREV_9100(ah))
288 return;
289
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
299
300 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
301 }
302
303 static bool ath9k_hw_chip_test(struct ath_hw *ah)
304 {
305 struct ath_common *common = ath9k_hw_common(ah);
306 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
307 u32 regHold[2];
308 u32 patternData[4] = { 0x55555555,
309 0xaaaaaaaa,
310 0x66666666,
311 0x99999999 };
312 int i, j;
313
314 for (i = 0; i < 2; i++) {
315 u32 addr = regAddr[i];
316 u32 wrData, rdData;
317
318 regHold[i] = REG_READ(ah, addr);
319 for (j = 0; j < 0x100; j++) {
320 wrData = (j << 16) | j;
321 REG_WRITE(ah, addr, wrData);
322 rdData = REG_READ(ah, addr);
323 if (rdData != wrData) {
324 ath_print(common, ATH_DBG_FATAL,
325 "address test failed "
326 "addr: 0x%08x - wr:0x%08x != "
327 "rd:0x%08x\n",
328 addr, wrData, rdData);
329 return false;
330 }
331 }
332 for (j = 0; j < 4; j++) {
333 wrData = patternData[j];
334 REG_WRITE(ah, addr, wrData);
335 rdData = REG_READ(ah, addr);
336 if (wrData != rdData) {
337 ath_print(common, ATH_DBG_FATAL,
338 "address test failed "
339 "addr: 0x%08x - wr:0x%08x != "
340 "rd:0x%08x\n",
341 addr, wrData, rdData);
342 return false;
343 }
344 }
345 REG_WRITE(ah, regAddr[i], regHold[i]);
346 }
347 udelay(100);
348
349 return true;
350 }
351
352 static const char *ath9k_hw_devname(u16 devid)
353 {
354 switch (devid) {
355 case AR5416_DEVID_PCI:
356 return "Atheros 5416";
357 case AR5416_DEVID_PCIE:
358 return "Atheros 5418";
359 case AR9160_DEVID_PCI:
360 return "Atheros 9160";
361 case AR5416_AR9100_DEVID:
362 return "Atheros 9100";
363 case AR9280_DEVID_PCI:
364 case AR9280_DEVID_PCIE:
365 return "Atheros 9280";
366 case AR9285_DEVID_PCIE:
367 return "Atheros 9285";
368 case AR5416_DEVID_AR9287_PCI:
369 case AR5416_DEVID_AR9287_PCIE:
370 return "Atheros 9287";
371 }
372
373 return NULL;
374 }
375
376 static void ath9k_hw_init_config(struct ath_hw *ah)
377 {
378 int i;
379
380 ah->config.dma_beacon_response_time = 2;
381 ah->config.sw_beacon_response_time = 10;
382 ah->config.additional_swba_backoff = 0;
383 ah->config.ack_6mb = 0x0;
384 ah->config.cwm_ignore_extcca = 0;
385 ah->config.pcie_powersave_enable = 0;
386 ah->config.pcie_clock_req = 0;
387 ah->config.pcie_waen = 0;
388 ah->config.analog_shiftreg = 1;
389 ah->config.ht_enable = 1;
390 ah->config.ofdm_trig_low = 200;
391 ah->config.ofdm_trig_high = 500;
392 ah->config.cck_trig_high = 200;
393 ah->config.cck_trig_low = 100;
394 ah->config.enable_ani = 1;
395 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
396 ah->config.antenna_switch_swap = 0;
397
398 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
399 ah->config.spurchans[i][0] = AR_NO_SPUR;
400 ah->config.spurchans[i][1] = AR_NO_SPUR;
401 }
402
403 ah->config.intr_mitigation = true;
404
405 /*
406 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
408 * This means we use it for all AR5416 devices, and the few
409 * minor PCI AR9280 devices out there.
410 *
411 * Serialization is required because these devices do not handle
412 * well the case of two concurrent reads/writes due to the latency
413 * involved. During one read/write another read/write can be issued
414 * on another CPU while the previous read/write may still be working
415 * on our hardware, if we hit this case the hardware poops in a loop.
416 * We prevent this by serializing reads and writes.
417 *
418 * This issue is not present on PCI-Express devices or pre-AR5416
419 * devices (legacy, 802.11abg).
420 */
421 if (num_possible_cpus() > 1)
422 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
423 }
424 EXPORT_SYMBOL(ath9k_hw_init);
425
426 static void ath9k_hw_init_defaults(struct ath_hw *ah)
427 {
428 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
429
430 regulatory->country_code = CTRY_DEFAULT;
431 regulatory->power_limit = MAX_RATE_POWER;
432 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
433
434 ah->hw_version.magic = AR5416_MAGIC;
435 ah->hw_version.subvendorid = 0;
436
437 ah->ah_flags = 0;
438 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
439 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
440 if (!AR_SREV_9100(ah))
441 ah->ah_flags = AH_USE_EEPROM;
442
443 ah->atim_window = 0;
444 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
445 ah->beacon_interval = 100;
446 ah->enable_32kHz_clock = DONT_USE_32KHZ;
447 ah->slottime = (u32) -1;
448 ah->acktimeout = (u32) -1;
449 ah->ctstimeout = (u32) -1;
450 ah->globaltxtimeout = (u32) -1;
451
452 ah->gbeacon_rate = 0;
453
454 ah->power_mode = ATH9K_PM_UNDEFINED;
455 }
456
457 static int ath9k_hw_rf_claim(struct ath_hw *ah)
458 {
459 u32 val;
460
461 REG_WRITE(ah, AR_PHY(0), 0x00000007);
462
463 val = ath9k_hw_get_radiorev(ah);
464 switch (val & AR_RADIO_SREV_MAJOR) {
465 case 0:
466 val = AR_RAD5133_SREV_MAJOR;
467 break;
468 case AR_RAD5133_SREV_MAJOR:
469 case AR_RAD5122_SREV_MAJOR:
470 case AR_RAD2133_SREV_MAJOR:
471 case AR_RAD2122_SREV_MAJOR:
472 break;
473 default:
474 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
475 "Radio Chip Rev 0x%02X not supported\n",
476 val & AR_RADIO_SREV_MAJOR);
477 return -EOPNOTSUPP;
478 }
479
480 ah->hw_version.analog5GhzRev = val;
481
482 return 0;
483 }
484
485 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
486 {
487 struct ath_common *common = ath9k_hw_common(ah);
488 u32 sum;
489 int i;
490 u16 eeval;
491
492 sum = 0;
493 for (i = 0; i < 3; i++) {
494 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
495 sum += eeval;
496 common->macaddr[2 * i] = eeval >> 8;
497 common->macaddr[2 * i + 1] = eeval & 0xff;
498 }
499 if (sum == 0 || sum == 0xffff * 3)
500 return -EADDRNOTAVAIL;
501
502 return 0;
503 }
504
505 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
506 {
507 u32 rxgain_type;
508
509 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
510 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
511
512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
513 INIT_INI_ARRAY(&ah->iniModesRxGain,
514 ar9280Modes_backoff_13db_rxgain_9280_2,
515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
517 INIT_INI_ARRAY(&ah->iniModesRxGain,
518 ar9280Modes_backoff_23db_rxgain_9280_2,
519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
520 else
521 INIT_INI_ARRAY(&ah->iniModesRxGain,
522 ar9280Modes_original_rxgain_9280_2,
523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
524 } else {
525 INIT_INI_ARRAY(&ah->iniModesRxGain,
526 ar9280Modes_original_rxgain_9280_2,
527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
528 }
529 }
530
531 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
532 {
533 u32 txgain_type;
534
535 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
536 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
537
538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
539 INIT_INI_ARRAY(&ah->iniModesTxGain,
540 ar9280Modes_high_power_tx_gain_9280_2,
541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
542 else
543 INIT_INI_ARRAY(&ah->iniModesTxGain,
544 ar9280Modes_original_tx_gain_9280_2,
545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
546 } else {
547 INIT_INI_ARRAY(&ah->iniModesTxGain,
548 ar9280Modes_original_tx_gain_9280_2,
549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
550 }
551 }
552
553 static int ath9k_hw_post_init(struct ath_hw *ah)
554 {
555 int ecode;
556
557 if (!ath9k_hw_chip_test(ah))
558 return -ENODEV;
559
560 ecode = ath9k_hw_rf_claim(ah);
561 if (ecode != 0)
562 return ecode;
563
564 ecode = ath9k_hw_eeprom_init(ah);
565 if (ecode != 0)
566 return ecode;
567
568 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
569 "Eeprom VER: %d, REV: %d\n",
570 ah->eep_ops->get_eeprom_ver(ah),
571 ah->eep_ops->get_eeprom_rev(ah));
572
573 if (!AR_SREV_9280_10_OR_LATER(ah)) {
574 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
575 if (ecode) {
576 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
577 "Failed allocating banks for "
578 "external radio\n");
579 return ecode;
580 }
581 }
582
583 if (!AR_SREV_9100(ah)) {
584 ath9k_hw_ani_setup(ah);
585 ath9k_hw_ani_init(ah);
586 }
587
588 return 0;
589 }
590
591 static bool ath9k_hw_devid_supported(u16 devid)
592 {
593 switch (devid) {
594 case AR5416_DEVID_PCI:
595 case AR5416_DEVID_PCIE:
596 case AR5416_AR9100_DEVID:
597 case AR9160_DEVID_PCI:
598 case AR9280_DEVID_PCI:
599 case AR9280_DEVID_PCIE:
600 case AR9285_DEVID_PCIE:
601 case AR5416_DEVID_AR9287_PCI:
602 case AR5416_DEVID_AR9287_PCIE:
603 case AR9271_USB:
604 return true;
605 default:
606 break;
607 }
608 return false;
609 }
610
611 static bool ath9k_hw_macversion_supported(u32 macversion)
612 {
613 switch (macversion) {
614 case AR_SREV_VERSION_5416_PCI:
615 case AR_SREV_VERSION_5416_PCIE:
616 case AR_SREV_VERSION_9160:
617 case AR_SREV_VERSION_9100:
618 case AR_SREV_VERSION_9280:
619 case AR_SREV_VERSION_9285:
620 case AR_SREV_VERSION_9287:
621 case AR_SREV_VERSION_9271:
622 return true;
623 default:
624 break;
625 }
626 return false;
627 }
628
629 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
630 {
631 if (AR_SREV_9160_10_OR_LATER(ah)) {
632 if (AR_SREV_9280_10_OR_LATER(ah)) {
633 ah->iq_caldata.calData = &iq_cal_single_sample;
634 ah->adcgain_caldata.calData =
635 &adc_gain_cal_single_sample;
636 ah->adcdc_caldata.calData =
637 &adc_dc_cal_single_sample;
638 ah->adcdc_calinitdata.calData =
639 &adc_init_dc_cal;
640 } else {
641 ah->iq_caldata.calData = &iq_cal_multi_sample;
642 ah->adcgain_caldata.calData =
643 &adc_gain_cal_multi_sample;
644 ah->adcdc_caldata.calData =
645 &adc_dc_cal_multi_sample;
646 ah->adcdc_calinitdata.calData =
647 &adc_init_dc_cal;
648 }
649 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
650 }
651 }
652
653 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
654 {
655 if (AR_SREV_9271(ah)) {
656 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
657 ARRAY_SIZE(ar9271Modes_9271), 6);
658 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
659 ARRAY_SIZE(ar9271Common_9271), 2);
660 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
661 ar9271Modes_9271_1_0_only,
662 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
663 return;
664 }
665
666 if (AR_SREV_9287_11_OR_LATER(ah)) {
667 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
668 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
669 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
670 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
671 if (ah->config.pcie_clock_req)
672 INIT_INI_ARRAY(&ah->iniPcieSerdes,
673 ar9287PciePhy_clkreq_off_L1_9287_1_1,
674 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
675 else
676 INIT_INI_ARRAY(&ah->iniPcieSerdes,
677 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
678 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
679 2);
680 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
681 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
682 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
683 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
684 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
685
686 if (ah->config.pcie_clock_req)
687 INIT_INI_ARRAY(&ah->iniPcieSerdes,
688 ar9287PciePhy_clkreq_off_L1_9287_1_0,
689 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
690 else
691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
692 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
693 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
694 2);
695 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
696
697
698 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
699 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
700 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
701 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
702
703 if (ah->config.pcie_clock_req) {
704 INIT_INI_ARRAY(&ah->iniPcieSerdes,
705 ar9285PciePhy_clkreq_off_L1_9285_1_2,
706 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
707 } else {
708 INIT_INI_ARRAY(&ah->iniPcieSerdes,
709 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
710 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
711 2);
712 }
713 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
714 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
715 ARRAY_SIZE(ar9285Modes_9285), 6);
716 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
717 ARRAY_SIZE(ar9285Common_9285), 2);
718
719 if (ah->config.pcie_clock_req) {
720 INIT_INI_ARRAY(&ah->iniPcieSerdes,
721 ar9285PciePhy_clkreq_off_L1_9285,
722 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
723 } else {
724 INIT_INI_ARRAY(&ah->iniPcieSerdes,
725 ar9285PciePhy_clkreq_always_on_L1_9285,
726 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
727 }
728 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
729 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
730 ARRAY_SIZE(ar9280Modes_9280_2), 6);
731 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
732 ARRAY_SIZE(ar9280Common_9280_2), 2);
733
734 if (ah->config.pcie_clock_req) {
735 INIT_INI_ARRAY(&ah->iniPcieSerdes,
736 ar9280PciePhy_clkreq_off_L1_9280,
737 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
738 } else {
739 INIT_INI_ARRAY(&ah->iniPcieSerdes,
740 ar9280PciePhy_clkreq_always_on_L1_9280,
741 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
742 }
743 INIT_INI_ARRAY(&ah->iniModesAdditional,
744 ar9280Modes_fast_clock_9280_2,
745 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
746 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
747 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
748 ARRAY_SIZE(ar9280Modes_9280), 6);
749 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
750 ARRAY_SIZE(ar9280Common_9280), 2);
751 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
752 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
753 ARRAY_SIZE(ar5416Modes_9160), 6);
754 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
755 ARRAY_SIZE(ar5416Common_9160), 2);
756 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
757 ARRAY_SIZE(ar5416Bank0_9160), 2);
758 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
759 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
760 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
761 ARRAY_SIZE(ar5416Bank1_9160), 2);
762 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
763 ARRAY_SIZE(ar5416Bank2_9160), 2);
764 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
765 ARRAY_SIZE(ar5416Bank3_9160), 3);
766 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
767 ARRAY_SIZE(ar5416Bank6_9160), 3);
768 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
769 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
770 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
771 ARRAY_SIZE(ar5416Bank7_9160), 2);
772 if (AR_SREV_9160_11(ah)) {
773 INIT_INI_ARRAY(&ah->iniAddac,
774 ar5416Addac_91601_1,
775 ARRAY_SIZE(ar5416Addac_91601_1), 2);
776 } else {
777 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
778 ARRAY_SIZE(ar5416Addac_9160), 2);
779 }
780 } else if (AR_SREV_9100_OR_LATER(ah)) {
781 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
782 ARRAY_SIZE(ar5416Modes_9100), 6);
783 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
784 ARRAY_SIZE(ar5416Common_9100), 2);
785 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
786 ARRAY_SIZE(ar5416Bank0_9100), 2);
787 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
788 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
789 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
790 ARRAY_SIZE(ar5416Bank1_9100), 2);
791 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
792 ARRAY_SIZE(ar5416Bank2_9100), 2);
793 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
794 ARRAY_SIZE(ar5416Bank3_9100), 3);
795 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
796 ARRAY_SIZE(ar5416Bank6_9100), 3);
797 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
798 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
799 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
800 ARRAY_SIZE(ar5416Bank7_9100), 2);
801 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
802 ARRAY_SIZE(ar5416Addac_9100), 2);
803 } else {
804 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
805 ARRAY_SIZE(ar5416Modes), 6);
806 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
807 ARRAY_SIZE(ar5416Common), 2);
808 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
809 ARRAY_SIZE(ar5416Bank0), 2);
810 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
811 ARRAY_SIZE(ar5416BB_RfGain), 3);
812 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
813 ARRAY_SIZE(ar5416Bank1), 2);
814 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
815 ARRAY_SIZE(ar5416Bank2), 2);
816 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
817 ARRAY_SIZE(ar5416Bank3), 3);
818 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
819 ARRAY_SIZE(ar5416Bank6), 3);
820 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
821 ARRAY_SIZE(ar5416Bank6TPC), 3);
822 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
823 ARRAY_SIZE(ar5416Bank7), 2);
824 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
825 ARRAY_SIZE(ar5416Addac), 2);
826 }
827 }
828
829 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
830 {
831 if (AR_SREV_9287_11_OR_LATER(ah))
832 INIT_INI_ARRAY(&ah->iniModesRxGain,
833 ar9287Modes_rx_gain_9287_1_1,
834 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
835 else if (AR_SREV_9287_10(ah))
836 INIT_INI_ARRAY(&ah->iniModesRxGain,
837 ar9287Modes_rx_gain_9287_1_0,
838 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
839 else if (AR_SREV_9280_20(ah))
840 ath9k_hw_init_rxgain_ini(ah);
841
842 if (AR_SREV_9287_11_OR_LATER(ah)) {
843 INIT_INI_ARRAY(&ah->iniModesTxGain,
844 ar9287Modes_tx_gain_9287_1_1,
845 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
846 } else if (AR_SREV_9287_10(ah)) {
847 INIT_INI_ARRAY(&ah->iniModesTxGain,
848 ar9287Modes_tx_gain_9287_1_0,
849 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
850 } else if (AR_SREV_9280_20(ah)) {
851 ath9k_hw_init_txgain_ini(ah);
852 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
853 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
854
855 /* txgain table */
856 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
857 INIT_INI_ARRAY(&ah->iniModesTxGain,
858 ar9285Modes_high_power_tx_gain_9285_1_2,
859 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
860 } else {
861 INIT_INI_ARRAY(&ah->iniModesTxGain,
862 ar9285Modes_original_tx_gain_9285_1_2,
863 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
864 }
865
866 }
867 }
868
869 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
870 {
871 u32 i, j;
872
873 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
874 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
875
876 /* EEPROM Fixup */
877 for (i = 0; i < ah->iniModes.ia_rows; i++) {
878 u32 reg = INI_RA(&ah->iniModes, i, 0);
879
880 for (j = 1; j < ah->iniModes.ia_columns; j++) {
881 u32 val = INI_RA(&ah->iniModes, i, j);
882
883 INI_RA(&ah->iniModes, i, j) =
884 ath9k_hw_ini_fixup(ah,
885 &ah->eeprom.def,
886 reg, val);
887 }
888 }
889 }
890 }
891
892 int ath9k_hw_init(struct ath_hw *ah)
893 {
894 struct ath_common *common = ath9k_hw_common(ah);
895 int r = 0;
896
897 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
898 ath_print(common, ATH_DBG_FATAL,
899 "Unsupported device ID: 0x%0x\n",
900 ah->hw_version.devid);
901 return -EOPNOTSUPP;
902 }
903
904 ath9k_hw_init_defaults(ah);
905 ath9k_hw_init_config(ah);
906
907 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
908 ath_print(common, ATH_DBG_FATAL,
909 "Couldn't reset chip\n");
910 return -EIO;
911 }
912
913 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
914 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
915 return -EIO;
916 }
917
918 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
919 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
920 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
921 ah->config.serialize_regmode =
922 SER_REG_MODE_ON;
923 } else {
924 ah->config.serialize_regmode =
925 SER_REG_MODE_OFF;
926 }
927 }
928
929 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
930 ah->config.serialize_regmode);
931
932 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
933 ath_print(common, ATH_DBG_FATAL,
934 "Mac Chip Rev 0x%02x.%x is not supported by "
935 "this driver\n", ah->hw_version.macVersion,
936 ah->hw_version.macRev);
937 return -EOPNOTSUPP;
938 }
939
940 if (AR_SREV_9100(ah)) {
941 ah->iq_caldata.calData = &iq_cal_multi_sample;
942 ah->supp_cals = IQ_MISMATCH_CAL;
943 ah->is_pciexpress = false;
944 }
945
946 if (AR_SREV_9271(ah))
947 ah->is_pciexpress = false;
948
949 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
950
951 ath9k_hw_init_cal_settings(ah);
952
953 ah->ani_function = ATH9K_ANI_ALL;
954 if (AR_SREV_9280_10_OR_LATER(ah))
955 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
956
957 ath9k_hw_init_mode_regs(ah);
958
959 if (ah->is_pciexpress)
960 ath9k_hw_configpcipowersave(ah, 0, 0);
961 else
962 ath9k_hw_disablepcie(ah);
963
964 /* Support for Japan ch.14 (2484) spread */
965 if (AR_SREV_9287_11_OR_LATER(ah)) {
966 INIT_INI_ARRAY(&ah->iniCckfirNormal,
967 ar9287Common_normal_cck_fir_coeff_92871_1,
968 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
969 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
970 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
971 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
972 }
973
974 r = ath9k_hw_post_init(ah);
975 if (r)
976 return r;
977
978 ath9k_hw_init_mode_gain_regs(ah);
979 ath9k_hw_fill_cap_info(ah);
980 ath9k_hw_init_11a_eeprom_fix(ah);
981
982 r = ath9k_hw_init_macaddr(ah);
983 if (r) {
984 ath_print(common, ATH_DBG_FATAL,
985 "Failed to initialize MAC address\n");
986 return r;
987 }
988
989 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
990 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
991 else
992 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
993
994 ath9k_init_nfcal_hist_buffer(ah);
995
996 common->state = ATH_HW_INITIALIZED;
997
998 return 0;
999 }
1000
1001 static void ath9k_hw_init_bb(struct ath_hw *ah,
1002 struct ath9k_channel *chan)
1003 {
1004 u32 synthDelay;
1005
1006 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1007 if (IS_CHAN_B(chan))
1008 synthDelay = (4 * synthDelay) / 22;
1009 else
1010 synthDelay /= 10;
1011
1012 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1013
1014 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1015 }
1016
1017 static void ath9k_hw_init_qos(struct ath_hw *ah)
1018 {
1019 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1020 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1021
1022 REG_WRITE(ah, AR_QOS_NO_ACK,
1023 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1024 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1025 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1026
1027 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1028 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1029 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1030 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1031 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1032 }
1033
1034 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1035 {
1036 u32 lcr;
1037 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1038
1039 lcr = REG_READ(ah , 0x5100c);
1040 lcr |= 0x80;
1041
1042 REG_WRITE(ah, 0x5100c, lcr);
1043 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1044 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1045
1046 lcr &= ~0x80;
1047 REG_WRITE(ah, 0x5100c, lcr);
1048 }
1049
1050 static void ath9k_hw_init_pll(struct ath_hw *ah,
1051 struct ath9k_channel *chan)
1052 {
1053 u32 pll;
1054
1055 if (AR_SREV_9100(ah)) {
1056 if (chan && IS_CHAN_5GHZ(chan))
1057 pll = 0x1450;
1058 else
1059 pll = 0x1458;
1060 } else {
1061 if (AR_SREV_9280_10_OR_LATER(ah)) {
1062 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1063
1064 if (chan && IS_CHAN_HALF_RATE(chan))
1065 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1066 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1067 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1068
1069 if (chan && IS_CHAN_5GHZ(chan)) {
1070 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1071
1072
1073 if (AR_SREV_9280_20(ah)) {
1074 if (((chan->channel % 20) == 0)
1075 || ((chan->channel % 10) == 0))
1076 pll = 0x2850;
1077 else
1078 pll = 0x142c;
1079 }
1080 } else {
1081 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1082 }
1083
1084 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1085
1086 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1087
1088 if (chan && IS_CHAN_HALF_RATE(chan))
1089 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1090 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1091 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1092
1093 if (chan && IS_CHAN_5GHZ(chan))
1094 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1095 else
1096 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1097 } else {
1098 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1099
1100 if (chan && IS_CHAN_HALF_RATE(chan))
1101 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1102 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1103 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1104
1105 if (chan && IS_CHAN_5GHZ(chan))
1106 pll |= SM(0xa, AR_RTC_PLL_DIV);
1107 else
1108 pll |= SM(0xb, AR_RTC_PLL_DIV);
1109 }
1110 }
1111 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1112
1113 /* Switch the core clock for ar9271 to 117Mhz */
1114 if (AR_SREV_9271(ah)) {
1115 if ((pll == 0x142c) || (pll == 0x2850) ) {
1116 udelay(500);
1117 /* set CLKOBS to output AHB clock */
1118 REG_WRITE(ah, 0x7020, 0xe);
1119 /*
1120 * 0x304: 117Mhz, ahb_ratio: 1x1
1121 * 0x306: 40Mhz, ahb_ratio: 1x1
1122 */
1123 REG_WRITE(ah, 0x50040, 0x304);
1124 /*
1125 * makes adjustments for the baud dividor to keep the
1126 * targetted baud rate based on the used core clock.
1127 */
1128 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1129 AR9271_TARGET_BAUD_RATE);
1130 }
1131 }
1132
1133 udelay(RTC_PLL_SETTLE_DELAY);
1134
1135 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1136 }
1137
1138 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1139 {
1140 int rx_chainmask, tx_chainmask;
1141
1142 rx_chainmask = ah->rxchainmask;
1143 tx_chainmask = ah->txchainmask;
1144
1145 switch (rx_chainmask) {
1146 case 0x5:
1147 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1148 AR_PHY_SWAP_ALT_CHAIN);
1149 case 0x3:
1150 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1151 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1152 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1153 break;
1154 }
1155 case 0x1:
1156 case 0x2:
1157 case 0x7:
1158 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1159 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1160 break;
1161 default:
1162 break;
1163 }
1164
1165 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1166 if (tx_chainmask == 0x5) {
1167 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1168 AR_PHY_SWAP_ALT_CHAIN);
1169 }
1170 if (AR_SREV_9100(ah))
1171 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1172 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1173 }
1174
1175 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1176 enum nl80211_iftype opmode)
1177 {
1178 ah->mask_reg = AR_IMR_TXERR |
1179 AR_IMR_TXURN |
1180 AR_IMR_RXERR |
1181 AR_IMR_RXORN |
1182 AR_IMR_BCNMISC;
1183
1184 if (ah->config.intr_mitigation)
1185 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1186 else
1187 ah->mask_reg |= AR_IMR_RXOK;
1188
1189 ah->mask_reg |= AR_IMR_TXOK;
1190
1191 if (opmode == NL80211_IFTYPE_AP)
1192 ah->mask_reg |= AR_IMR_MIB;
1193
1194 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1195 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1196
1197 if (!AR_SREV_9100(ah)) {
1198 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1199 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1200 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1201 }
1202 }
1203
1204 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1205 {
1206 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1207 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1208 "bad ack timeout %u\n", us);
1209 ah->acktimeout = (u32) -1;
1210 return false;
1211 } else {
1212 REG_RMW_FIELD(ah, AR_TIME_OUT,
1213 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1214 ah->acktimeout = us;
1215 return true;
1216 }
1217 }
1218
1219 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1220 {
1221 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1222 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1223 "bad cts timeout %u\n", us);
1224 ah->ctstimeout = (u32) -1;
1225 return false;
1226 } else {
1227 REG_RMW_FIELD(ah, AR_TIME_OUT,
1228 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1229 ah->ctstimeout = us;
1230 return true;
1231 }
1232 }
1233
1234 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1235 {
1236 if (tu > 0xFFFF) {
1237 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1238 "bad global tx timeout %u\n", tu);
1239 ah->globaltxtimeout = (u32) -1;
1240 return false;
1241 } else {
1242 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1243 ah->globaltxtimeout = tu;
1244 return true;
1245 }
1246 }
1247
1248 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1249 {
1250 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1251 ah->misc_mode);
1252
1253 if (ah->misc_mode != 0)
1254 REG_WRITE(ah, AR_PCU_MISC,
1255 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1256 if (ah->slottime != (u32) -1)
1257 ath9k_hw_setslottime(ah, ah->slottime);
1258 if (ah->acktimeout != (u32) -1)
1259 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1260 if (ah->ctstimeout != (u32) -1)
1261 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1262 if (ah->globaltxtimeout != (u32) -1)
1263 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1264 }
1265
1266 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1267 {
1268 return vendorid == ATHEROS_VENDOR_ID ?
1269 ath9k_hw_devname(devid) : NULL;
1270 }
1271
1272 void ath9k_hw_detach(struct ath_hw *ah)
1273 {
1274 struct ath_common *common = ath9k_hw_common(ah);
1275
1276 if (common->state <= ATH_HW_INITIALIZED)
1277 goto free_hw;
1278
1279 if (!AR_SREV_9100(ah))
1280 ath9k_hw_ani_disable(ah);
1281
1282 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1283
1284 free_hw:
1285 if (!AR_SREV_9280_10_OR_LATER(ah))
1286 ath9k_hw_rf_free_ext_banks(ah);
1287 kfree(ah);
1288 ah = NULL;
1289 }
1290 EXPORT_SYMBOL(ath9k_hw_detach);
1291
1292 /*******/
1293 /* INI */
1294 /*******/
1295
1296 static void ath9k_hw_override_ini(struct ath_hw *ah,
1297 struct ath9k_channel *chan)
1298 {
1299 u32 val;
1300
1301 if (AR_SREV_9271(ah)) {
1302 /*
1303 * Enable spectral scan to solution for issues with stuck
1304 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1305 * AR9271 1.1
1306 */
1307 if (AR_SREV_9271_10(ah)) {
1308 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1309 AR_PHY_SPECTRAL_SCAN_ENABLE;
1310 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1311 }
1312 else if (AR_SREV_9271_11(ah))
1313 /*
1314 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1315 * present on AR9271 1.1
1316 */
1317 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1318 return;
1319 }
1320
1321 /*
1322 * Set the RX_ABORT and RX_DIS and clear if off only after
1323 * RXE is set for MAC. This prevents frames with corrupted
1324 * descriptor status.
1325 */
1326 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1327
1328 if (AR_SREV_9280_10_OR_LATER(ah)) {
1329 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1330 (~AR_PCU_MISC_MODE2_HWWAR1);
1331
1332 if (AR_SREV_9287_10_OR_LATER(ah))
1333 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1334
1335 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1336 }
1337
1338 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1339 AR_SREV_9280_10_OR_LATER(ah))
1340 return;
1341 /*
1342 * Disable BB clock gating
1343 * Necessary to avoid issues on AR5416 2.0
1344 */
1345 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1346 }
1347
1348 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1349 struct ar5416_eeprom_def *pEepData,
1350 u32 reg, u32 value)
1351 {
1352 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1353 struct ath_common *common = ath9k_hw_common(ah);
1354
1355 switch (ah->hw_version.devid) {
1356 case AR9280_DEVID_PCI:
1357 if (reg == 0x7894) {
1358 ath_print(common, ATH_DBG_EEPROM,
1359 "ini VAL: %x EEPROM: %x\n", value,
1360 (pBase->version & 0xff));
1361
1362 if ((pBase->version & 0xff) > 0x0a) {
1363 ath_print(common, ATH_DBG_EEPROM,
1364 "PWDCLKIND: %d\n",
1365 pBase->pwdclkind);
1366 value &= ~AR_AN_TOP2_PWDCLKIND;
1367 value |= AR_AN_TOP2_PWDCLKIND &
1368 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1369 } else {
1370 ath_print(common, ATH_DBG_EEPROM,
1371 "PWDCLKIND Earlier Rev\n");
1372 }
1373
1374 ath_print(common, ATH_DBG_EEPROM,
1375 "final ini VAL: %x\n", value);
1376 }
1377 break;
1378 }
1379
1380 return value;
1381 }
1382
1383 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1384 struct ar5416_eeprom_def *pEepData,
1385 u32 reg, u32 value)
1386 {
1387 if (ah->eep_map == EEP_MAP_4KBITS)
1388 return value;
1389 else
1390 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1391 }
1392
1393 static void ath9k_olc_init(struct ath_hw *ah)
1394 {
1395 u32 i;
1396
1397 if (OLC_FOR_AR9287_10_LATER) {
1398 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1399 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1400 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1401 AR9287_AN_TXPC0_TXPCMODE,
1402 AR9287_AN_TXPC0_TXPCMODE_S,
1403 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1404 udelay(100);
1405 } else {
1406 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1407 ah->originalGain[i] =
1408 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1409 AR_PHY_TX_GAIN);
1410 ah->PDADCdelta = 0;
1411 }
1412 }
1413
1414 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1415 struct ath9k_channel *chan)
1416 {
1417 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1418
1419 if (IS_CHAN_B(chan))
1420 ctl |= CTL_11B;
1421 else if (IS_CHAN_G(chan))
1422 ctl |= CTL_11G;
1423 else
1424 ctl |= CTL_11A;
1425
1426 return ctl;
1427 }
1428
1429 static int ath9k_hw_process_ini(struct ath_hw *ah,
1430 struct ath9k_channel *chan)
1431 {
1432 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1433 int i, regWrites = 0;
1434 struct ieee80211_channel *channel = chan->chan;
1435 u32 modesIndex, freqIndex;
1436
1437 switch (chan->chanmode) {
1438 case CHANNEL_A:
1439 case CHANNEL_A_HT20:
1440 modesIndex = 1;
1441 freqIndex = 1;
1442 break;
1443 case CHANNEL_A_HT40PLUS:
1444 case CHANNEL_A_HT40MINUS:
1445 modesIndex = 2;
1446 freqIndex = 1;
1447 break;
1448 case CHANNEL_G:
1449 case CHANNEL_G_HT20:
1450 case CHANNEL_B:
1451 modesIndex = 4;
1452 freqIndex = 2;
1453 break;
1454 case CHANNEL_G_HT40PLUS:
1455 case CHANNEL_G_HT40MINUS:
1456 modesIndex = 3;
1457 freqIndex = 2;
1458 break;
1459
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1465 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1466 ah->eep_ops->set_addac(ah, chan);
1467
1468 if (AR_SREV_5416_22_OR_LATER(ah)) {
1469 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1470 } else {
1471 struct ar5416IniArray temp;
1472 u32 addacSize =
1473 sizeof(u32) * ah->iniAddac.ia_rows *
1474 ah->iniAddac.ia_columns;
1475
1476 memcpy(ah->addac5416_21,
1477 ah->iniAddac.ia_array, addacSize);
1478
1479 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1480
1481 temp.ia_array = ah->addac5416_21;
1482 temp.ia_columns = ah->iniAddac.ia_columns;
1483 temp.ia_rows = ah->iniAddac.ia_rows;
1484 REG_WRITE_ARRAY(&temp, 1, regWrites);
1485 }
1486
1487 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1488
1489 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1490 u32 reg = INI_RA(&ah->iniModes, i, 0);
1491 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1492
1493 REG_WRITE(ah, reg, val);
1494
1495 if (reg >= 0x7800 && reg < 0x78a0
1496 && ah->config.analog_shiftreg) {
1497 udelay(100);
1498 }
1499
1500 DO_DELAY(regWrites);
1501 }
1502
1503 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1504 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1505
1506 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1507 AR_SREV_9287_10_OR_LATER(ah))
1508 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1509
1510 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1511 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1512 u32 val = INI_RA(&ah->iniCommon, i, 1);
1513
1514 REG_WRITE(ah, reg, val);
1515
1516 if (reg >= 0x7800 && reg < 0x78a0
1517 && ah->config.analog_shiftreg) {
1518 udelay(100);
1519 }
1520
1521 DO_DELAY(regWrites);
1522 }
1523
1524 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1525
1526 if (AR_SREV_9271_10(ah))
1527 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1528 modesIndex, regWrites);
1529
1530 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1531 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1532 regWrites);
1533 }
1534
1535 ath9k_hw_override_ini(ah, chan);
1536 ath9k_hw_set_regs(ah, chan);
1537 ath9k_hw_init_chain_masks(ah);
1538
1539 if (OLC_FOR_AR9280_20_LATER)
1540 ath9k_olc_init(ah);
1541
1542 ah->eep_ops->set_txpower(ah, chan,
1543 ath9k_regd_get_ctl(regulatory, chan),
1544 channel->max_antenna_gain * 2,
1545 channel->max_power * 2,
1546 min((u32) MAX_RATE_POWER,
1547 (u32) regulatory->power_limit));
1548
1549 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1550 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1551 "ar5416SetRfRegs failed\n");
1552 return -EIO;
1553 }
1554
1555 return 0;
1556 }
1557
1558 /****************************************/
1559 /* Reset and Channel Switching Routines */
1560 /****************************************/
1561
1562 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1563 {
1564 u32 rfMode = 0;
1565
1566 if (chan == NULL)
1567 return;
1568
1569 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1570 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1571
1572 if (!AR_SREV_9280_10_OR_LATER(ah))
1573 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1574 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1575
1576 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1577 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1578
1579 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1580 }
1581
1582 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1583 {
1584 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1585 }
1586
1587 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1588 {
1589 u32 regval;
1590
1591 /*
1592 * set AHB_MODE not to do cacheline prefetches
1593 */
1594 regval = REG_READ(ah, AR_AHB_MODE);
1595 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1596
1597 /*
1598 * let mac dma reads be in 128 byte chunks
1599 */
1600 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1601 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1602
1603 /*
1604 * Restore TX Trigger Level to its pre-reset value.
1605 * The initial value depends on whether aggregation is enabled, and is
1606 * adjusted whenever underruns are detected.
1607 */
1608 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1609
1610 /*
1611 * let mac dma writes be in 128 byte chunks
1612 */
1613 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1614 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1615
1616 /*
1617 * Setup receive FIFO threshold to hold off TX activities
1618 */
1619 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1620
1621 /*
1622 * reduce the number of usable entries in PCU TXBUF to avoid
1623 * wrap around issues.
1624 */
1625 if (AR_SREV_9285(ah)) {
1626 /* For AR9285 the number of Fifos are reduced to half.
1627 * So set the usable tx buf size also to half to
1628 * avoid data/delimiter underruns
1629 */
1630 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1631 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1632 } else if (!AR_SREV_9271(ah)) {
1633 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1634 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1635 }
1636 }
1637
1638 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1639 {
1640 u32 val;
1641
1642 val = REG_READ(ah, AR_STA_ID1);
1643 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1644 switch (opmode) {
1645 case NL80211_IFTYPE_AP:
1646 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1647 | AR_STA_ID1_KSRCH_MODE);
1648 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1649 break;
1650 case NL80211_IFTYPE_ADHOC:
1651 case NL80211_IFTYPE_MESH_POINT:
1652 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1653 | AR_STA_ID1_KSRCH_MODE);
1654 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1655 break;
1656 case NL80211_IFTYPE_STATION:
1657 case NL80211_IFTYPE_MONITOR:
1658 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1659 break;
1660 }
1661 }
1662
1663 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1664 u32 coef_scaled,
1665 u32 *coef_mantissa,
1666 u32 *coef_exponent)
1667 {
1668 u32 coef_exp, coef_man;
1669
1670 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1671 if ((coef_scaled >> coef_exp) & 0x1)
1672 break;
1673
1674 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1675
1676 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1677
1678 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1679 *coef_exponent = coef_exp - 16;
1680 }
1681
1682 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1683 struct ath9k_channel *chan)
1684 {
1685 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1686 u32 clockMhzScaled = 0x64000000;
1687 struct chan_centers centers;
1688
1689 if (IS_CHAN_HALF_RATE(chan))
1690 clockMhzScaled = clockMhzScaled >> 1;
1691 else if (IS_CHAN_QUARTER_RATE(chan))
1692 clockMhzScaled = clockMhzScaled >> 2;
1693
1694 ath9k_hw_get_channel_centers(ah, chan, &centers);
1695 coef_scaled = clockMhzScaled / centers.synth_center;
1696
1697 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1698 &ds_coef_exp);
1699
1700 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1701 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1702 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1703 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1704
1705 coef_scaled = (9 * coef_scaled) / 10;
1706
1707 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1708 &ds_coef_exp);
1709
1710 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1711 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1712 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1713 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1714 }
1715
1716 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1717 {
1718 u32 rst_flags;
1719 u32 tmpReg;
1720
1721 if (AR_SREV_9100(ah)) {
1722 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1723 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1724 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1725 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1726 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1727 }
1728
1729 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1730 AR_RTC_FORCE_WAKE_ON_INT);
1731
1732 if (AR_SREV_9100(ah)) {
1733 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1734 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1735 } else {
1736 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1737 if (tmpReg &
1738 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1739 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1740 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1741 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1742 } else {
1743 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1744 }
1745
1746 rst_flags = AR_RTC_RC_MAC_WARM;
1747 if (type == ATH9K_RESET_COLD)
1748 rst_flags |= AR_RTC_RC_MAC_COLD;
1749 }
1750
1751 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1752 udelay(50);
1753
1754 REG_WRITE(ah, AR_RTC_RC, 0);
1755 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1756 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1757 "RTC stuck in MAC reset\n");
1758 return false;
1759 }
1760
1761 if (!AR_SREV_9100(ah))
1762 REG_WRITE(ah, AR_RC, 0);
1763
1764 if (AR_SREV_9100(ah))
1765 udelay(50);
1766
1767 return true;
1768 }
1769
1770 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1771 {
1772 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1773 AR_RTC_FORCE_WAKE_ON_INT);
1774
1775 if (!AR_SREV_9100(ah))
1776 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1777
1778 REG_WRITE(ah, AR_RTC_RESET, 0);
1779 udelay(2);
1780
1781 if (!AR_SREV_9100(ah))
1782 REG_WRITE(ah, AR_RC, 0);
1783
1784 REG_WRITE(ah, AR_RTC_RESET, 1);
1785
1786 if (!ath9k_hw_wait(ah,
1787 AR_RTC_STATUS,
1788 AR_RTC_STATUS_M,
1789 AR_RTC_STATUS_ON,
1790 AH_WAIT_TIMEOUT)) {
1791 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1792 "RTC not waking up\n");
1793 return false;
1794 }
1795
1796 ath9k_hw_read_revisions(ah);
1797
1798 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1799 }
1800
1801 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1802 {
1803 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1804 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1805
1806 switch (type) {
1807 case ATH9K_RESET_POWER_ON:
1808 return ath9k_hw_set_reset_power_on(ah);
1809 case ATH9K_RESET_WARM:
1810 case ATH9K_RESET_COLD:
1811 return ath9k_hw_set_reset(ah, type);
1812 default:
1813 return false;
1814 }
1815 }
1816
1817 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1818 {
1819 u32 phymode;
1820 u32 enableDacFifo = 0;
1821
1822 if (AR_SREV_9285_10_OR_LATER(ah))
1823 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1824 AR_PHY_FC_ENABLE_DAC_FIFO);
1825
1826 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1827 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1828
1829 if (IS_CHAN_HT40(chan)) {
1830 phymode |= AR_PHY_FC_DYN2040_EN;
1831
1832 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1833 (chan->chanmode == CHANNEL_G_HT40PLUS))
1834 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1835
1836 }
1837 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1838
1839 ath9k_hw_set11nmac2040(ah);
1840
1841 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1842 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1843 }
1844
1845 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1846 struct ath9k_channel *chan)
1847 {
1848 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1849 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1850 return false;
1851 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1852 return false;
1853
1854 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1855 return false;
1856
1857 ah->chip_fullsleep = false;
1858 ath9k_hw_init_pll(ah, chan);
1859 ath9k_hw_set_rfmode(ah, chan);
1860
1861 return true;
1862 }
1863
1864 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1865 struct ath9k_channel *chan)
1866 {
1867 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1868 struct ath_common *common = ath9k_hw_common(ah);
1869 struct ieee80211_channel *channel = chan->chan;
1870 u32 synthDelay, qnum;
1871
1872 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1873 if (ath9k_hw_numtxpending(ah, qnum)) {
1874 ath_print(common, ATH_DBG_QUEUE,
1875 "Transmit frames pending on "
1876 "queue %d\n", qnum);
1877 return false;
1878 }
1879 }
1880
1881 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1882 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1883 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1884 ath_print(common, ATH_DBG_FATAL,
1885 "Could not kill baseband RX\n");
1886 return false;
1887 }
1888
1889 ath9k_hw_set_regs(ah, chan);
1890
1891 if (AR_SREV_9280_10_OR_LATER(ah)) {
1892 ath9k_hw_ar9280_set_channel(ah, chan);
1893 } else {
1894 if (!(ath9k_hw_set_channel(ah, chan))) {
1895 ath_print(common, ATH_DBG_FATAL,
1896 "Failed to set channel\n");
1897 return false;
1898 }
1899 }
1900
1901 ah->eep_ops->set_txpower(ah, chan,
1902 ath9k_regd_get_ctl(regulatory, chan),
1903 channel->max_antenna_gain * 2,
1904 channel->max_power * 2,
1905 min((u32) MAX_RATE_POWER,
1906 (u32) regulatory->power_limit));
1907
1908 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1909 if (IS_CHAN_B(chan))
1910 synthDelay = (4 * synthDelay) / 22;
1911 else
1912 synthDelay /= 10;
1913
1914 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1915
1916 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1917
1918 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1919 ath9k_hw_set_delta_slope(ah, chan);
1920
1921 if (AR_SREV_9280_10_OR_LATER(ah))
1922 ath9k_hw_9280_spur_mitigate(ah, chan);
1923 else
1924 ath9k_hw_spur_mitigate(ah, chan);
1925
1926 if (!chan->oneTimeCalsDone)
1927 chan->oneTimeCalsDone = true;
1928
1929 return true;
1930 }
1931
1932 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1933 {
1934 int bb_spur = AR_NO_SPUR;
1935 int freq;
1936 int bin, cur_bin;
1937 int bb_spur_off, spur_subchannel_sd;
1938 int spur_freq_sd;
1939 int spur_delta_phase;
1940 int denominator;
1941 int upper, lower, cur_vit_mask;
1942 int tmp, newVal;
1943 int i;
1944 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1945 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1946 };
1947 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1948 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1949 };
1950 int inc[4] = { 0, 100, 0, 0 };
1951 struct chan_centers centers;
1952
1953 int8_t mask_m[123];
1954 int8_t mask_p[123];
1955 int8_t mask_amt;
1956 int tmp_mask;
1957 int cur_bb_spur;
1958 bool is2GHz = IS_CHAN_2GHZ(chan);
1959
1960 memset(&mask_m, 0, sizeof(int8_t) * 123);
1961 memset(&mask_p, 0, sizeof(int8_t) * 123);
1962
1963 ath9k_hw_get_channel_centers(ah, chan, &centers);
1964 freq = centers.synth_center;
1965
1966 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1967 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1968 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1969
1970 if (is2GHz)
1971 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1972 else
1973 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1974
1975 if (AR_NO_SPUR == cur_bb_spur)
1976 break;
1977 cur_bb_spur = cur_bb_spur - freq;
1978
1979 if (IS_CHAN_HT40(chan)) {
1980 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1981 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1982 bb_spur = cur_bb_spur;
1983 break;
1984 }
1985 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1986 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1987 bb_spur = cur_bb_spur;
1988 break;
1989 }
1990 }
1991
1992 if (AR_NO_SPUR == bb_spur) {
1993 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1994 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1995 return;
1996 } else {
1997 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1998 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1999 }
2000
2001 bin = bb_spur * 320;
2002
2003 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2004
2005 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2006 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2007 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2008 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2009 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
2010
2011 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2012 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2013 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2014 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2015 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2016 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
2017
2018 if (IS_CHAN_HT40(chan)) {
2019 if (bb_spur < 0) {
2020 spur_subchannel_sd = 1;
2021 bb_spur_off = bb_spur + 10;
2022 } else {
2023 spur_subchannel_sd = 0;
2024 bb_spur_off = bb_spur - 10;
2025 }
2026 } else {
2027 spur_subchannel_sd = 0;
2028 bb_spur_off = bb_spur;
2029 }
2030
2031 if (IS_CHAN_HT40(chan))
2032 spur_delta_phase =
2033 ((bb_spur * 262144) /
2034 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2035 else
2036 spur_delta_phase =
2037 ((bb_spur * 524288) /
2038 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2039
2040 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2041 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2042
2043 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2044 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2045 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2046 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2047
2048 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2049 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2050
2051 cur_bin = -6000;
2052 upper = bin + 100;
2053 lower = bin - 100;
2054
2055 for (i = 0; i < 4; i++) {
2056 int pilot_mask = 0;
2057 int chan_mask = 0;
2058 int bp = 0;
2059 for (bp = 0; bp < 30; bp++) {
2060 if ((cur_bin > lower) && (cur_bin < upper)) {
2061 pilot_mask = pilot_mask | 0x1 << bp;
2062 chan_mask = chan_mask | 0x1 << bp;
2063 }
2064 cur_bin += 100;
2065 }
2066 cur_bin += inc[i];
2067 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2068 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2069 }
2070
2071 cur_vit_mask = 6100;
2072 upper = bin + 120;
2073 lower = bin - 120;
2074
2075 for (i = 0; i < 123; i++) {
2076 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2077
2078 /* workaround for gcc bug #37014 */
2079 volatile int tmp_v = abs(cur_vit_mask - bin);
2080
2081 if (tmp_v < 75)
2082 mask_amt = 1;
2083 else
2084 mask_amt = 0;
2085 if (cur_vit_mask < 0)
2086 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2087 else
2088 mask_p[cur_vit_mask / 100] = mask_amt;
2089 }
2090 cur_vit_mask -= 100;
2091 }
2092
2093 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2094 | (mask_m[48] << 26) | (mask_m[49] << 24)
2095 | (mask_m[50] << 22) | (mask_m[51] << 20)
2096 | (mask_m[52] << 18) | (mask_m[53] << 16)
2097 | (mask_m[54] << 14) | (mask_m[55] << 12)
2098 | (mask_m[56] << 10) | (mask_m[57] << 8)
2099 | (mask_m[58] << 6) | (mask_m[59] << 4)
2100 | (mask_m[60] << 2) | (mask_m[61] << 0);
2101 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2102 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2103
2104 tmp_mask = (mask_m[31] << 28)
2105 | (mask_m[32] << 26) | (mask_m[33] << 24)
2106 | (mask_m[34] << 22) | (mask_m[35] << 20)
2107 | (mask_m[36] << 18) | (mask_m[37] << 16)
2108 | (mask_m[48] << 14) | (mask_m[39] << 12)
2109 | (mask_m[40] << 10) | (mask_m[41] << 8)
2110 | (mask_m[42] << 6) | (mask_m[43] << 4)
2111 | (mask_m[44] << 2) | (mask_m[45] << 0);
2112 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2113 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2114
2115 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2116 | (mask_m[18] << 26) | (mask_m[18] << 24)
2117 | (mask_m[20] << 22) | (mask_m[20] << 20)
2118 | (mask_m[22] << 18) | (mask_m[22] << 16)
2119 | (mask_m[24] << 14) | (mask_m[24] << 12)
2120 | (mask_m[25] << 10) | (mask_m[26] << 8)
2121 | (mask_m[27] << 6) | (mask_m[28] << 4)
2122 | (mask_m[29] << 2) | (mask_m[30] << 0);
2123 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2124 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2125
2126 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2127 | (mask_m[2] << 26) | (mask_m[3] << 24)
2128 | (mask_m[4] << 22) | (mask_m[5] << 20)
2129 | (mask_m[6] << 18) | (mask_m[7] << 16)
2130 | (mask_m[8] << 14) | (mask_m[9] << 12)
2131 | (mask_m[10] << 10) | (mask_m[11] << 8)
2132 | (mask_m[12] << 6) | (mask_m[13] << 4)
2133 | (mask_m[14] << 2) | (mask_m[15] << 0);
2134 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2135 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2136
2137 tmp_mask = (mask_p[15] << 28)
2138 | (mask_p[14] << 26) | (mask_p[13] << 24)
2139 | (mask_p[12] << 22) | (mask_p[11] << 20)
2140 | (mask_p[10] << 18) | (mask_p[9] << 16)
2141 | (mask_p[8] << 14) | (mask_p[7] << 12)
2142 | (mask_p[6] << 10) | (mask_p[5] << 8)
2143 | (mask_p[4] << 6) | (mask_p[3] << 4)
2144 | (mask_p[2] << 2) | (mask_p[1] << 0);
2145 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2146 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2147
2148 tmp_mask = (mask_p[30] << 28)
2149 | (mask_p[29] << 26) | (mask_p[28] << 24)
2150 | (mask_p[27] << 22) | (mask_p[26] << 20)
2151 | (mask_p[25] << 18) | (mask_p[24] << 16)
2152 | (mask_p[23] << 14) | (mask_p[22] << 12)
2153 | (mask_p[21] << 10) | (mask_p[20] << 8)
2154 | (mask_p[19] << 6) | (mask_p[18] << 4)
2155 | (mask_p[17] << 2) | (mask_p[16] << 0);
2156 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2157 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2158
2159 tmp_mask = (mask_p[45] << 28)
2160 | (mask_p[44] << 26) | (mask_p[43] << 24)
2161 | (mask_p[42] << 22) | (mask_p[41] << 20)
2162 | (mask_p[40] << 18) | (mask_p[39] << 16)
2163 | (mask_p[38] << 14) | (mask_p[37] << 12)
2164 | (mask_p[36] << 10) | (mask_p[35] << 8)
2165 | (mask_p[34] << 6) | (mask_p[33] << 4)
2166 | (mask_p[32] << 2) | (mask_p[31] << 0);
2167 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2168 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2169
2170 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2171 | (mask_p[59] << 26) | (mask_p[58] << 24)
2172 | (mask_p[57] << 22) | (mask_p[56] << 20)
2173 | (mask_p[55] << 18) | (mask_p[54] << 16)
2174 | (mask_p[53] << 14) | (mask_p[52] << 12)
2175 | (mask_p[51] << 10) | (mask_p[50] << 8)
2176 | (mask_p[49] << 6) | (mask_p[48] << 4)
2177 | (mask_p[47] << 2) | (mask_p[46] << 0);
2178 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2179 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2180 }
2181
2182 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2183 {
2184 int bb_spur = AR_NO_SPUR;
2185 int bin, cur_bin;
2186 int spur_freq_sd;
2187 int spur_delta_phase;
2188 int denominator;
2189 int upper, lower, cur_vit_mask;
2190 int tmp, new;
2191 int i;
2192 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2193 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2194 };
2195 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2196 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2197 };
2198 int inc[4] = { 0, 100, 0, 0 };
2199
2200 int8_t mask_m[123];
2201 int8_t mask_p[123];
2202 int8_t mask_amt;
2203 int tmp_mask;
2204 int cur_bb_spur;
2205 bool is2GHz = IS_CHAN_2GHZ(chan);
2206
2207 memset(&mask_m, 0, sizeof(int8_t) * 123);
2208 memset(&mask_p, 0, sizeof(int8_t) * 123);
2209
2210 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2211 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2212 if (AR_NO_SPUR == cur_bb_spur)
2213 break;
2214 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2215 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2216 bb_spur = cur_bb_spur;
2217 break;
2218 }
2219 }
2220
2221 if (AR_NO_SPUR == bb_spur)
2222 return;
2223
2224 bin = bb_spur * 32;
2225
2226 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2227 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2228 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2229 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2230 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2231
2232 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2233
2234 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2235 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2236 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2237 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2238 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2239 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2240
2241 spur_delta_phase = ((bb_spur * 524288) / 100) &
2242 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2243
2244 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2245 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2246
2247 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2248 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2249 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2250 REG_WRITE(ah, AR_PHY_TIMING11, new);
2251
2252 cur_bin = -6000;
2253 upper = bin + 100;
2254 lower = bin - 100;
2255
2256 for (i = 0; i < 4; i++) {
2257 int pilot_mask = 0;
2258 int chan_mask = 0;
2259 int bp = 0;
2260 for (bp = 0; bp < 30; bp++) {
2261 if ((cur_bin > lower) && (cur_bin < upper)) {
2262 pilot_mask = pilot_mask | 0x1 << bp;
2263 chan_mask = chan_mask | 0x1 << bp;
2264 }
2265 cur_bin += 100;
2266 }
2267 cur_bin += inc[i];
2268 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2269 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2270 }
2271
2272 cur_vit_mask = 6100;
2273 upper = bin + 120;
2274 lower = bin - 120;
2275
2276 for (i = 0; i < 123; i++) {
2277 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2278
2279 /* workaround for gcc bug #37014 */
2280 volatile int tmp_v = abs(cur_vit_mask - bin);
2281
2282 if (tmp_v < 75)
2283 mask_amt = 1;
2284 else
2285 mask_amt = 0;
2286 if (cur_vit_mask < 0)
2287 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2288 else
2289 mask_p[cur_vit_mask / 100] = mask_amt;
2290 }
2291 cur_vit_mask -= 100;
2292 }
2293
2294 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2295 | (mask_m[48] << 26) | (mask_m[49] << 24)
2296 | (mask_m[50] << 22) | (mask_m[51] << 20)
2297 | (mask_m[52] << 18) | (mask_m[53] << 16)
2298 | (mask_m[54] << 14) | (mask_m[55] << 12)
2299 | (mask_m[56] << 10) | (mask_m[57] << 8)
2300 | (mask_m[58] << 6) | (mask_m[59] << 4)
2301 | (mask_m[60] << 2) | (mask_m[61] << 0);
2302 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2303 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2304
2305 tmp_mask = (mask_m[31] << 28)
2306 | (mask_m[32] << 26) | (mask_m[33] << 24)
2307 | (mask_m[34] << 22) | (mask_m[35] << 20)
2308 | (mask_m[36] << 18) | (mask_m[37] << 16)
2309 | (mask_m[48] << 14) | (mask_m[39] << 12)
2310 | (mask_m[40] << 10) | (mask_m[41] << 8)
2311 | (mask_m[42] << 6) | (mask_m[43] << 4)
2312 | (mask_m[44] << 2) | (mask_m[45] << 0);
2313 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2314 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2315
2316 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2317 | (mask_m[18] << 26) | (mask_m[18] << 24)
2318 | (mask_m[20] << 22) | (mask_m[20] << 20)
2319 | (mask_m[22] << 18) | (mask_m[22] << 16)
2320 | (mask_m[24] << 14) | (mask_m[24] << 12)
2321 | (mask_m[25] << 10) | (mask_m[26] << 8)
2322 | (mask_m[27] << 6) | (mask_m[28] << 4)
2323 | (mask_m[29] << 2) | (mask_m[30] << 0);
2324 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2325 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2326
2327 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2328 | (mask_m[2] << 26) | (mask_m[3] << 24)
2329 | (mask_m[4] << 22) | (mask_m[5] << 20)
2330 | (mask_m[6] << 18) | (mask_m[7] << 16)
2331 | (mask_m[8] << 14) | (mask_m[9] << 12)
2332 | (mask_m[10] << 10) | (mask_m[11] << 8)
2333 | (mask_m[12] << 6) | (mask_m[13] << 4)
2334 | (mask_m[14] << 2) | (mask_m[15] << 0);
2335 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2336 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2337
2338 tmp_mask = (mask_p[15] << 28)
2339 | (mask_p[14] << 26) | (mask_p[13] << 24)
2340 | (mask_p[12] << 22) | (mask_p[11] << 20)
2341 | (mask_p[10] << 18) | (mask_p[9] << 16)
2342 | (mask_p[8] << 14) | (mask_p[7] << 12)
2343 | (mask_p[6] << 10) | (mask_p[5] << 8)
2344 | (mask_p[4] << 6) | (mask_p[3] << 4)
2345 | (mask_p[2] << 2) | (mask_p[1] << 0);
2346 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2347 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2348
2349 tmp_mask = (mask_p[30] << 28)
2350 | (mask_p[29] << 26) | (mask_p[28] << 24)
2351 | (mask_p[27] << 22) | (mask_p[26] << 20)
2352 | (mask_p[25] << 18) | (mask_p[24] << 16)
2353 | (mask_p[23] << 14) | (mask_p[22] << 12)
2354 | (mask_p[21] << 10) | (mask_p[20] << 8)
2355 | (mask_p[19] << 6) | (mask_p[18] << 4)
2356 | (mask_p[17] << 2) | (mask_p[16] << 0);
2357 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2358 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2359
2360 tmp_mask = (mask_p[45] << 28)
2361 | (mask_p[44] << 26) | (mask_p[43] << 24)
2362 | (mask_p[42] << 22) | (mask_p[41] << 20)
2363 | (mask_p[40] << 18) | (mask_p[39] << 16)
2364 | (mask_p[38] << 14) | (mask_p[37] << 12)
2365 | (mask_p[36] << 10) | (mask_p[35] << 8)
2366 | (mask_p[34] << 6) | (mask_p[33] << 4)
2367 | (mask_p[32] << 2) | (mask_p[31] << 0);
2368 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2369 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2370
2371 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2372 | (mask_p[59] << 26) | (mask_p[58] << 24)
2373 | (mask_p[57] << 22) | (mask_p[56] << 20)
2374 | (mask_p[55] << 18) | (mask_p[54] << 16)
2375 | (mask_p[53] << 14) | (mask_p[52] << 12)
2376 | (mask_p[51] << 10) | (mask_p[50] << 8)
2377 | (mask_p[49] << 6) | (mask_p[48] << 4)
2378 | (mask_p[47] << 2) | (mask_p[46] << 0);
2379 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2380 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2381 }
2382
2383 static void ath9k_enable_rfkill(struct ath_hw *ah)
2384 {
2385 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2386 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2387
2388 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2389 AR_GPIO_INPUT_MUX2_RFSILENT);
2390
2391 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2392 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2393 }
2394
2395 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2396 bool bChannelChange)
2397 {
2398 struct ath_common *common = ath9k_hw_common(ah);
2399 u32 saveLedState;
2400 struct ath9k_channel *curchan = ah->curchan;
2401 u32 saveDefAntenna;
2402 u32 macStaId1;
2403 u64 tsf = 0;
2404 int i, rx_chainmask, r;
2405
2406 ah->txchainmask = common->tx_chainmask;
2407 ah->rxchainmask = common->rx_chainmask;
2408
2409 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2410 return -EIO;
2411
2412 if (curchan && !ah->chip_fullsleep)
2413 ath9k_hw_getnf(ah, curchan);
2414
2415 if (bChannelChange &&
2416 (ah->chip_fullsleep != true) &&
2417 (ah->curchan != NULL) &&
2418 (chan->channel != ah->curchan->channel) &&
2419 ((chan->channelFlags & CHANNEL_ALL) ==
2420 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2421 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2422 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2423
2424 if (ath9k_hw_channel_change(ah, chan)) {
2425 ath9k_hw_loadnf(ah, ah->curchan);
2426 ath9k_hw_start_nfcal(ah);
2427 return 0;
2428 }
2429 }
2430
2431 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2432 if (saveDefAntenna == 0)
2433 saveDefAntenna = 1;
2434
2435 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2436
2437 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2438 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2439 tsf = ath9k_hw_gettsf64(ah);
2440
2441 saveLedState = REG_READ(ah, AR_CFG_LED) &
2442 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2443 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2444
2445 ath9k_hw_mark_phy_inactive(ah);
2446
2447 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2448 REG_WRITE(ah,
2449 AR9271_RESET_POWER_DOWN_CONTROL,
2450 AR9271_RADIO_RF_RST);
2451 udelay(50);
2452 }
2453
2454 if (!ath9k_hw_chip_reset(ah, chan)) {
2455 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2456 return -EINVAL;
2457 }
2458
2459 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2460 ah->htc_reset_init = false;
2461 REG_WRITE(ah,
2462 AR9271_RESET_POWER_DOWN_CONTROL,
2463 AR9271_GATE_MAC_CTL);
2464 udelay(50);
2465 }
2466
2467 /* Restore TSF */
2468 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2469 ath9k_hw_settsf64(ah, tsf);
2470
2471 if (AR_SREV_9280_10_OR_LATER(ah))
2472 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2473
2474 if (AR_SREV_9287_12_OR_LATER(ah)) {
2475 /* Enable ASYNC FIFO */
2476 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2477 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2478 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2479 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2480 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2481 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2482 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2483 }
2484 r = ath9k_hw_process_ini(ah, chan);
2485 if (r)
2486 return r;
2487
2488 /* Setup MFP options for CCMP */
2489 if (AR_SREV_9280_20_OR_LATER(ah)) {
2490 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2491 * frames when constructing CCMP AAD. */
2492 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2493 0xc7ff);
2494 ah->sw_mgmt_crypto = false;
2495 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2496 /* Disable hardware crypto for management frames */
2497 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2498 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2499 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2500 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2501 ah->sw_mgmt_crypto = true;
2502 } else
2503 ah->sw_mgmt_crypto = true;
2504
2505 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2506 ath9k_hw_set_delta_slope(ah, chan);
2507
2508 if (AR_SREV_9280_10_OR_LATER(ah))
2509 ath9k_hw_9280_spur_mitigate(ah, chan);
2510 else
2511 ath9k_hw_spur_mitigate(ah, chan);
2512
2513 ah->eep_ops->set_board_values(ah, chan);
2514
2515 ath9k_hw_decrease_chain_power(ah, chan);
2516
2517 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2518 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2519 | macStaId1
2520 | AR_STA_ID1_RTS_USE_DEF
2521 | (ah->config.
2522 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2523 | ah->sta_id1_defaults);
2524 ath9k_hw_set_operating_mode(ah, ah->opmode);
2525
2526 ath_hw_setbssidmask(common);
2527
2528 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2529
2530 ath9k_hw_write_associd(ah);
2531
2532 REG_WRITE(ah, AR_ISR, ~0);
2533
2534 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2535
2536 if (AR_SREV_9280_10_OR_LATER(ah))
2537 ath9k_hw_ar9280_set_channel(ah, chan);
2538 else
2539 if (!(ath9k_hw_set_channel(ah, chan)))
2540 return -EIO;
2541
2542 for (i = 0; i < AR_NUM_DCU; i++)
2543 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2544
2545 ah->intr_txqs = 0;
2546 for (i = 0; i < ah->caps.total_queues; i++)
2547 ath9k_hw_resettxqueue(ah, i);
2548
2549 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2550 ath9k_hw_init_qos(ah);
2551
2552 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2553 ath9k_enable_rfkill(ah);
2554
2555 ath9k_hw_init_user_settings(ah);
2556
2557 if (AR_SREV_9287_12_OR_LATER(ah)) {
2558 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2559 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2560 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2561 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2562 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2563 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2564
2565 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2566 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2567
2568 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2569 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2570 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2571 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2572 }
2573 if (AR_SREV_9287_12_OR_LATER(ah)) {
2574 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2575 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2576 }
2577
2578 REG_WRITE(ah, AR_STA_ID1,
2579 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2580
2581 ath9k_hw_set_dma(ah);
2582
2583 REG_WRITE(ah, AR_OBS, 8);
2584
2585 if (ah->config.intr_mitigation) {
2586 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2587 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2588 }
2589
2590 ath9k_hw_init_bb(ah, chan);
2591
2592 if (!ath9k_hw_init_cal(ah, chan))
2593 return -EIO;
2594
2595 rx_chainmask = ah->rxchainmask;
2596 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2597 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2598 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2599 }
2600
2601 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2602
2603 /*
2604 * For big endian systems turn on swapping for descriptors
2605 */
2606 if (AR_SREV_9100(ah)) {
2607 u32 mask;
2608 mask = REG_READ(ah, AR_CFG);
2609 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2610 ath_print(common, ATH_DBG_RESET,
2611 "CFG Byte Swap Set 0x%x\n", mask);
2612 } else {
2613 mask =
2614 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2615 REG_WRITE(ah, AR_CFG, mask);
2616 ath_print(common, ATH_DBG_RESET,
2617 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2618 }
2619 } else {
2620 /* Configure AR9271 target WLAN */
2621 if (AR_SREV_9271(ah))
2622 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2623 #ifdef __BIG_ENDIAN
2624 else
2625 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2626 #endif
2627 }
2628
2629 if (ah->btcoex_hw.enabled)
2630 ath9k_hw_btcoex_enable(ah);
2631
2632 return 0;
2633 }
2634 EXPORT_SYMBOL(ath9k_hw_reset);
2635
2636 /************************/
2637 /* Key Cache Management */
2638 /************************/
2639
2640 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2641 {
2642 u32 keyType;
2643
2644 if (entry >= ah->caps.keycache_size) {
2645 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2646 "keychache entry %u out of range\n", entry);
2647 return false;
2648 }
2649
2650 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2651
2652 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2653 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2654 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2655 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2656 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2657 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2658 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2659 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2660
2661 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2662 u16 micentry = entry + 64;
2663
2664 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2665 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2666 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2667 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2668
2669 }
2670
2671 return true;
2672 }
2673 EXPORT_SYMBOL(ath9k_hw_keyreset);
2674
2675 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2676 {
2677 u32 macHi, macLo;
2678
2679 if (entry >= ah->caps.keycache_size) {
2680 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2681 "keychache entry %u out of range\n", entry);
2682 return false;
2683 }
2684
2685 if (mac != NULL) {
2686 macHi = (mac[5] << 8) | mac[4];
2687 macLo = (mac[3] << 24) |
2688 (mac[2] << 16) |
2689 (mac[1] << 8) |
2690 mac[0];
2691 macLo >>= 1;
2692 macLo |= (macHi & 1) << 31;
2693 macHi >>= 1;
2694 } else {
2695 macLo = macHi = 0;
2696 }
2697 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2698 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2699
2700 return true;
2701 }
2702 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2703
2704 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2705 const struct ath9k_keyval *k,
2706 const u8 *mac)
2707 {
2708 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2709 struct ath_common *common = ath9k_hw_common(ah);
2710 u32 key0, key1, key2, key3, key4;
2711 u32 keyType;
2712
2713 if (entry >= pCap->keycache_size) {
2714 ath_print(common, ATH_DBG_FATAL,
2715 "keycache entry %u out of range\n", entry);
2716 return false;
2717 }
2718
2719 switch (k->kv_type) {
2720 case ATH9K_CIPHER_AES_OCB:
2721 keyType = AR_KEYTABLE_TYPE_AES;
2722 break;
2723 case ATH9K_CIPHER_AES_CCM:
2724 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2725 ath_print(common, ATH_DBG_ANY,
2726 "AES-CCM not supported by mac rev 0x%x\n",
2727 ah->hw_version.macRev);
2728 return false;
2729 }
2730 keyType = AR_KEYTABLE_TYPE_CCM;
2731 break;
2732 case ATH9K_CIPHER_TKIP:
2733 keyType = AR_KEYTABLE_TYPE_TKIP;
2734 if (ATH9K_IS_MIC_ENABLED(ah)
2735 && entry + 64 >= pCap->keycache_size) {
2736 ath_print(common, ATH_DBG_ANY,
2737 "entry %u inappropriate for TKIP\n", entry);
2738 return false;
2739 }
2740 break;
2741 case ATH9K_CIPHER_WEP:
2742 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2743 ath_print(common, ATH_DBG_ANY,
2744 "WEP key length %u too small\n", k->kv_len);
2745 return false;
2746 }
2747 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2748 keyType = AR_KEYTABLE_TYPE_40;
2749 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2750 keyType = AR_KEYTABLE_TYPE_104;
2751 else
2752 keyType = AR_KEYTABLE_TYPE_128;
2753 break;
2754 case ATH9K_CIPHER_CLR:
2755 keyType = AR_KEYTABLE_TYPE_CLR;
2756 break;
2757 default:
2758 ath_print(common, ATH_DBG_FATAL,
2759 "cipher %u not supported\n", k->kv_type);
2760 return false;
2761 }
2762
2763 key0 = get_unaligned_le32(k->kv_val + 0);
2764 key1 = get_unaligned_le16(k->kv_val + 4);
2765 key2 = get_unaligned_le32(k->kv_val + 6);
2766 key3 = get_unaligned_le16(k->kv_val + 10);
2767 key4 = get_unaligned_le32(k->kv_val + 12);
2768 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2769 key4 &= 0xff;
2770
2771 /*
2772 * Note: Key cache registers access special memory area that requires
2773 * two 32-bit writes to actually update the values in the internal
2774 * memory. Consequently, the exact order and pairs used here must be
2775 * maintained.
2776 */
2777
2778 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2779 u16 micentry = entry + 64;
2780
2781 /*
2782 * Write inverted key[47:0] first to avoid Michael MIC errors
2783 * on frames that could be sent or received at the same time.
2784 * The correct key will be written in the end once everything
2785 * else is ready.
2786 */
2787 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2788 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2789
2790 /* Write key[95:48] */
2791 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2792 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2793
2794 /* Write key[127:96] and key type */
2795 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2796 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2797
2798 /* Write MAC address for the entry */
2799 (void) ath9k_hw_keysetmac(ah, entry, mac);
2800
2801 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2802 /*
2803 * TKIP uses two key cache entries:
2804 * Michael MIC TX/RX keys in the same key cache entry
2805 * (idx = main index + 64):
2806 * key0 [31:0] = RX key [31:0]
2807 * key1 [15:0] = TX key [31:16]
2808 * key1 [31:16] = reserved
2809 * key2 [31:0] = RX key [63:32]
2810 * key3 [15:0] = TX key [15:0]
2811 * key3 [31:16] = reserved
2812 * key4 [31:0] = TX key [63:32]
2813 */
2814 u32 mic0, mic1, mic2, mic3, mic4;
2815
2816 mic0 = get_unaligned_le32(k->kv_mic + 0);
2817 mic2 = get_unaligned_le32(k->kv_mic + 4);
2818 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2819 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2820 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2821
2822 /* Write RX[31:0] and TX[31:16] */
2823 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2824 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2825
2826 /* Write RX[63:32] and TX[15:0] */
2827 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2828 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2829
2830 /* Write TX[63:32] and keyType(reserved) */
2831 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2832 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2833 AR_KEYTABLE_TYPE_CLR);
2834
2835 } else {
2836 /*
2837 * TKIP uses four key cache entries (two for group
2838 * keys):
2839 * Michael MIC TX/RX keys are in different key cache
2840 * entries (idx = main index + 64 for TX and
2841 * main index + 32 + 96 for RX):
2842 * key0 [31:0] = TX/RX MIC key [31:0]
2843 * key1 [31:0] = reserved
2844 * key2 [31:0] = TX/RX MIC key [63:32]
2845 * key3 [31:0] = reserved
2846 * key4 [31:0] = reserved
2847 *
2848 * Upper layer code will call this function separately
2849 * for TX and RX keys when these registers offsets are
2850 * used.
2851 */
2852 u32 mic0, mic2;
2853
2854 mic0 = get_unaligned_le32(k->kv_mic + 0);
2855 mic2 = get_unaligned_le32(k->kv_mic + 4);
2856
2857 /* Write MIC key[31:0] */
2858 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2859 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2860
2861 /* Write MIC key[63:32] */
2862 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2863 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2864
2865 /* Write TX[63:32] and keyType(reserved) */
2866 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2867 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2868 AR_KEYTABLE_TYPE_CLR);
2869 }
2870
2871 /* MAC address registers are reserved for the MIC entry */
2872 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2873 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2874
2875 /*
2876 * Write the correct (un-inverted) key[47:0] last to enable
2877 * TKIP now that all other registers are set with correct
2878 * values.
2879 */
2880 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2881 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2882 } else {
2883 /* Write key[47:0] */
2884 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2885 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2886
2887 /* Write key[95:48] */
2888 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2889 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2890
2891 /* Write key[127:96] and key type */
2892 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2893 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2894
2895 /* Write MAC address for the entry */
2896 (void) ath9k_hw_keysetmac(ah, entry, mac);
2897 }
2898
2899 return true;
2900 }
2901 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2902
2903 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2904 {
2905 if (entry < ah->caps.keycache_size) {
2906 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2907 if (val & AR_KEYTABLE_VALID)
2908 return true;
2909 }
2910 return false;
2911 }
2912 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2913
2914 /******************************/
2915 /* Power Management (Chipset) */
2916 /******************************/
2917
2918 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2919 {
2920 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2921 if (setChip) {
2922 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2923 AR_RTC_FORCE_WAKE_EN);
2924 if (!AR_SREV_9100(ah))
2925 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2926
2927 if(!AR_SREV_5416(ah))
2928 REG_CLR_BIT(ah, (AR_RTC_RESET),
2929 AR_RTC_RESET_EN);
2930 }
2931 }
2932
2933 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2934 {
2935 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2936 if (setChip) {
2937 struct ath9k_hw_capabilities *pCap = &ah->caps;
2938
2939 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2940 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2941 AR_RTC_FORCE_WAKE_ON_INT);
2942 } else {
2943 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2944 AR_RTC_FORCE_WAKE_EN);
2945 }
2946 }
2947 }
2948
2949 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2950 {
2951 u32 val;
2952 int i;
2953
2954 if (setChip) {
2955 if ((REG_READ(ah, AR_RTC_STATUS) &
2956 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2957 if (ath9k_hw_set_reset_reg(ah,
2958 ATH9K_RESET_POWER_ON) != true) {
2959 return false;
2960 }
2961 ath9k_hw_init_pll(ah, NULL);
2962 }
2963 if (AR_SREV_9100(ah))
2964 REG_SET_BIT(ah, AR_RTC_RESET,
2965 AR_RTC_RESET_EN);
2966
2967 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2968 AR_RTC_FORCE_WAKE_EN);
2969 udelay(50);
2970
2971 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2972 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2973 if (val == AR_RTC_STATUS_ON)
2974 break;
2975 udelay(50);
2976 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2977 AR_RTC_FORCE_WAKE_EN);
2978 }
2979 if (i == 0) {
2980 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2981 "Failed to wakeup in %uus\n",
2982 POWER_UP_TIME / 20);
2983 return false;
2984 }
2985 }
2986
2987 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2988
2989 return true;
2990 }
2991
2992 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2993 {
2994 struct ath_common *common = ath9k_hw_common(ah);
2995 int status = true, setChip = true;
2996 static const char *modes[] = {
2997 "AWAKE",
2998 "FULL-SLEEP",
2999 "NETWORK SLEEP",
3000 "UNDEFINED"
3001 };
3002
3003 if (ah->power_mode == mode)
3004 return status;
3005
3006 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
3007 modes[ah->power_mode], modes[mode]);
3008
3009 switch (mode) {
3010 case ATH9K_PM_AWAKE:
3011 status = ath9k_hw_set_power_awake(ah, setChip);
3012 break;
3013 case ATH9K_PM_FULL_SLEEP:
3014 ath9k_set_power_sleep(ah, setChip);
3015 ah->chip_fullsleep = true;
3016 break;
3017 case ATH9K_PM_NETWORK_SLEEP:
3018 ath9k_set_power_network_sleep(ah, setChip);
3019 break;
3020 default:
3021 ath_print(common, ATH_DBG_FATAL,
3022 "Unknown power mode %u\n", mode);
3023 return false;
3024 }
3025 ah->power_mode = mode;
3026
3027 return status;
3028 }
3029 EXPORT_SYMBOL(ath9k_hw_setpower);
3030
3031 /*
3032 * Helper for ASPM support.
3033 *
3034 * Disable PLL when in L0s as well as receiver clock when in L1.
3035 * This power saving option must be enabled through the SerDes.
3036 *
3037 * Programming the SerDes must go through the same 288 bit serial shift
3038 * register as the other analog registers. Hence the 9 writes.
3039 */
3040 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
3041 {
3042 u8 i;
3043 u32 val;
3044
3045 if (ah->is_pciexpress != true)
3046 return;
3047
3048 /* Do not touch SerDes registers */
3049 if (ah->config.pcie_powersave_enable == 2)
3050 return;
3051
3052 /* Nothing to do on restore for 11N */
3053 if (!restore) {
3054 if (AR_SREV_9280_20_OR_LATER(ah)) {
3055 /*
3056 * AR9280 2.0 or later chips use SerDes values from the
3057 * initvals.h initialized depending on chipset during
3058 * ath9k_hw_init()
3059 */
3060 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3061 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3062 INI_RA(&ah->iniPcieSerdes, i, 1));
3063 }
3064 } else if (AR_SREV_9280(ah) &&
3065 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3066 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3067 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3068
3069 /* RX shut off when elecidle is asserted */
3070 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3071 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3072 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3073
3074 /* Shut off CLKREQ active in L1 */
3075 if (ah->config.pcie_clock_req)
3076 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3077 else
3078 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3079
3080 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3081 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3082 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3083
3084 /* Load the new settings */
3085 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3086
3087 } else {
3088 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3089 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3090
3091 /* RX shut off when elecidle is asserted */
3092 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3093 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3094 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3095
3096 /*
3097 * Ignore ah->ah_config.pcie_clock_req setting for
3098 * pre-AR9280 11n
3099 */
3100 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3101
3102 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3103 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3104 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3105
3106 /* Load the new settings */
3107 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3108 }
3109
3110 udelay(1000);
3111
3112 /* set bit 19 to allow forcing of pcie core into L1 state */
3113 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3114
3115 /* Several PCIe massages to ensure proper behaviour */
3116 if (ah->config.pcie_waen) {
3117 val = ah->config.pcie_waen;
3118 if (!power_off)
3119 val &= (~AR_WA_D3_L1_DISABLE);
3120 } else {
3121 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3122 AR_SREV_9287(ah)) {
3123 val = AR9285_WA_DEFAULT;
3124 if (!power_off)
3125 val &= (~AR_WA_D3_L1_DISABLE);
3126 } else if (AR_SREV_9280(ah)) {
3127 /*
3128 * On AR9280 chips bit 22 of 0x4004 needs to be
3129 * set otherwise card may disappear.
3130 */
3131 val = AR9280_WA_DEFAULT;
3132 if (!power_off)
3133 val &= (~AR_WA_D3_L1_DISABLE);
3134 } else
3135 val = AR_WA_DEFAULT;
3136 }
3137
3138 REG_WRITE(ah, AR_WA, val);
3139 }
3140
3141 if (power_off) {
3142 /*
3143 * Set PCIe workaround bits
3144 * bit 14 in WA register (disable L1) should only
3145 * be set when device enters D3 and be cleared
3146 * when device comes back to D0.
3147 */
3148 if (ah->config.pcie_waen) {
3149 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3150 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3151 } else {
3152 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3153 AR_SREV_9287(ah)) &&
3154 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3155 (AR_SREV_9280(ah) &&
3156 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3157 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3158 }
3159 }
3160 }
3161 }
3162 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
3163
3164 /**********************/
3165 /* Interrupt Handling */
3166 /**********************/
3167
3168 bool ath9k_hw_intrpend(struct ath_hw *ah)
3169 {
3170 u32 host_isr;
3171
3172 if (AR_SREV_9100(ah))
3173 return true;
3174
3175 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3176 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3177 return true;
3178
3179 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3180 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3181 && (host_isr != AR_INTR_SPURIOUS))
3182 return true;
3183
3184 return false;
3185 }
3186 EXPORT_SYMBOL(ath9k_hw_intrpend);
3187
3188 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3189 {
3190 u32 isr = 0;
3191 u32 mask2 = 0;
3192 struct ath9k_hw_capabilities *pCap = &ah->caps;
3193 u32 sync_cause = 0;
3194 bool fatal_int = false;
3195 struct ath_common *common = ath9k_hw_common(ah);
3196
3197 if (!AR_SREV_9100(ah)) {
3198 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3199 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3200 == AR_RTC_STATUS_ON) {
3201 isr = REG_READ(ah, AR_ISR);
3202 }
3203 }
3204
3205 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3206 AR_INTR_SYNC_DEFAULT;
3207
3208 *masked = 0;
3209
3210 if (!isr && !sync_cause)
3211 return false;
3212 } else {
3213 *masked = 0;
3214 isr = REG_READ(ah, AR_ISR);
3215 }
3216
3217 if (isr) {
3218 if (isr & AR_ISR_BCNMISC) {
3219 u32 isr2;
3220 isr2 = REG_READ(ah, AR_ISR_S2);
3221 if (isr2 & AR_ISR_S2_TIM)
3222 mask2 |= ATH9K_INT_TIM;
3223 if (isr2 & AR_ISR_S2_DTIM)
3224 mask2 |= ATH9K_INT_DTIM;
3225 if (isr2 & AR_ISR_S2_DTIMSYNC)
3226 mask2 |= ATH9K_INT_DTIMSYNC;
3227 if (isr2 & (AR_ISR_S2_CABEND))
3228 mask2 |= ATH9K_INT_CABEND;
3229 if (isr2 & AR_ISR_S2_GTT)
3230 mask2 |= ATH9K_INT_GTT;
3231 if (isr2 & AR_ISR_S2_CST)
3232 mask2 |= ATH9K_INT_CST;
3233 if (isr2 & AR_ISR_S2_TSFOOR)
3234 mask2 |= ATH9K_INT_TSFOOR;
3235 }
3236
3237 isr = REG_READ(ah, AR_ISR_RAC);
3238 if (isr == 0xffffffff) {
3239 *masked = 0;
3240 return false;
3241 }
3242
3243 *masked = isr & ATH9K_INT_COMMON;
3244
3245 if (ah->config.intr_mitigation) {
3246 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3247 *masked |= ATH9K_INT_RX;
3248 }
3249
3250 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3251 *masked |= ATH9K_INT_RX;
3252 if (isr &
3253 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3254 AR_ISR_TXEOL)) {
3255 u32 s0_s, s1_s;
3256
3257 *masked |= ATH9K_INT_TX;
3258
3259 s0_s = REG_READ(ah, AR_ISR_S0_S);
3260 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3261 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3262
3263 s1_s = REG_READ(ah, AR_ISR_S1_S);
3264 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3265 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3266 }
3267
3268 if (isr & AR_ISR_RXORN) {
3269 ath_print(common, ATH_DBG_INTERRUPT,
3270 "receive FIFO overrun interrupt\n");
3271 }
3272
3273 if (!AR_SREV_9100(ah)) {
3274 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3275 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3276 if (isr5 & AR_ISR_S5_TIM_TIMER)
3277 *masked |= ATH9K_INT_TIM_TIMER;
3278 }
3279 }
3280
3281 *masked |= mask2;
3282 }
3283
3284 if (AR_SREV_9100(ah))
3285 return true;
3286
3287 if (isr & AR_ISR_GENTMR) {
3288 u32 s5_s;
3289
3290 s5_s = REG_READ(ah, AR_ISR_S5_S);
3291 if (isr & AR_ISR_GENTMR) {
3292 ah->intr_gen_timer_trigger =
3293 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3294
3295 ah->intr_gen_timer_thresh =
3296 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3297
3298 if (ah->intr_gen_timer_trigger)
3299 *masked |= ATH9K_INT_GENTIMER;
3300
3301 }
3302 }
3303
3304 if (sync_cause) {
3305 fatal_int =
3306 (sync_cause &
3307 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3308 ? true : false;
3309
3310 if (fatal_int) {
3311 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3312 ath_print(common, ATH_DBG_ANY,
3313 "received PCI FATAL interrupt\n");
3314 }
3315 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3316 ath_print(common, ATH_DBG_ANY,
3317 "received PCI PERR interrupt\n");
3318 }
3319 *masked |= ATH9K_INT_FATAL;
3320 }
3321 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3322 ath_print(common, ATH_DBG_INTERRUPT,
3323 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3324 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3325 REG_WRITE(ah, AR_RC, 0);
3326 *masked |= ATH9K_INT_FATAL;
3327 }
3328 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3329 ath_print(common, ATH_DBG_INTERRUPT,
3330 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3331 }
3332
3333 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3334 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3335 }
3336
3337 return true;
3338 }
3339 EXPORT_SYMBOL(ath9k_hw_getisr);
3340
3341 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3342 {
3343 u32 omask = ah->mask_reg;
3344 u32 mask, mask2;
3345 struct ath9k_hw_capabilities *pCap = &ah->caps;
3346 struct ath_common *common = ath9k_hw_common(ah);
3347
3348 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3349
3350 if (omask & ATH9K_INT_GLOBAL) {
3351 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3352 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3353 (void) REG_READ(ah, AR_IER);
3354 if (!AR_SREV_9100(ah)) {
3355 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3356 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3357
3358 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3359 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3360 }
3361 }
3362
3363 mask = ints & ATH9K_INT_COMMON;
3364 mask2 = 0;
3365
3366 if (ints & ATH9K_INT_TX) {
3367 if (ah->txok_interrupt_mask)
3368 mask |= AR_IMR_TXOK;
3369 if (ah->txdesc_interrupt_mask)
3370 mask |= AR_IMR_TXDESC;
3371 if (ah->txerr_interrupt_mask)
3372 mask |= AR_IMR_TXERR;
3373 if (ah->txeol_interrupt_mask)
3374 mask |= AR_IMR_TXEOL;
3375 }
3376 if (ints & ATH9K_INT_RX) {
3377 mask |= AR_IMR_RXERR;
3378 if (ah->config.intr_mitigation)
3379 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3380 else
3381 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3382 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3383 mask |= AR_IMR_GENTMR;
3384 }
3385
3386 if (ints & (ATH9K_INT_BMISC)) {
3387 mask |= AR_IMR_BCNMISC;
3388 if (ints & ATH9K_INT_TIM)
3389 mask2 |= AR_IMR_S2_TIM;
3390 if (ints & ATH9K_INT_DTIM)
3391 mask2 |= AR_IMR_S2_DTIM;
3392 if (ints & ATH9K_INT_DTIMSYNC)
3393 mask2 |= AR_IMR_S2_DTIMSYNC;
3394 if (ints & ATH9K_INT_CABEND)
3395 mask2 |= AR_IMR_S2_CABEND;
3396 if (ints & ATH9K_INT_TSFOOR)
3397 mask2 |= AR_IMR_S2_TSFOOR;
3398 }
3399
3400 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3401 mask |= AR_IMR_BCNMISC;
3402 if (ints & ATH9K_INT_GTT)
3403 mask2 |= AR_IMR_S2_GTT;
3404 if (ints & ATH9K_INT_CST)
3405 mask2 |= AR_IMR_S2_CST;
3406 }
3407
3408 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3409 REG_WRITE(ah, AR_IMR, mask);
3410 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3411 AR_IMR_S2_DTIM |
3412 AR_IMR_S2_DTIMSYNC |
3413 AR_IMR_S2_CABEND |
3414 AR_IMR_S2_CABTO |
3415 AR_IMR_S2_TSFOOR |
3416 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3417 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3418 ah->mask_reg = ints;
3419
3420 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3421 if (ints & ATH9K_INT_TIM_TIMER)
3422 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3423 else
3424 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3425 }
3426
3427 if (ints & ATH9K_INT_GLOBAL) {
3428 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3429 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3430 if (!AR_SREV_9100(ah)) {
3431 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3432 AR_INTR_MAC_IRQ);
3433 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3434
3435
3436 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3437 AR_INTR_SYNC_DEFAULT);
3438 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3439 AR_INTR_SYNC_DEFAULT);
3440 }
3441 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3442 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3443 }
3444
3445 return omask;
3446 }
3447 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
3448
3449 /*******************/
3450 /* Beacon Handling */
3451 /*******************/
3452
3453 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3454 {
3455 int flags = 0;
3456
3457 ah->beacon_interval = beacon_period;
3458
3459 switch (ah->opmode) {
3460 case NL80211_IFTYPE_STATION:
3461 case NL80211_IFTYPE_MONITOR:
3462 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3463 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3464 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3465 flags |= AR_TBTT_TIMER_EN;
3466 break;
3467 case NL80211_IFTYPE_ADHOC:
3468 case NL80211_IFTYPE_MESH_POINT:
3469 REG_SET_BIT(ah, AR_TXCFG,
3470 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3471 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3472 TU_TO_USEC(next_beacon +
3473 (ah->atim_window ? ah->
3474 atim_window : 1)));
3475 flags |= AR_NDP_TIMER_EN;
3476 case NL80211_IFTYPE_AP:
3477 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3478 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3479 TU_TO_USEC(next_beacon -
3480 ah->config.
3481 dma_beacon_response_time));
3482 REG_WRITE(ah, AR_NEXT_SWBA,
3483 TU_TO_USEC(next_beacon -
3484 ah->config.
3485 sw_beacon_response_time));
3486 flags |=
3487 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3488 break;
3489 default:
3490 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3491 "%s: unsupported opmode: %d\n",
3492 __func__, ah->opmode);
3493 return;
3494 break;
3495 }
3496
3497 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3498 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3499 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3500 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3501
3502 beacon_period &= ~ATH9K_BEACON_ENA;
3503 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3504 ath9k_hw_reset_tsf(ah);
3505 }
3506
3507 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3508 }
3509 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3510
3511 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3512 const struct ath9k_beacon_state *bs)
3513 {
3514 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3515 struct ath9k_hw_capabilities *pCap = &ah->caps;
3516 struct ath_common *common = ath9k_hw_common(ah);
3517
3518 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3519
3520 REG_WRITE(ah, AR_BEACON_PERIOD,
3521 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3522 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3523 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3524
3525 REG_RMW_FIELD(ah, AR_RSSI_THR,
3526 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3527
3528 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3529
3530 if (bs->bs_sleepduration > beaconintval)
3531 beaconintval = bs->bs_sleepduration;
3532
3533 dtimperiod = bs->bs_dtimperiod;
3534 if (bs->bs_sleepduration > dtimperiod)
3535 dtimperiod = bs->bs_sleepduration;
3536
3537 if (beaconintval == dtimperiod)
3538 nextTbtt = bs->bs_nextdtim;
3539 else
3540 nextTbtt = bs->bs_nexttbtt;
3541
3542 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3543 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3544 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3545 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3546
3547 REG_WRITE(ah, AR_NEXT_DTIM,
3548 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3549 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3550
3551 REG_WRITE(ah, AR_SLEEP1,
3552 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3553 | AR_SLEEP1_ASSUME_DTIM);
3554
3555 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3556 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3557 else
3558 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3559
3560 REG_WRITE(ah, AR_SLEEP2,
3561 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3562
3563 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3564 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3565
3566 REG_SET_BIT(ah, AR_TIMER_MODE,
3567 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3568 AR_DTIM_TIMER_EN);
3569
3570 /* TSF Out of Range Threshold */
3571 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3572 }
3573 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3574
3575 /*******************/
3576 /* HW Capabilities */
3577 /*******************/
3578
3579 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3580 {
3581 struct ath9k_hw_capabilities *pCap = &ah->caps;
3582 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3583 struct ath_common *common = ath9k_hw_common(ah);
3584 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3585
3586 u16 capField = 0, eeval;
3587
3588 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3589 regulatory->current_rd = eeval;
3590
3591 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3592 if (AR_SREV_9285_10_OR_LATER(ah))
3593 eeval |= AR9285_RDEXT_DEFAULT;
3594 regulatory->current_rd_ext = eeval;
3595
3596 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3597
3598 if (ah->opmode != NL80211_IFTYPE_AP &&
3599 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3600 if (regulatory->current_rd == 0x64 ||
3601 regulatory->current_rd == 0x65)
3602 regulatory->current_rd += 5;
3603 else if (regulatory->current_rd == 0x41)
3604 regulatory->current_rd = 0x43;
3605 ath_print(common, ATH_DBG_REGULATORY,
3606 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3607 }
3608
3609 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3610 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3611
3612 if (eeval & AR5416_OPFLAGS_11A) {
3613 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3614 if (ah->config.ht_enable) {
3615 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3616 set_bit(ATH9K_MODE_11NA_HT20,
3617 pCap->wireless_modes);
3618 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3619 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3620 pCap->wireless_modes);
3621 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3622 pCap->wireless_modes);
3623 }
3624 }
3625 }
3626
3627 if (eeval & AR5416_OPFLAGS_11G) {
3628 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3629 if (ah->config.ht_enable) {
3630 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3631 set_bit(ATH9K_MODE_11NG_HT20,
3632 pCap->wireless_modes);
3633 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3634 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3635 pCap->wireless_modes);
3636 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3637 pCap->wireless_modes);
3638 }
3639 }
3640 }
3641
3642 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3643 /*
3644 * For AR9271 we will temporarilly uses the rx chainmax as read from
3645 * the EEPROM.
3646 */
3647 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3648 !(eeval & AR5416_OPFLAGS_11A) &&
3649 !(AR_SREV_9271(ah)))
3650 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3651 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3652 else
3653 /* Use rx_chainmask from EEPROM. */
3654 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3655
3656 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3657 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3658
3659 pCap->low_2ghz_chan = 2312;
3660 pCap->high_2ghz_chan = 2732;
3661
3662 pCap->low_5ghz_chan = 4920;
3663 pCap->high_5ghz_chan = 6100;
3664
3665 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3666 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3667 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3668
3669 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3670 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3671 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3672
3673 if (ah->config.ht_enable)
3674 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3675 else
3676 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3677
3678 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3679 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3680 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3681 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3682
3683 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3684 pCap->total_queues =
3685 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3686 else
3687 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3688
3689 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3690 pCap->keycache_size =
3691 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3692 else
3693 pCap->keycache_size = AR_KEYTABLE_SIZE;
3694
3695 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3696 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3697
3698 if (AR_SREV_9285_10_OR_LATER(ah))
3699 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3700 else if (AR_SREV_9280_10_OR_LATER(ah))
3701 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3702 else
3703 pCap->num_gpio_pins = AR_NUM_GPIO;
3704
3705 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3706 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3707 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3708 } else {
3709 pCap->rts_aggr_limit = (8 * 1024);
3710 }
3711
3712 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3713
3714 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3715 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3716 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3717 ah->rfkill_gpio =
3718 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3719 ah->rfkill_polarity =
3720 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3721
3722 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3723 }
3724 #endif
3725
3726 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3727
3728 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3729 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3730 else
3731 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3732
3733 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3734 pCap->reg_cap =
3735 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3736 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3737 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3738 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3739 } else {
3740 pCap->reg_cap =
3741 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3742 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3743 }
3744
3745 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3746 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3747 AR_SREV_5416(ah))
3748 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3749
3750 pCap->num_antcfg_5ghz =
3751 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3752 pCap->num_antcfg_2ghz =
3753 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3754
3755 if (AR_SREV_9280_10_OR_LATER(ah) &&
3756 ath9k_hw_btcoex_supported(ah)) {
3757 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3758 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3759
3760 if (AR_SREV_9285(ah)) {
3761 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3762 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3763 } else {
3764 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3765 }
3766 } else {
3767 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3768 }
3769 }
3770
3771 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3772 u32 capability, u32 *result)
3773 {
3774 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3775 switch (type) {
3776 case ATH9K_CAP_CIPHER:
3777 switch (capability) {
3778 case ATH9K_CIPHER_AES_CCM:
3779 case ATH9K_CIPHER_AES_OCB:
3780 case ATH9K_CIPHER_TKIP:
3781 case ATH9K_CIPHER_WEP:
3782 case ATH9K_CIPHER_MIC:
3783 case ATH9K_CIPHER_CLR:
3784 return true;
3785 default:
3786 return false;
3787 }
3788 case ATH9K_CAP_TKIP_MIC:
3789 switch (capability) {
3790 case 0:
3791 return true;
3792 case 1:
3793 return (ah->sta_id1_defaults &
3794 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3795 false;
3796 }
3797 case ATH9K_CAP_TKIP_SPLIT:
3798 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3799 false : true;
3800 case ATH9K_CAP_DIVERSITY:
3801 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3802 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3803 true : false;
3804 case ATH9K_CAP_MCAST_KEYSRCH:
3805 switch (capability) {
3806 case 0:
3807 return true;
3808 case 1:
3809 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3810 return false;
3811 } else {
3812 return (ah->sta_id1_defaults &
3813 AR_STA_ID1_MCAST_KSRCH) ? true :
3814 false;
3815 }
3816 }
3817 return false;
3818 case ATH9K_CAP_TXPOW:
3819 switch (capability) {
3820 case 0:
3821 return 0;
3822 case 1:
3823 *result = regulatory->power_limit;
3824 return 0;
3825 case 2:
3826 *result = regulatory->max_power_level;
3827 return 0;
3828 case 3:
3829 *result = regulatory->tp_scale;
3830 return 0;
3831 }
3832 return false;
3833 case ATH9K_CAP_DS:
3834 return (AR_SREV_9280_20_OR_LATER(ah) &&
3835 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3836 ? false : true;
3837 default:
3838 return false;
3839 }
3840 }
3841 EXPORT_SYMBOL(ath9k_hw_getcapability);
3842
3843 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3844 u32 capability, u32 setting, int *status)
3845 {
3846 u32 v;
3847
3848 switch (type) {
3849 case ATH9K_CAP_TKIP_MIC:
3850 if (setting)
3851 ah->sta_id1_defaults |=
3852 AR_STA_ID1_CRPT_MIC_ENABLE;
3853 else
3854 ah->sta_id1_defaults &=
3855 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3856 return true;
3857 case ATH9K_CAP_DIVERSITY:
3858 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3859 if (setting)
3860 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3861 else
3862 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3863 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3864 return true;
3865 case ATH9K_CAP_MCAST_KEYSRCH:
3866 if (setting)
3867 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3868 else
3869 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3870 return true;
3871 default:
3872 return false;
3873 }
3874 }
3875 EXPORT_SYMBOL(ath9k_hw_setcapability);
3876
3877 /****************************/
3878 /* GPIO / RFKILL / Antennae */
3879 /****************************/
3880
3881 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3882 u32 gpio, u32 type)
3883 {
3884 int addr;
3885 u32 gpio_shift, tmp;
3886
3887 if (gpio > 11)
3888 addr = AR_GPIO_OUTPUT_MUX3;
3889 else if (gpio > 5)
3890 addr = AR_GPIO_OUTPUT_MUX2;
3891 else
3892 addr = AR_GPIO_OUTPUT_MUX1;
3893
3894 gpio_shift = (gpio % 6) * 5;
3895
3896 if (AR_SREV_9280_20_OR_LATER(ah)
3897 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3898 REG_RMW(ah, addr, (type << gpio_shift),
3899 (0x1f << gpio_shift));
3900 } else {
3901 tmp = REG_READ(ah, addr);
3902 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3903 tmp &= ~(0x1f << gpio_shift);
3904 tmp |= (type << gpio_shift);
3905 REG_WRITE(ah, addr, tmp);
3906 }
3907 }
3908
3909 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3910 {
3911 u32 gpio_shift;
3912
3913 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3914
3915 gpio_shift = gpio << 1;
3916
3917 REG_RMW(ah,
3918 AR_GPIO_OE_OUT,
3919 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3920 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3921 }
3922 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3923
3924 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3925 {
3926 #define MS_REG_READ(x, y) \
3927 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3928
3929 if (gpio >= ah->caps.num_gpio_pins)
3930 return 0xffffffff;
3931
3932 if (AR_SREV_9287_10_OR_LATER(ah))
3933 return MS_REG_READ(AR9287, gpio) != 0;
3934 else if (AR_SREV_9285_10_OR_LATER(ah))
3935 return MS_REG_READ(AR9285, gpio) != 0;
3936 else if (AR_SREV_9280_10_OR_LATER(ah))
3937 return MS_REG_READ(AR928X, gpio) != 0;
3938 else
3939 return MS_REG_READ(AR, gpio) != 0;
3940 }
3941 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3942
3943 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3944 u32 ah_signal_type)
3945 {
3946 u32 gpio_shift;
3947
3948 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3949
3950 gpio_shift = 2 * gpio;
3951
3952 REG_RMW(ah,
3953 AR_GPIO_OE_OUT,
3954 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3955 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3956 }
3957 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3958
3959 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3960 {
3961 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3962 AR_GPIO_BIT(gpio));
3963 }
3964 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3965
3966 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3967 {
3968 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3969 }
3970 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3971
3972 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3973 {
3974 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3975 }
3976 EXPORT_SYMBOL(ath9k_hw_setantenna);
3977
3978 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3979 enum ath9k_ant_setting settings,
3980 struct ath9k_channel *chan,
3981 u8 *tx_chainmask,
3982 u8 *rx_chainmask,
3983 u8 *antenna_cfgd)
3984 {
3985 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3986
3987 if (AR_SREV_9280(ah)) {
3988 if (!tx_chainmask_cfg) {
3989
3990 tx_chainmask_cfg = *tx_chainmask;
3991 rx_chainmask_cfg = *rx_chainmask;
3992 }
3993
3994 switch (settings) {
3995 case ATH9K_ANT_FIXED_A:
3996 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3997 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3998 *antenna_cfgd = true;
3999 break;
4000 case ATH9K_ANT_FIXED_B:
4001 if (ah->caps.tx_chainmask >
4002 ATH9K_ANTENNA1_CHAINMASK) {
4003 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
4004 }
4005 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
4006 *antenna_cfgd = true;
4007 break;
4008 case ATH9K_ANT_VARIABLE:
4009 *tx_chainmask = tx_chainmask_cfg;
4010 *rx_chainmask = rx_chainmask_cfg;
4011 *antenna_cfgd = true;
4012 break;
4013 default:
4014 break;
4015 }
4016 } else {
4017 ah->config.diversity_control = settings;
4018 }
4019
4020 return true;
4021 }
4022
4023 /*********************/
4024 /* General Operation */
4025 /*********************/
4026
4027 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
4028 {
4029 u32 bits = REG_READ(ah, AR_RX_FILTER);
4030 u32 phybits = REG_READ(ah, AR_PHY_ERR);
4031
4032 if (phybits & AR_PHY_ERR_RADAR)
4033 bits |= ATH9K_RX_FILTER_PHYRADAR;
4034 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
4035 bits |= ATH9K_RX_FILTER_PHYERR;
4036
4037 return bits;
4038 }
4039 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
4040
4041 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4042 {
4043 u32 phybits;
4044
4045 REG_WRITE(ah, AR_RX_FILTER, bits);
4046
4047 phybits = 0;
4048 if (bits & ATH9K_RX_FILTER_PHYRADAR)
4049 phybits |= AR_PHY_ERR_RADAR;
4050 if (bits & ATH9K_RX_FILTER_PHYERR)
4051 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
4052 REG_WRITE(ah, AR_PHY_ERR, phybits);
4053
4054 if (phybits)
4055 REG_WRITE(ah, AR_RXCFG,
4056 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
4057 else
4058 REG_WRITE(ah, AR_RXCFG,
4059 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
4060 }
4061 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
4062
4063 bool ath9k_hw_phy_disable(struct ath_hw *ah)
4064 {
4065 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
4066 return false;
4067
4068 ath9k_hw_init_pll(ah, NULL);
4069 return true;
4070 }
4071 EXPORT_SYMBOL(ath9k_hw_phy_disable);
4072
4073 bool ath9k_hw_disable(struct ath_hw *ah)
4074 {
4075 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
4076 return false;
4077
4078 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
4079 return false;
4080
4081 ath9k_hw_init_pll(ah, NULL);
4082 return true;
4083 }
4084 EXPORT_SYMBOL(ath9k_hw_disable);
4085
4086 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4087 {
4088 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4089 struct ath9k_channel *chan = ah->curchan;
4090 struct ieee80211_channel *channel = chan->chan;
4091
4092 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
4093
4094 ah->eep_ops->set_txpower(ah, chan,
4095 ath9k_regd_get_ctl(regulatory, chan),
4096 channel->max_antenna_gain * 2,
4097 channel->max_power * 2,
4098 min((u32) MAX_RATE_POWER,
4099 (u32) regulatory->power_limit));
4100 }
4101 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
4102
4103 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
4104 {
4105 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4106 }
4107 EXPORT_SYMBOL(ath9k_hw_setmac);
4108
4109 void ath9k_hw_setopmode(struct ath_hw *ah)
4110 {
4111 ath9k_hw_set_operating_mode(ah, ah->opmode);
4112 }
4113 EXPORT_SYMBOL(ath9k_hw_setopmode);
4114
4115 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4116 {
4117 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4118 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4119 }
4120 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
4121
4122 void ath9k_hw_write_associd(struct ath_hw *ah)
4123 {
4124 struct ath_common *common = ath9k_hw_common(ah);
4125
4126 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4127 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4128 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4129 }
4130 EXPORT_SYMBOL(ath9k_hw_write_associd);
4131
4132 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4133 {
4134 u64 tsf;
4135
4136 tsf = REG_READ(ah, AR_TSF_U32);
4137 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4138
4139 return tsf;
4140 }
4141 EXPORT_SYMBOL(ath9k_hw_gettsf64);
4142
4143 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4144 {
4145 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4146 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4147 }
4148 EXPORT_SYMBOL(ath9k_hw_settsf64);
4149
4150 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4151 {
4152 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4153 AH_TSF_WRITE_TIMEOUT))
4154 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4155 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4156
4157 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4158 }
4159 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
4160
4161 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4162 {
4163 if (setting)
4164 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4165 else
4166 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4167 }
4168 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
4169
4170 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4171 {
4172 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4173 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4174 "bad slot time %u\n", us);
4175 ah->slottime = (u32) -1;
4176 return false;
4177 } else {
4178 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4179 ah->slottime = us;
4180 return true;
4181 }
4182 }
4183 EXPORT_SYMBOL(ath9k_hw_setslottime);
4184
4185 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
4186 {
4187 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
4188 u32 macmode;
4189
4190 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
4191 macmode = AR_2040_JOINED_RX_CLEAR;
4192 else
4193 macmode = 0;
4194
4195 REG_WRITE(ah, AR_2040_MODE, macmode);
4196 }
4197
4198 /* HW Generic timers configuration */
4199
4200 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4201 {
4202 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4203 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4204 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4205 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4206 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4207 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4208 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4209 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4210 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4211 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4212 AR_NDP2_TIMER_MODE, 0x0002},
4213 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4214 AR_NDP2_TIMER_MODE, 0x0004},
4215 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4216 AR_NDP2_TIMER_MODE, 0x0008},
4217 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4218 AR_NDP2_TIMER_MODE, 0x0010},
4219 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4220 AR_NDP2_TIMER_MODE, 0x0020},
4221 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4222 AR_NDP2_TIMER_MODE, 0x0040},
4223 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4224 AR_NDP2_TIMER_MODE, 0x0080}
4225 };
4226
4227 /* HW generic timer primitives */
4228
4229 /* compute and clear index of rightmost 1 */
4230 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4231 {
4232 u32 b;
4233
4234 b = *mask;
4235 b &= (0-b);
4236 *mask &= ~b;
4237 b *= debruijn32;
4238 b >>= 27;
4239
4240 return timer_table->gen_timer_index[b];
4241 }
4242
4243 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4244 {
4245 return REG_READ(ah, AR_TSF_L32);
4246 }
4247 EXPORT_SYMBOL(ath9k_hw_gettsf32);
4248
4249 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4250 void (*trigger)(void *),
4251 void (*overflow)(void *),
4252 void *arg,
4253 u8 timer_index)
4254 {
4255 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4256 struct ath_gen_timer *timer;
4257
4258 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4259
4260 if (timer == NULL) {
4261 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4262 "Failed to allocate memory"
4263 "for hw timer[%d]\n", timer_index);
4264 return NULL;
4265 }
4266
4267 /* allocate a hardware generic timer slot */
4268 timer_table->timers[timer_index] = timer;
4269 timer->index = timer_index;
4270 timer->trigger = trigger;
4271 timer->overflow = overflow;
4272 timer->arg = arg;
4273
4274 return timer;
4275 }
4276 EXPORT_SYMBOL(ath_gen_timer_alloc);
4277
4278 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4279 struct ath_gen_timer *timer,
4280 u32 timer_next,
4281 u32 timer_period)
4282 {
4283 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4284 u32 tsf;
4285
4286 BUG_ON(!timer_period);
4287
4288 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4289
4290 tsf = ath9k_hw_gettsf32(ah);
4291
4292 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4293 "curent tsf %x period %x"
4294 "timer_next %x\n", tsf, timer_period, timer_next);
4295
4296 /*
4297 * Pull timer_next forward if the current TSF already passed it
4298 * because of software latency
4299 */
4300 if (timer_next < tsf)
4301 timer_next = tsf + timer_period;
4302
4303 /*
4304 * Program generic timer registers
4305 */
4306 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4307 timer_next);
4308 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4309 timer_period);
4310 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4311 gen_tmr_configuration[timer->index].mode_mask);
4312
4313 /* Enable both trigger and thresh interrupt masks */
4314 REG_SET_BIT(ah, AR_IMR_S5,
4315 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4316 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4317 }
4318 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
4319
4320 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4321 {
4322 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4323
4324 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4325 (timer->index >= ATH_MAX_GEN_TIMER)) {
4326 return;
4327 }
4328
4329 /* Clear generic timer enable bits. */
4330 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4331 gen_tmr_configuration[timer->index].mode_mask);
4332
4333 /* Disable both trigger and thresh interrupt masks */
4334 REG_CLR_BIT(ah, AR_IMR_S5,
4335 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4336 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4337
4338 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4339 }
4340 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
4341
4342 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4343 {
4344 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4345
4346 /* free the hardware generic timer slot */
4347 timer_table->timers[timer->index] = NULL;
4348 kfree(timer);
4349 }
4350 EXPORT_SYMBOL(ath_gen_timer_free);
4351
4352 /*
4353 * Generic Timer Interrupts handling
4354 */
4355 void ath_gen_timer_isr(struct ath_hw *ah)
4356 {
4357 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4358 struct ath_gen_timer *timer;
4359 struct ath_common *common = ath9k_hw_common(ah);
4360 u32 trigger_mask, thresh_mask, index;
4361
4362 /* get hardware generic timer interrupt status */
4363 trigger_mask = ah->intr_gen_timer_trigger;
4364 thresh_mask = ah->intr_gen_timer_thresh;
4365 trigger_mask &= timer_table->timer_mask.val;
4366 thresh_mask &= timer_table->timer_mask.val;
4367
4368 trigger_mask &= ~thresh_mask;
4369
4370 while (thresh_mask) {
4371 index = rightmost_index(timer_table, &thresh_mask);
4372 timer = timer_table->timers[index];
4373 BUG_ON(!timer);
4374 ath_print(common, ATH_DBG_HWTIMER,
4375 "TSF overflow for Gen timer %d\n", index);
4376 timer->overflow(timer->arg);
4377 }
4378
4379 while (trigger_mask) {
4380 index = rightmost_index(timer_table, &trigger_mask);
4381 timer = timer_table->timers[index];
4382 BUG_ON(!timer);
4383 ath_print(common, ATH_DBG_HWTIMER,
4384 "Gen timer[%d] trigger\n", index);
4385 timer->trigger(timer->arg);
4386 }
4387 }
4388 EXPORT_SYMBOL(ath_gen_timer_isr);
4389
4390 static struct {
4391 u32 version;
4392 const char * name;
4393 } ath_mac_bb_names[] = {
4394 /* Devices with external radios */
4395 { AR_SREV_VERSION_5416_PCI, "5416" },
4396 { AR_SREV_VERSION_5416_PCIE, "5418" },
4397 { AR_SREV_VERSION_9100, "9100" },
4398 { AR_SREV_VERSION_9160, "9160" },
4399 /* Single-chip solutions */
4400 { AR_SREV_VERSION_9280, "9280" },
4401 { AR_SREV_VERSION_9285, "9285" },
4402 { AR_SREV_VERSION_9287, "9287" },
4403 { AR_SREV_VERSION_9271, "9271" },
4404 };
4405
4406 /* For devices with external radios */
4407 static struct {
4408 u16 version;
4409 const char * name;
4410 } ath_rf_names[] = {
4411 { 0, "5133" },
4412 { AR_RAD5133_SREV_MAJOR, "5133" },
4413 { AR_RAD5122_SREV_MAJOR, "5122" },
4414 { AR_RAD2133_SREV_MAJOR, "2133" },
4415 { AR_RAD2122_SREV_MAJOR, "2122" }
4416 };
4417
4418 /*
4419 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
4420 */
4421 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
4422 {
4423 int i;
4424
4425 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
4426 if (ath_mac_bb_names[i].version == mac_bb_version) {
4427 return ath_mac_bb_names[i].name;
4428 }
4429 }
4430
4431 return "????";
4432 }
4433
4434 /*
4435 * Return the RF name. "????" is returned if the RF is unknown.
4436 * Used for devices with external radios.
4437 */
4438 static const char *ath9k_hw_rf_name(u16 rf_version)
4439 {
4440 int i;
4441
4442 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
4443 if (ath_rf_names[i].version == rf_version) {
4444 return ath_rf_names[i].name;
4445 }
4446 }
4447
4448 return "????";
4449 }
4450
4451 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
4452 {
4453 int used;
4454
4455 /* chipsets >= AR9280 are single-chip */
4456 if (AR_SREV_9280_10_OR_LATER(ah)) {
4457 used = snprintf(hw_name, len,
4458 "Atheros AR%s Rev:%x",
4459 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4460 ah->hw_version.macRev);
4461 }
4462 else {
4463 used = snprintf(hw_name, len,
4464 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
4465 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4466 ah->hw_version.macRev,
4467 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
4468 AR_RADIO_SREV_MAJOR)),
4469 ah->hw_version.phyRev);
4470 }
4471
4472 hw_name[used] = '\0';
4473 }
4474 EXPORT_SYMBOL(ath9k_hw_name);
Linux with added FPC-III support