arch/arc/boot/dts/axc001.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   4  */
   5
   6 /*
   7  * Device tree for AXC001 770D/EM6/AS221 CPU card
   8  * Note that this file only supports the 770D CPU
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 / {
  14         compatible = "snps,arc";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpu_card {
  19                 compatible = "simple-bus";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22
  23                 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
  24
  25                 core_clk: core_clk {
  26                         #clock-cells = <0>;
  27                         compatible = "fixed-clock";
  28                         clock-frequency = <750000000>;
  29                 };
  30
  31                 input_clk: input-clk {
  32                         #clock-cells = <0>;
  33                         compatible = "fixed-clock";
  34                         clock-frequency = <33333333>;
  35                 };
  36
  37                 core_intc: arc700-intc@cpu {
  38                         compatible = "snps,arc700-intc";
  39                         interrupt-controller;
  40                         #interrupt-cells = <1>;
  41                 };
  42
  43                 /*
  44                  * this GPIO block ORs all interrupts on CPU card (creg,..)
  45                  * to uplink only 1 IRQ to ARC core intc
  46                  */
  47                 dw-apb-gpio@2000 {
  48                         compatible = "snps,dw-apb-gpio";
  49                         reg = < 0x2000 0x80 >;
  50                         #address-cells = <1>;
  51                         #size-cells = <0>;
  52
  53                         ictl_intc: gpio-controller@0 {
  54                                 compatible = "snps,dw-apb-gpio-port";
  55                                 gpio-controller;
  56                                 #gpio-cells = <2>;
  57                                 snps,nr-gpios = <30>;
  58                                 reg = <0>;
  59                                 interrupt-controller;
  60                                 #interrupt-cells = <2>;
  61                                 interrupt-parent = <&core_intc>;
  62                                 interrupts = <15>;
  63                         };
  64                 };
  65
  66                 debug_uart: dw-apb-uart@5000 {
  67                         compatible = "snps,dw-apb-uart";
  68                         reg = <0x5000 0x100>;
  69                         clock-frequency = <33333000>;
  70                         interrupt-parent = <&ictl_intc>;
  71                         interrupts = <19 4>;
  72                         baud = <115200>;
  73                         reg-shift = <2>;
  74                         reg-io-width = <4>;
  75                 };
  76
  77                 arcpct0: pct {
  78                         compatible = "snps,arc700-pct";
  79                 };
  80         };
  81
  82         /*
  83          * This INTC is actually connected to DW APB GPIO
  84          * which acts as a wire between MB INTC and CPU INTC.
  85          * GPIO INTC is configured in platform init code
  86          * and here we mimic direct connection from MB INTC to
  87          * CPU INTC, thus we set "interrupts = <7>" instead of
  88          * "interrupts = <12>"
  89          *
  90          * This intc actually resides on MB, but we move it here to
  91          * avoid duplicating the MB dtsi file given that IRQ from
  92          * this intc to cpu intc are different for axs101 and axs103
  93          */
  94         mb_intc: dw-apb-ictl@e0012000 {
  95                 #interrupt-cells = <1>;
  96                 compatible = "snps,dw-apb-ictl";
  97                 reg = < 0x0 0xe0012000 0x0 0x200 >;
  98                 interrupt-controller;
  99                 interrupt-parent = <&core_intc>;
 100                 interrupts = < 7 >;
 101         };
 102
 103         memory {
 104                 device_type = "memory";
 105                 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
 106                 reg = <0x0 0x80000000 0x0 0x1b000000>;  /* (512 - 32) MiB */
 107         };
 108
 109         reserved-memory {
 110                 #address-cells = <2>;
 111                 #size-cells = <2>;
 112                 ranges;
 113                 /*
 114                  * We just move frame buffer area to the very end of
 115                  * available DDR. And even though in case of ARC770 there's
 116                  * no strict requirement for a frame-buffer to be in any
 117                  * particular location it allows us to use the same
 118                  * base board's DT node for ARC PGU as for ARc HS38.
 119                  */
 120                 frame_buffer: frame_buffer@9e000000 {
 121                         compatible = "shared-dma-pool";
 122                         reg = <0x0 0x9e000000 0x0 0x2000000>;
 123                         no-map;
 124                 };
 125         };
 126 };