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drm/panfrost: Move gpu_{write, read}() macros to panfrost_regs.h
[linux/fpc-iii.git] / drivers / platform / x86 / intel_pmc_core.c
blob1d902230ba611535c5ce0d85a6ac7b7b05e21040
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel Core SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 * All Rights Reserved.
7 *
8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com>
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14 #include <linux/acpi.h>
15 #include <linux/bitfield.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/dmi.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/suspend.h>
24 #include <linux/uaccess.h>
25
26 #include <asm/cpu_device_id.h>
27 #include <asm/intel-family.h>
28 #include <asm/msr.h>
29
30 #include "intel_pmc_core.h"
31
32 static struct pmc_dev pmc;
33
34 /* PKGC MSRs are common across Intel Core SoCs */
35 static const struct pmc_bit_map msr_map[] = {
36 {"Package C2", MSR_PKG_C2_RESIDENCY},
37 {"Package C3", MSR_PKG_C3_RESIDENCY},
38 {"Package C6", MSR_PKG_C6_RESIDENCY},
39 {"Package C7", MSR_PKG_C7_RESIDENCY},
40 {"Package C8", MSR_PKG_C8_RESIDENCY},
41 {"Package C9", MSR_PKG_C9_RESIDENCY},
42 {"Package C10", MSR_PKG_C10_RESIDENCY},
43 {}
44 };
45
46 static const struct pmc_bit_map spt_pll_map[] = {
47 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
48 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
49 {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
50 {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
51 {},
52 };
53
54 static const struct pmc_bit_map spt_mphy_map[] = {
55 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
56 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
57 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
58 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
59 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
60 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
61 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
62 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
63 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
64 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
65 {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
66 {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
67 {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
68 {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
69 {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
70 {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
71 {},
72 };
73
74 static const struct pmc_bit_map spt_pfear_map[] = {
75 {"PMC", SPT_PMC_BIT_PMC},
76 {"OPI-DMI", SPT_PMC_BIT_OPI},
77 {"SPI / eSPI", SPT_PMC_BIT_SPI},
78 {"XHCI", SPT_PMC_BIT_XHCI},
79 {"SPA", SPT_PMC_BIT_SPA},
80 {"SPB", SPT_PMC_BIT_SPB},
81 {"SPC", SPT_PMC_BIT_SPC},
82 {"GBE", SPT_PMC_BIT_GBE},
83 {"SATA", SPT_PMC_BIT_SATA},
84 {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
85 {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
86 {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
87 {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
88 {"RSVD", SPT_PMC_BIT_RSVD_0B},
89 {"LPSS", SPT_PMC_BIT_LPSS},
90 {"LPC", SPT_PMC_BIT_LPC},
91 {"SMB", SPT_PMC_BIT_SMB},
92 {"ISH", SPT_PMC_BIT_ISH},
93 {"P2SB", SPT_PMC_BIT_P2SB},
94 {"DFX", SPT_PMC_BIT_DFX},
95 {"SCC", SPT_PMC_BIT_SCC},
96 {"RSVD", SPT_PMC_BIT_RSVD_0C},
97 {"FUSE", SPT_PMC_BIT_FUSE},
98 {"CAMERA", SPT_PMC_BIT_CAMREA},
99 {"RSVD", SPT_PMC_BIT_RSVD_0D},
100 {"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
101 {"EXI", SPT_PMC_BIT_EXI},
102 {"CSE", SPT_PMC_BIT_CSE},
103 {"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
104 {"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
105 {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
106 {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
107 {"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
108 {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
109 {"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
110 {"RSVD", SPT_PMC_BIT_RSVD_1A},
111 {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
112 {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
113 {"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
114 {"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
115 {},
116 };
117
118 static const struct pmc_bit_map spt_ltr_show_map[] = {
119 {"SOUTHPORT_A", SPT_PMC_LTR_SPA},
120 {"SOUTHPORT_B", SPT_PMC_LTR_SPB},
121 {"SATA", SPT_PMC_LTR_SATA},
122 {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
123 {"XHCI", SPT_PMC_LTR_XHCI},
124 {"Reserved", SPT_PMC_LTR_RESERVED},
125 {"ME", SPT_PMC_LTR_ME},
126 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
127 {"EVA", SPT_PMC_LTR_EVA},
128 {"SOUTHPORT_C", SPT_PMC_LTR_SPC},
129 {"HD_AUDIO", SPT_PMC_LTR_AZ},
130 {"LPSS", SPT_PMC_LTR_LPSS},
131 {"SOUTHPORT_D", SPT_PMC_LTR_SPD},
132 {"SOUTHPORT_E", SPT_PMC_LTR_SPE},
133 {"CAMERA", SPT_PMC_LTR_CAM},
134 {"ESPI", SPT_PMC_LTR_ESPI},
135 {"SCC", SPT_PMC_LTR_SCC},
136 {"ISH", SPT_PMC_LTR_ISH},
137 /* Below two cannot be used for LTR_IGNORE */
138 {"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
139 {"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
140 {}
141 };
142
143 static const struct pmc_reg_map spt_reg_map = {
144 .pfear_sts = spt_pfear_map,
145 .mphy_sts = spt_mphy_map,
146 .pll_sts = spt_pll_map,
147 .ltr_show_sts = spt_ltr_show_map,
148 .msr_sts = msr_map,
149 .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
150 .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
151 .regmap_length = SPT_PMC_MMIO_REG_LEN,
152 .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
153 .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
154 .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
155 .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
156 .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
157 .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
158 };
159
160 /* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
161 static const struct pmc_bit_map cnp_pfear_map[] = {
162 {"PMC", BIT(0)},
163 {"OPI-DMI", BIT(1)},
164 {"SPI/eSPI", BIT(2)},
165 {"XHCI", BIT(3)},
166 {"SPA", BIT(4)},
167 {"SPB", BIT(5)},
168 {"SPC", BIT(6)},
169 {"GBE", BIT(7)},
170
171 {"SATA", BIT(0)},
172 {"HDA_PGD0", BIT(1)},
173 {"HDA_PGD1", BIT(2)},
174 {"HDA_PGD2", BIT(3)},
175 {"HDA_PGD3", BIT(4)},
176 {"SPD", BIT(5)},
177 {"LPSS", BIT(6)},
178 {"LPC", BIT(7)},
179
180 {"SMB", BIT(0)},
181 {"ISH", BIT(1)},
182 {"P2SB", BIT(2)},
183 {"NPK_VNN", BIT(3)},
184 {"SDX", BIT(4)},
185 {"SPE", BIT(5)},
186 {"Fuse", BIT(6)},
187 /* Reserved for Cannonlake but valid for Icelake */
188 {"SBR8", BIT(7)},
189
190 {"CSME_FSC", BIT(0)},
191 {"USB3_OTG", BIT(1)},
192 {"EXI", BIT(2)},
193 {"CSE", BIT(3)},
194 {"CSME_KVM", BIT(4)},
195 {"CSME_PMT", BIT(5)},
196 {"CSME_CLINK", BIT(6)},
197 {"CSME_PTIO", BIT(7)},
198
199 {"CSME_USBR", BIT(0)},
200 {"CSME_SUSRAM", BIT(1)},
201 {"CSME_SMT1", BIT(2)},
202 {"CSME_SMT4", BIT(3)},
203 {"CSME_SMS2", BIT(4)},
204 {"CSME_SMS1", BIT(5)},
205 {"CSME_RTC", BIT(6)},
206 {"CSME_PSF", BIT(7)},
207
208 {"SBR0", BIT(0)},
209 {"SBR1", BIT(1)},
210 {"SBR2", BIT(2)},
211 {"SBR3", BIT(3)},
212 {"SBR4", BIT(4)},
213 {"SBR5", BIT(5)},
214 {"CSME_PECI", BIT(6)},
215 {"PSF1", BIT(7)},
216
217 {"PSF2", BIT(0)},
218 {"PSF3", BIT(1)},
219 {"PSF4", BIT(2)},
220 {"CNVI", BIT(3)},
221 {"UFS0", BIT(4)},
222 {"EMMC", BIT(5)},
223 {"SPF", BIT(6)},
224 {"SBR6", BIT(7)},
225
226 {"SBR7", BIT(0)},
227 {"NPK_AON", BIT(1)},
228 {"HDA_PGD4", BIT(2)},
229 {"HDA_PGD5", BIT(3)},
230 {"HDA_PGD6", BIT(4)},
231 /* Reserved for Cannonlake but valid for Icelake */
232 {"PSF6", BIT(5)},
233 {"PSF7", BIT(6)},
234 {"PSF8", BIT(7)},
235
236 /* Icelake generation onwards only */
237 {"RES_65", BIT(0)},
238 {"RES_66", BIT(1)},
239 {"RES_67", BIT(2)},
240 {"TAM", BIT(3)},
241 {"GBETSN", BIT(4)},
242 {"TBTLSX", BIT(5)},
243 {"RES_71", BIT(6)},
244 {"RES_72", BIT(7)},
245 {}
246 };
247
248 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
249 {"AUDIO_D3", BIT(0)},
250 {"OTG_D3", BIT(1)},
251 {"XHCI_D3", BIT(2)},
252 {"LPIO_D3", BIT(3)},
253 {"SDX_D3", BIT(4)},
254 {"SATA_D3", BIT(5)},
255 {"UFS0_D3", BIT(6)},
256 {"UFS1_D3", BIT(7)},
257 {"EMMC_D3", BIT(8)},
258 {}
259 };
260
261 static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
262 {"SDIO_PLL_OFF", BIT(0)},
263 {"USB2_PLL_OFF", BIT(1)},
264 {"AUDIO_PLL_OFF", BIT(2)},
265 {"OC_PLL_OFF", BIT(3)},
266 {"MAIN_PLL_OFF", BIT(4)},
267 {"XOSC_OFF", BIT(5)},
268 {"LPC_CLKS_GATED", BIT(6)},
269 {"PCIE_CLKREQS_IDLE", BIT(7)},
270 {"AUDIO_ROSC_OFF", BIT(8)},
271 {"HPET_XOSC_CLK_REQ", BIT(9)},
272 {"PMC_ROSC_SLOW_CLK", BIT(10)},
273 {"AON2_ROSC_GATED", BIT(11)},
274 {"CLKACKS_DEASSERTED", BIT(12)},
275 {}
276 };
277
278 static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
279 {"MPHY_CORE_GATED", BIT(0)},
280 {"CSME_GATED", BIT(1)},
281 {"USB2_SUS_GATED", BIT(2)},
282 {"DYN_FLEX_IO_IDLE", BIT(3)},
283 {"GBE_NO_LINK", BIT(4)},
284 {"THERM_SEN_DISABLED", BIT(5)},
285 {"PCIE_LOW_POWER", BIT(6)},
286 {"ISH_VNNAON_REQ_ACT", BIT(7)},
287 {"ISH_VNN_REQ_ACT", BIT(8)},
288 {"CNV_VNNAON_REQ_ACT", BIT(9)},
289 {"CNV_VNN_REQ_ACT", BIT(10)},
290 {"NPK_VNNON_REQ_ACT", BIT(11)},
291 {"PMSYNC_STATE_IDLE", BIT(12)},
292 {"ALST_GT_THRES", BIT(13)},
293 {"PMC_ARC_PG_READY", BIT(14)},
294 {}
295 };
296
297 static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
298 cnp_slps0_dbg0_map,
299 cnp_slps0_dbg1_map,
300 cnp_slps0_dbg2_map,
301 NULL,
302 };
303
304 static const struct pmc_bit_map cnp_ltr_show_map[] = {
305 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
306 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
307 {"SATA", CNP_PMC_LTR_SATA},
308 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
309 {"XHCI", CNP_PMC_LTR_XHCI},
310 {"Reserved", CNP_PMC_LTR_RESERVED},
311 {"ME", CNP_PMC_LTR_ME},
312 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
313 {"EVA", CNP_PMC_LTR_EVA},
314 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
315 {"HD_AUDIO", CNP_PMC_LTR_AZ},
316 {"CNV", CNP_PMC_LTR_CNV},
317 {"LPSS", CNP_PMC_LTR_LPSS},
318 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
319 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
320 {"CAMERA", CNP_PMC_LTR_CAM},
321 {"ESPI", CNP_PMC_LTR_ESPI},
322 {"SCC", CNP_PMC_LTR_SCC},
323 {"ISH", CNP_PMC_LTR_ISH},
324 {"UFSX2", CNP_PMC_LTR_UFSX2},
325 {"EMMC", CNP_PMC_LTR_EMMC},
326 /* Reserved for Cannonlake but valid for Icelake */
327 {"WIGIG", ICL_PMC_LTR_WIGIG},
328 /* Below two cannot be used for LTR_IGNORE */
329 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
330 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
331 {}
332 };
333
334 static const struct pmc_reg_map cnp_reg_map = {
335 .pfear_sts = cnp_pfear_map,
336 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
337 .slps0_dbg_maps = cnp_slps0_dbg_maps,
338 .ltr_show_sts = cnp_ltr_show_map,
339 .msr_sts = msr_map,
340 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
341 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
342 .regmap_length = CNP_PMC_MMIO_REG_LEN,
343 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
344 .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
345 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
346 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
347 .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
348 };
349
350 static const struct pmc_reg_map icl_reg_map = {
351 .pfear_sts = cnp_pfear_map,
352 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
353 .slps0_dbg_maps = cnp_slps0_dbg_maps,
354 .ltr_show_sts = cnp_ltr_show_map,
355 .msr_sts = msr_map,
356 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
357 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
358 .regmap_length = CNP_PMC_MMIO_REG_LEN,
359 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
360 .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
361 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
362 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
363 .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
364 };
365
366 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
367 {
368 return readb(pmcdev->regbase + offset);
369 }
370
371 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
372 {
373 return readl(pmcdev->regbase + reg_offset);
374 }
375
376 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
377 reg_offset, u32 val)
378 {
379 writel(val, pmcdev->regbase + reg_offset);
380 }
381
382 static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
383 {
384 return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
385 }
386
387 static int pmc_core_dev_state_get(void *data, u64 *val)
388 {
389 struct pmc_dev *pmcdev = data;
390 const struct pmc_reg_map *map = pmcdev->map;
391 u32 value;
392
393 value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
394 *val = pmc_core_adjust_slp_s0_step(value);
395
396 return 0;
397 }
398
399 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
400
401 static int pmc_core_check_read_lock_bit(void)
402 {
403 struct pmc_dev *pmcdev = &pmc;
404 u32 value;
405
406 value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
407 return value & BIT(pmcdev->map->pm_read_disable_bit);
408 }
409
410 #if IS_ENABLED(CONFIG_DEBUG_FS)
411 static bool slps0_dbg_latch;
412
413 static void pmc_core_display_map(struct seq_file *s, int index,
414 u8 pf_reg, const struct pmc_bit_map *pf_map)
415 {
416 seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
417 index, pf_map[index].name,
418 pf_map[index].bit_mask & pf_reg ? "Off" : "On");
419 }
420
421 static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
422 {
423 struct pmc_dev *pmcdev = s->private;
424 const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
425 u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
426 int index, iter;
427
428 iter = pmcdev->map->ppfear0_offset;
429
430 for (index = 0; index < pmcdev->map->ppfear_buckets &&
431 index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
432 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
433
434 for (index = 0; map[index].name &&
435 index < pmcdev->map->ppfear_buckets * 8; index++)
436 pmc_core_display_map(s, index, pf_regs[index / 8], map);
437
438 return 0;
439 }
440 DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
441
442 /* This function should return link status, 0 means ready */
443 static int pmc_core_mtpmc_link_status(void)
444 {
445 struct pmc_dev *pmcdev = &pmc;
446 u32 value;
447
448 value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
449 return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
450 }
451
452 static int pmc_core_send_msg(u32 *addr_xram)
453 {
454 struct pmc_dev *pmcdev = &pmc;
455 u32 dest;
456 int timeout;
457
458 for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
459 if (pmc_core_mtpmc_link_status() == 0)
460 break;
461 msleep(5);
462 }
463
464 if (timeout <= 0 && pmc_core_mtpmc_link_status())
465 return -EBUSY;
466
467 dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
468 pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
469 return 0;
470 }
471
472 static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
473 {
474 struct pmc_dev *pmcdev = s->private;
475 const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
476 u32 mphy_core_reg_low, mphy_core_reg_high;
477 u32 val_low, val_high;
478 int index, err = 0;
479
480 if (pmcdev->pmc_xram_read_bit) {
481 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
482 return 0;
483 }
484
485 mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
486 mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
487
488 mutex_lock(&pmcdev->lock);
489
490 if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
491 err = -EBUSY;
492 goto out_unlock;
493 }
494
495 msleep(10);
496 val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
497
498 if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
499 err = -EBUSY;
500 goto out_unlock;
501 }
502
503 msleep(10);
504 val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
505
506 for (index = 0; map[index].name && index < 8; index++) {
507 seq_printf(s, "%-32s\tState: %s\n",
508 map[index].name,
509 map[index].bit_mask & val_low ? "Not power gated" :
510 "Power gated");
511 }
512
513 for (index = 8; map[index].name; index++) {
514 seq_printf(s, "%-32s\tState: %s\n",
515 map[index].name,
516 map[index].bit_mask & val_high ? "Not power gated" :
517 "Power gated");
518 }
519
520 out_unlock:
521 mutex_unlock(&pmcdev->lock);
522 return err;
523 }
524 DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
525
526 static int pmc_core_pll_show(struct seq_file *s, void *unused)
527 {
528 struct pmc_dev *pmcdev = s->private;
529 const struct pmc_bit_map *map = pmcdev->map->pll_sts;
530 u32 mphy_common_reg, val;
531 int index, err = 0;
532
533 if (pmcdev->pmc_xram_read_bit) {
534 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
535 return 0;
536 }
537
538 mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
539 mutex_lock(&pmcdev->lock);
540
541 if (pmc_core_send_msg(&mphy_common_reg) != 0) {
542 err = -EBUSY;
543 goto out_unlock;
544 }
545
546 /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
547 msleep(10);
548 val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
549
550 for (index = 0; map[index].name ; index++) {
551 seq_printf(s, "%-32s\tState: %s\n",
552 map[index].name,
553 map[index].bit_mask & val ? "Active" : "Idle");
554 }
555
556 out_unlock:
557 mutex_unlock(&pmcdev->lock);
558 return err;
559 }
560 DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
561
562 static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
563 *userbuf, size_t count, loff_t *ppos)
564 {
565 struct pmc_dev *pmcdev = &pmc;
566 const struct pmc_reg_map *map = pmcdev->map;
567 u32 val, buf_size, fd;
568 int err = 0;
569
570 buf_size = count < 64 ? count : 64;
571 mutex_lock(&pmcdev->lock);
572
573 if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
574 err = -EFAULT;
575 goto out_unlock;
576 }
577
578 if (val > map->ltr_ignore_max) {
579 err = -EINVAL;
580 goto out_unlock;
581 }
582
583 fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
584 fd |= (1U << val);
585 pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
586
587 out_unlock:
588 mutex_unlock(&pmcdev->lock);
589 return err == 0 ? count : err;
590 }
591
592 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
593 {
594 return 0;
595 }
596
597 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
598 {
599 return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
600 }
601
602 static const struct file_operations pmc_core_ltr_ignore_ops = {
603 .open = pmc_core_ltr_ignore_open,
604 .read = seq_read,
605 .write = pmc_core_ltr_ignore_write,
606 .llseek = seq_lseek,
607 .release = single_release,
608 };
609
610 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
611 {
612 const struct pmc_reg_map *map = pmcdev->map;
613 u32 fd;
614
615 mutex_lock(&pmcdev->lock);
616
617 if (!reset && !slps0_dbg_latch)
618 goto out_unlock;
619
620 fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
621 if (reset)
622 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
623 else
624 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
625 pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
626
627 slps0_dbg_latch = 0;
628
629 out_unlock:
630 mutex_unlock(&pmcdev->lock);
631 }
632
633 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
634 {
635 struct pmc_dev *pmcdev = s->private;
636 const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
637 const struct pmc_bit_map *map;
638 int offset;
639 u32 data;
640
641 pmc_core_slps0_dbg_latch(pmcdev, false);
642 offset = pmcdev->map->slps0_dbg_offset;
643 while (*maps) {
644 map = *maps;
645 data = pmc_core_reg_read(pmcdev, offset);
646 offset += 4;
647 while (map->name) {
648 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
649 map->name,
650 data & map->bit_mask ?
651 "Yes" : "No");
652 ++map;
653 }
654 ++maps;
655 }
656 pmc_core_slps0_dbg_latch(pmcdev, true);
657 return 0;
658 }
659 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
660
661 static u32 convert_ltr_scale(u32 val)
662 {
663 /*
664 * As per PCIE specification supporting document
665 * ECN_LatencyTolnReporting_14Aug08.pdf the Latency
666 * Tolerance Reporting data payload is encoded in a
667 * 3 bit scale and 10 bit value fields. Values are
668 * multiplied by the indicated scale to yield an absolute time
669 * value, expressible in a range from 1 nanosecond to
670 * 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
671 *
672 * scale encoding is as follows:
673 *
674 * ----------------------------------------------
675 * |scale factor | Multiplier (ns) |
676 * ----------------------------------------------
677 * | 0 | 1 |
678 * | 1 | 32 |
679 * | 2 | 1024 |
680 * | 3 | 32768 |
681 * | 4 | 1048576 |
682 * | 5 | 33554432 |
683 * | 6 | Invalid |
684 * | 7 | Invalid |
685 * ----------------------------------------------
686 */
687 if (val > 5) {
688 pr_warn("Invalid LTR scale factor.\n");
689 return 0;
690 }
691
692 return 1U << (5 * val);
693 }
694
695 static int pmc_core_ltr_show(struct seq_file *s, void *unused)
696 {
697 struct pmc_dev *pmcdev = s->private;
698 const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
699 u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
700 u32 ltr_raw_data, scale, val;
701 u16 snoop_ltr, nonsnoop_ltr;
702 int index;
703
704 for (index = 0; map[index].name ; index++) {
705 decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
706 ltr_raw_data = pmc_core_reg_read(pmcdev,
707 map[index].bit_mask);
708 snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
709 nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
710
711 if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
712 scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
713 val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
714 decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
715 }
716
717 if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
718 scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
719 val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
720 decoded_snoop_ltr = val * convert_ltr_scale(scale);
721 }
722
723 seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
724 map[index].name, ltr_raw_data,
725 decoded_non_snoop_ltr,
726 decoded_snoop_ltr);
727 }
728 return 0;
729 }
730 DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
731
732 static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
733 {
734 struct pmc_dev *pmcdev = s->private;
735 const struct pmc_bit_map *map = pmcdev->map->msr_sts;
736 u64 pcstate_count;
737 int index;
738
739 for (index = 0; map[index].name ; index++) {
740 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
741 continue;
742
743 seq_printf(s, "%-8s : 0x%llx\n", map[index].name,
744 pcstate_count);
745 }
746
747 return 0;
748 }
749 DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
750
751 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
752 {
753 debugfs_remove_recursive(pmcdev->dbgfs_dir);
754 }
755
756 static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
757 {
758 struct dentry *dir;
759
760 dir = debugfs_create_dir("pmc_core", NULL);
761 if (!dir)
762 return -ENOMEM;
763
764 pmcdev->dbgfs_dir = dir;
765
766 debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
767 &pmc_core_dev_state);
768
769 debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
770 &pmc_core_ppfear_fops);
771
772 debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
773 &pmc_core_ltr_ignore_ops);
774
775 debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
776
777 debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
778 &pmc_core_pkgc_fops);
779
780 if (pmcdev->map->pll_sts)
781 debugfs_create_file("pll_status", 0444, dir, pmcdev,
782 &pmc_core_pll_fops);
783
784 if (pmcdev->map->mphy_sts)
785 debugfs_create_file("mphy_core_lanes_power_gating_status",
786 0444, dir, pmcdev,
787 &pmc_core_mphy_pg_fops);
788
789 if (pmcdev->map->slps0_dbg_maps) {
790 debugfs_create_file("slp_s0_debug_status", 0444,
791 dir, pmcdev,
792 &pmc_core_slps0_dbg_fops);
793
794 debugfs_create_bool("slp_s0_dbg_latch", 0644,
795 dir, &slps0_dbg_latch);
796 }
797
798 return 0;
799 }
800 #else
801 static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
802 {
803 return 0;
804 }
805
806 static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
807 {
808 }
809 #endif /* CONFIG_DEBUG_FS */
810
811 static const struct x86_cpu_id intel_pmc_core_ids[] = {
812 INTEL_CPU_FAM6(SKYLAKE_MOBILE, spt_reg_map),
813 INTEL_CPU_FAM6(SKYLAKE_DESKTOP, spt_reg_map),
814 INTEL_CPU_FAM6(KABYLAKE_MOBILE, spt_reg_map),
815 INTEL_CPU_FAM6(KABYLAKE_DESKTOP, spt_reg_map),
816 INTEL_CPU_FAM6(CANNONLAKE_MOBILE, cnp_reg_map),
817 INTEL_CPU_FAM6(ICELAKE_MOBILE, icl_reg_map),
818 {}
819 };
820
821 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
822
823 static const struct pci_device_id pmc_pci_ids[] = {
824 { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
825 { 0, },
826 };
827
828 /*
829 * This quirk can be used on those platforms where
830 * the platform BIOS enforces 24Mhx Crystal to shutdown
831 * before PMC can assert SLP_S0#.
832 */
833 static int quirk_xtal_ignore(const struct dmi_system_id *id)
834 {
835 struct pmc_dev *pmcdev = &pmc;
836 u32 value;
837
838 value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
839 /* 24MHz Crystal Shutdown Qualification Disable */
840 value |= SPT_PMC_VRIC1_XTALSDQDIS;
841 /* Low Voltage Mode Enable */
842 value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
843 pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
844 return 0;
845 }
846
847 static const struct dmi_system_id pmc_core_dmi_table[] = {
848 {
849 .callback = quirk_xtal_ignore,
850 .ident = "HP Elite x2 1013 G3",
851 .matches = {
852 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
853 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
854 },
855 },
856 {}
857 };
858
859 static int pmc_core_probe(struct platform_device *pdev)
860 {
861 static bool device_initialized;
862 struct pmc_dev *pmcdev = &pmc;
863 const struct x86_cpu_id *cpu_id;
864 u64 slp_s0_addr;
865 int err;
866
867 if (device_initialized)
868 return -ENODEV;
869
870 cpu_id = x86_match_cpu(intel_pmc_core_ids);
871 if (!cpu_id)
872 return -ENODEV;
873
874 pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
875
876 /*
877 * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here
878 * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
879 * in this case.
880 */
881 if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
882 pmcdev->map = &cnp_reg_map;
883
884 if (lpit_read_residency_count_address(&slp_s0_addr))
885 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
886 else
887 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
888
889 pmcdev->regbase = ioremap(pmcdev->base_addr,
890 pmcdev->map->regmap_length);
891 if (!pmcdev->regbase)
892 return -ENOMEM;
893
894 mutex_init(&pmcdev->lock);
895 platform_set_drvdata(pdev, pmcdev);
896 pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
897 dmi_check_system(pmc_core_dmi_table);
898
899 err = pmc_core_dbgfs_register(pmcdev);
900 if (err < 0) {
901 dev_warn(&pdev->dev, "debugfs register failed.\n");
902 iounmap(pmcdev->regbase);
903 return err;
904 }
905
906 device_initialized = true;
907 dev_info(&pdev->dev, " initialized\n");
908
909 return 0;
910 }
911
912 static int pmc_core_remove(struct platform_device *pdev)
913 {
914 struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
915
916 pmc_core_dbgfs_unregister(pmcdev);
917 platform_set_drvdata(pdev, NULL);
918 mutex_destroy(&pmcdev->lock);
919 iounmap(pmcdev->regbase);
920 return 0;
921 }
922
923 #ifdef CONFIG_PM_SLEEP
924
925 static bool warn_on_s0ix_failures;
926 module_param(warn_on_s0ix_failures, bool, 0644);
927 MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
928
929 static int pmc_core_suspend(struct device *dev)
930 {
931 struct pmc_dev *pmcdev = dev_get_drvdata(dev);
932
933 pmcdev->check_counters = false;
934
935 /* No warnings on S0ix failures */
936 if (!warn_on_s0ix_failures)
937 return 0;
938
939 /* Check if the syspend will actually use S0ix */
940 if (pm_suspend_via_firmware())
941 return 0;
942
943 /* Save PC10 residency for checking later */
944 if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pmcdev->pc10_counter))
945 return -EIO;
946
947 /* Save S0ix residency for checking later */
948 if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter))
949 return -EIO;
950
951 pmcdev->check_counters = true;
952 return 0;
953 }
954
955 static inline bool pmc_core_is_pc10_failed(struct pmc_dev *pmcdev)
956 {
957 u64 pc10_counter;
958
959 if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pc10_counter))
960 return false;
961
962 if (pc10_counter == pmcdev->pc10_counter)
963 return true;
964
965 return false;
966 }
967
968 static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
969 {
970 u64 s0ix_counter;
971
972 if (pmc_core_dev_state_get(pmcdev, &s0ix_counter))
973 return false;
974
975 if (s0ix_counter == pmcdev->s0ix_counter)
976 return true;
977
978 return false;
979 }
980
981 static int pmc_core_resume(struct device *dev)
982 {
983 struct pmc_dev *pmcdev = dev_get_drvdata(dev);
984 const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
985 int offset = pmcdev->map->slps0_dbg_offset;
986 const struct pmc_bit_map *map;
987 u32 data;
988
989 if (!pmcdev->check_counters)
990 return 0;
991
992 if (!pmc_core_is_s0ix_failed(pmcdev))
993 return 0;
994
995 if (pmc_core_is_pc10_failed(pmcdev)) {
996 /* S0ix failed because of PC10 entry failure */
997 dev_info(dev, "CPU did not enter PC10!!! (PC10 cnt=0x%llx)\n",
998 pmcdev->pc10_counter);
999 return 0;
1000 }
1001
1002 /* The real interesting case - S0ix failed - lets ask PMC why. */
1003 dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
1004 pmcdev->s0ix_counter);
1005 while (*maps) {
1006 map = *maps;
1007 data = pmc_core_reg_read(pmcdev, offset);
1008 offset += 4;
1009 while (map->name) {
1010 dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
1011 map->name,
1012 data & map->bit_mask ? "Yes" : "No");
1013 map++;
1014 }
1015 maps++;
1016 }
1017 return 0;
1018 }
1019
1020 #endif
1021
1022 static const struct dev_pm_ops pmc_core_pm_ops = {
1023 SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
1024 };
1025
1026 static struct platform_driver pmc_core_driver = {
1027 .driver = {
1028 .name = "intel_pmc_core",
1029 .pm = &pmc_core_pm_ops,
1030 },
1031 .probe = pmc_core_probe,
1032 .remove = pmc_core_remove,
1033 };
1034
1035 static struct platform_device pmc_core_device = {
1036 .name = "intel_pmc_core",
1037 };
1038
1039 static int __init pmc_core_init(void)
1040 {
1041 int ret;
1042
1043 if (!x86_match_cpu(intel_pmc_core_ids))
1044 return -ENODEV;
1045
1046 ret = platform_driver_register(&pmc_core_driver);
1047 if (ret)
1048 return ret;
1049
1050 ret = platform_device_register(&pmc_core_device);
1051 if (ret) {
1052 platform_driver_unregister(&pmc_core_driver);
1053 return ret;
1054 }
1055
1056 return 0;
1057 }
1058
1059 static void __exit pmc_core_exit(void)
1060 {
1061 platform_device_unregister(&pmc_core_device);
1062 platform_driver_unregister(&pmc_core_driver);
1063 }
1064
1065 module_init(pmc_core_init)
1066 module_exit(pmc_core_exit)
1067
1068 MODULE_LICENSE("GPL v2");
1069 MODULE_DESCRIPTION("Intel PMC Core Driver");
Linux with added FPC-III support