1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Intel SCU IPC mechanism
5 * (C) Copyright 2008-2010,2015 Intel Corporation
6 * Author: Sreedhara DS (sreedhara.ds@intel.com)
8 * SCU running in ARC processor communicates with other entity running in IA
9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
13 * along with other APIs.
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
23 #include <linux/sfi.h>
25 #include <asm/intel-mid.h>
26 #include <asm/intel_scu_ipc.h>
28 /* IPC defines the following message types */
29 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
30 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
31 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
32 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
33 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
35 /* Command id associated with message IPCMSG_PCNTRL */
36 #define IPC_CMD_PCNTRL_W 0 /* Register write */
37 #define IPC_CMD_PCNTRL_R 1 /* Register read */
38 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
41 * IPC register summary
43 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
44 * To read or write information to the SCU, driver writes to IPC-1 memory
45 * mapped registers. The following is the IPC mechanism
47 * 1. IA core cDMI interface claims this transaction and converts it to a
48 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
50 * 2. South Complex cDMI block receives this message and writes it to
51 * the IPC-1 register block, causing an interrupt to the SCU
53 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
54 * message handler is called within firmware.
57 #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
58 #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
59 #define IPC_IOC 0x100 /* IPC command register IOC bit */
61 #define PCI_DEVICE_ID_LINCROFT 0x082a
62 #define PCI_DEVICE_ID_PENWELL 0x080e
63 #define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
64 #define PCI_DEVICE_ID_TANGIER 0x11a0
66 /* intel scu ipc driver data */
67 struct intel_scu_ipc_pdata_t
{
73 static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata
= {
74 .i2c_base
= 0xff12b000,
79 /* Penwell and Cloverview */
80 static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata
= {
81 .i2c_base
= 0xff12b000,
86 static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata
= {
87 .i2c_base
= 0xff00d000,
92 struct intel_scu_ipc_dev
{
94 void __iomem
*ipc_base
;
95 void __iomem
*i2c_base
;
96 struct completion cmd_complete
;
100 static struct intel_scu_ipc_dev ipcdev
; /* Only one for now */
103 * IPC Read Buffer (Read Only):
104 * 16 byte buffer for receiving data from SCU, if IPC command
105 * processing results in response data
107 #define IPC_READ_BUFFER 0x90
109 #define IPC_I2C_CNTRL_ADDR 0
110 #define I2C_DATA_ADDR 0x04
112 static DEFINE_MUTEX(ipclock
); /* lock used to prevent multiple call to SCU */
116 * Command Register (Write Only):
117 * A write to this register results in an interrupt to the SCU core processor
119 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
121 static inline void ipc_command(struct intel_scu_ipc_dev
*scu
, u32 cmd
)
124 reinit_completion(&scu
->cmd_complete
);
125 writel(cmd
| IPC_IOC
, scu
->ipc_base
);
127 writel(cmd
, scu
->ipc_base
);
132 * IPC Write Buffer (Write Only):
133 * 16-byte buffer for sending data associated with IPC command to
134 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
136 static inline void ipc_data_writel(struct intel_scu_ipc_dev
*scu
, u32 data
, u32 offset
)
138 writel(data
, scu
->ipc_base
+ 0x80 + offset
);
142 * Status Register (Read Only):
143 * Driver will read this register to get the ready/busy status of the IPC
144 * block and error status of the IPC command that was just processed by SCU
146 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
148 static inline u8
ipc_read_status(struct intel_scu_ipc_dev
*scu
)
150 return __raw_readl(scu
->ipc_base
+ 0x04);
153 /* Read ipc byte data */
154 static inline u8
ipc_data_readb(struct intel_scu_ipc_dev
*scu
, u32 offset
)
156 return readb(scu
->ipc_base
+ IPC_READ_BUFFER
+ offset
);
159 /* Read ipc u32 data */
160 static inline u32
ipc_data_readl(struct intel_scu_ipc_dev
*scu
, u32 offset
)
162 return readl(scu
->ipc_base
+ IPC_READ_BUFFER
+ offset
);
165 /* Wait till scu status is busy */
166 static inline int busy_loop(struct intel_scu_ipc_dev
*scu
)
168 u32 status
= ipc_read_status(scu
);
169 u32 loop_count
= 100000;
171 /* break if scu doesn't reset busy bit after huge retry */
172 while ((status
& BIT(0)) && --loop_count
) {
173 udelay(1); /* scu processing time is in few u secods */
174 status
= ipc_read_status(scu
);
177 if (status
& BIT(0)) {
178 dev_err(scu
->dev
, "IPC timed out");
188 /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
189 static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev
*scu
)
193 if (!wait_for_completion_timeout(&scu
->cmd_complete
, 3 * HZ
)) {
194 dev_err(scu
->dev
, "IPC timed out\n");
198 status
= ipc_read_status(scu
);
205 static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev
*scu
)
207 return scu
->irq_mode
? ipc_wait_for_interrupt(scu
) : busy_loop(scu
);
210 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
211 static int pwr_reg_rdwr(u16
*addr
, u8
*data
, u32 count
, u32 op
, u32 id
)
213 struct intel_scu_ipc_dev
*scu
= &ipcdev
;
217 u8 cbuf
[IPC_WWBUF_SIZE
];
218 u32
*wbuf
= (u32
*)&cbuf
;
220 memset(cbuf
, 0, sizeof(cbuf
));
222 mutex_lock(&ipclock
);
224 if (scu
->dev
== NULL
) {
225 mutex_unlock(&ipclock
);
229 for (nc
= 0; nc
< count
; nc
++, offset
+= 2) {
230 cbuf
[offset
] = addr
[nc
];
231 cbuf
[offset
+ 1] = addr
[nc
] >> 8;
234 if (id
== IPC_CMD_PCNTRL_R
) {
235 for (nc
= 0, offset
= 0; nc
< count
; nc
++, offset
+= 4)
236 ipc_data_writel(scu
, wbuf
[nc
], offset
);
237 ipc_command(scu
, (count
* 2) << 16 | id
<< 12 | 0 << 8 | op
);
238 } else if (id
== IPC_CMD_PCNTRL_W
) {
239 for (nc
= 0; nc
< count
; nc
++, offset
+= 1)
240 cbuf
[offset
] = data
[nc
];
241 for (nc
= 0, offset
= 0; nc
< count
; nc
++, offset
+= 4)
242 ipc_data_writel(scu
, wbuf
[nc
], offset
);
243 ipc_command(scu
, (count
* 3) << 16 | id
<< 12 | 0 << 8 | op
);
244 } else if (id
== IPC_CMD_PCNTRL_M
) {
245 cbuf
[offset
] = data
[0];
246 cbuf
[offset
+ 1] = data
[1];
247 ipc_data_writel(scu
, wbuf
[0], 0); /* Write wbuff */
248 ipc_command(scu
, 4 << 16 | id
<< 12 | 0 << 8 | op
);
251 err
= intel_scu_ipc_check_status(scu
);
252 if (!err
&& id
== IPC_CMD_PCNTRL_R
) { /* Read rbuf */
253 /* Workaround: values are read as 0 without memcpy_fromio */
254 memcpy_fromio(cbuf
, scu
->ipc_base
+ 0x90, 16);
255 for (nc
= 0; nc
< count
; nc
++)
256 data
[nc
] = ipc_data_readb(scu
, nc
);
258 mutex_unlock(&ipclock
);
263 * intel_scu_ipc_ioread8 - read a word via the SCU
264 * @addr: register on SCU
265 * @data: return pointer for read byte
267 * Read a single register. Returns 0 on success or an error code. All
268 * locking between SCU accesses is handled for the caller.
270 * This function may sleep.
272 int intel_scu_ipc_ioread8(u16 addr
, u8
*data
)
274 return pwr_reg_rdwr(&addr
, data
, 1, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
276 EXPORT_SYMBOL(intel_scu_ipc_ioread8
);
279 * intel_scu_ipc_ioread16 - read a word via the SCU
280 * @addr: register on SCU
281 * @data: return pointer for read word
283 * Read a register pair. Returns 0 on success or an error code. All
284 * locking between SCU accesses is handled for the caller.
286 * This function may sleep.
288 int intel_scu_ipc_ioread16(u16 addr
, u16
*data
)
290 u16 x
[2] = {addr
, addr
+ 1};
291 return pwr_reg_rdwr(x
, (u8
*)data
, 2, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
293 EXPORT_SYMBOL(intel_scu_ipc_ioread16
);
296 * intel_scu_ipc_ioread32 - read a dword via the SCU
297 * @addr: register on SCU
298 * @data: return pointer for read dword
300 * Read four registers. Returns 0 on success or an error code. All
301 * locking between SCU accesses is handled for the caller.
303 * This function may sleep.
305 int intel_scu_ipc_ioread32(u16 addr
, u32
*data
)
307 u16 x
[4] = {addr
, addr
+ 1, addr
+ 2, addr
+ 3};
308 return pwr_reg_rdwr(x
, (u8
*)data
, 4, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
310 EXPORT_SYMBOL(intel_scu_ipc_ioread32
);
313 * intel_scu_ipc_iowrite8 - write a byte via the SCU
314 * @addr: register on SCU
315 * @data: byte to write
317 * Write a single register. Returns 0 on success or an error code. All
318 * locking between SCU accesses is handled for the caller.
320 * This function may sleep.
322 int intel_scu_ipc_iowrite8(u16 addr
, u8 data
)
324 return pwr_reg_rdwr(&addr
, &data
, 1, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
326 EXPORT_SYMBOL(intel_scu_ipc_iowrite8
);
329 * intel_scu_ipc_iowrite16 - write a word via the SCU
330 * @addr: register on SCU
331 * @data: word to write
333 * Write two registers. Returns 0 on success or an error code. All
334 * locking between SCU accesses is handled for the caller.
336 * This function may sleep.
338 int intel_scu_ipc_iowrite16(u16 addr
, u16 data
)
340 u16 x
[2] = {addr
, addr
+ 1};
341 return pwr_reg_rdwr(x
, (u8
*)&data
, 2, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
343 EXPORT_SYMBOL(intel_scu_ipc_iowrite16
);
346 * intel_scu_ipc_iowrite32 - write a dword via the SCU
347 * @addr: register on SCU
348 * @data: dword to write
350 * Write four registers. Returns 0 on success or an error code. All
351 * locking between SCU accesses is handled for the caller.
353 * This function may sleep.
355 int intel_scu_ipc_iowrite32(u16 addr
, u32 data
)
357 u16 x
[4] = {addr
, addr
+ 1, addr
+ 2, addr
+ 3};
358 return pwr_reg_rdwr(x
, (u8
*)&data
, 4, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
360 EXPORT_SYMBOL(intel_scu_ipc_iowrite32
);
363 * intel_scu_ipc_readvv - read a set of registers
364 * @addr: register list
365 * @data: bytes to return
366 * @len: length of array
368 * Read registers. Returns 0 on success or an error code. All
369 * locking between SCU accesses is handled for the caller.
371 * The largest array length permitted by the hardware is 5 items.
373 * This function may sleep.
375 int intel_scu_ipc_readv(u16
*addr
, u8
*data
, int len
)
377 return pwr_reg_rdwr(addr
, data
, len
, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_R
);
379 EXPORT_SYMBOL(intel_scu_ipc_readv
);
382 * intel_scu_ipc_writev - write a set of registers
383 * @addr: register list
384 * @data: bytes to write
385 * @len: length of array
387 * Write registers. Returns 0 on success or an error code. All
388 * locking between SCU accesses is handled for the caller.
390 * The largest array length permitted by the hardware is 5 items.
392 * This function may sleep.
395 int intel_scu_ipc_writev(u16
*addr
, u8
*data
, int len
)
397 return pwr_reg_rdwr(addr
, data
, len
, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_W
);
399 EXPORT_SYMBOL(intel_scu_ipc_writev
);
402 * intel_scu_ipc_update_register - r/m/w a register
403 * @addr: register address
404 * @bits: bits to update
405 * @mask: mask of bits to update
407 * Read-modify-write power control unit register. The first data argument
408 * must be register value and second is mask value
409 * mask is a bitmap that indicates which bits to update.
410 * 0 = masked. Don't modify this bit, 1 = modify this bit.
411 * returns 0 on success or an error code.
413 * This function may sleep. Locking between SCU accesses is handled
416 int intel_scu_ipc_update_register(u16 addr
, u8 bits
, u8 mask
)
418 u8 data
[2] = { bits
, mask
};
419 return pwr_reg_rdwr(&addr
, data
, 1, IPCMSG_PCNTRL
, IPC_CMD_PCNTRL_M
);
421 EXPORT_SYMBOL(intel_scu_ipc_update_register
);
424 * intel_scu_ipc_simple_command - send a simple command
428 * Issue a simple command to the SCU. Do not use this interface if
429 * you must then access data as any data values may be overwritten
430 * by another SCU access by the time this function returns.
432 * This function may sleep. Locking for SCU accesses is handled for
435 int intel_scu_ipc_simple_command(int cmd
, int sub
)
437 struct intel_scu_ipc_dev
*scu
= &ipcdev
;
440 mutex_lock(&ipclock
);
441 if (scu
->dev
== NULL
) {
442 mutex_unlock(&ipclock
);
445 ipc_command(scu
, sub
<< 12 | cmd
);
446 err
= intel_scu_ipc_check_status(scu
);
447 mutex_unlock(&ipclock
);
450 EXPORT_SYMBOL(intel_scu_ipc_simple_command
);
453 * intel_scu_ipc_command - command with data
457 * @inlen: input length in dwords
459 * @outlein: output length in dwords
461 * Issue a command to the SCU which involves data transfers. Do the
462 * data copies under the lock but leave it for the caller to interpret
464 int intel_scu_ipc_command(int cmd
, int sub
, u32
*in
, int inlen
,
465 u32
*out
, int outlen
)
467 struct intel_scu_ipc_dev
*scu
= &ipcdev
;
470 mutex_lock(&ipclock
);
471 if (scu
->dev
== NULL
) {
472 mutex_unlock(&ipclock
);
476 for (i
= 0; i
< inlen
; i
++)
477 ipc_data_writel(scu
, *in
++, 4 * i
);
479 ipc_command(scu
, (inlen
<< 16) | (sub
<< 12) | cmd
);
480 err
= intel_scu_ipc_check_status(scu
);
483 for (i
= 0; i
< outlen
; i
++)
484 *out
++ = ipc_data_readl(scu
, 4 * i
);
487 mutex_unlock(&ipclock
);
490 EXPORT_SYMBOL(intel_scu_ipc_command
);
492 #define IPC_SPTR 0x08
493 #define IPC_DPTR 0x0C
496 * intel_scu_ipc_raw_command() - IPC command with data and pointers
497 * @cmd: IPC command code.
498 * @sub: IPC command sub type.
499 * @in: input data of this IPC command.
500 * @inlen: input data length in dwords.
501 * @out: output data of this IPC command.
502 * @outlen: output data length in dwords.
503 * @sptr: data writing to SPTR register.
504 * @dptr: data writing to DPTR register.
506 * Send an IPC command to SCU with input/output data and source/dest pointers.
508 * Return: an IPC error code or 0 on success.
510 int intel_scu_ipc_raw_command(int cmd
, int sub
, u8
*in
, int inlen
,
511 u32
*out
, int outlen
, u32 dptr
, u32 sptr
)
513 struct intel_scu_ipc_dev
*scu
= &ipcdev
;
514 int inbuflen
= DIV_ROUND_UP(inlen
, 4);
522 mutex_lock(&ipclock
);
523 if (scu
->dev
== NULL
) {
524 mutex_unlock(&ipclock
);
528 writel(dptr
, scu
->ipc_base
+ IPC_DPTR
);
529 writel(sptr
, scu
->ipc_base
+ IPC_SPTR
);
532 * SRAM controller doesn't support 8-bit writes, it only
533 * supports 32-bit writes, so we have to copy input data into
534 * the temporary buffer, and SCU FW will use the inlen to
535 * determine the actual input data length in the temporary
538 memcpy(inbuf
, in
, inlen
);
540 for (i
= 0; i
< inbuflen
; i
++)
541 ipc_data_writel(scu
, inbuf
[i
], 4 * i
);
543 ipc_command(scu
, (inlen
<< 16) | (sub
<< 12) | cmd
);
544 err
= intel_scu_ipc_check_status(scu
);
546 for (i
= 0; i
< outlen
; i
++)
547 *out
++ = ipc_data_readl(scu
, 4 * i
);
550 mutex_unlock(&ipclock
);
553 EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command
);
556 #define IPC_I2C_WRITE 1 /* I2C Write command */
557 #define IPC_I2C_READ 2 /* I2C Read command */
560 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
561 * @addr: I2C address + command bits
562 * @data: data to read/write
564 * Perform an an I2C read/write operation via the SCU. All locking is
565 * handled for the caller. This function may sleep.
567 * Returns an error code or 0 on success.
569 * This has to be in the IPC driver for the locking.
571 int intel_scu_ipc_i2c_cntrl(u32 addr
, u32
*data
)
573 struct intel_scu_ipc_dev
*scu
= &ipcdev
;
576 mutex_lock(&ipclock
);
577 if (scu
->dev
== NULL
) {
578 mutex_unlock(&ipclock
);
581 cmd
= (addr
>> 24) & 0xFF;
582 if (cmd
== IPC_I2C_READ
) {
583 writel(addr
, scu
->i2c_base
+ IPC_I2C_CNTRL_ADDR
);
584 /* Write not getting updated without delay */
585 usleep_range(1000, 2000);
586 *data
= readl(scu
->i2c_base
+ I2C_DATA_ADDR
);
587 } else if (cmd
== IPC_I2C_WRITE
) {
588 writel(*data
, scu
->i2c_base
+ I2C_DATA_ADDR
);
589 usleep_range(1000, 2000);
590 writel(addr
, scu
->i2c_base
+ IPC_I2C_CNTRL_ADDR
);
593 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd
);
595 mutex_unlock(&ipclock
);
598 mutex_unlock(&ipclock
);
601 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl
);
604 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
605 * When ioc bit is set to 1, caller api must wait for interrupt handler called
606 * which in turn unlocks the caller api. Currently this is not used
608 * This is edge triggered so we need take no action to clear anything
610 static irqreturn_t
ioc(int irq
, void *dev_id
)
612 struct intel_scu_ipc_dev
*scu
= dev_id
;
615 complete(&scu
->cmd_complete
);
621 * ipc_probe - probe an Intel SCU IPC
622 * @pdev: the PCI device matching
623 * @id: entry in the match table
625 * Enable and install an intel SCU IPC. This appears in the PCI space
626 * but uses some hard coded addresses as well.
628 static int ipc_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
631 struct intel_scu_ipc_dev
*scu
= &ipcdev
;
632 struct intel_scu_ipc_pdata_t
*pdata
;
634 if (scu
->dev
) /* We support only one SCU */
637 pdata
= (struct intel_scu_ipc_pdata_t
*)id
->driver_data
;
641 scu
->irq_mode
= pdata
->irq_mode
;
643 err
= pcim_enable_device(pdev
);
647 err
= pcim_iomap_regions(pdev
, 1 << 0, pci_name(pdev
));
651 init_completion(&scu
->cmd_complete
);
653 scu
->ipc_base
= pcim_iomap_table(pdev
)[0];
655 scu
->i2c_base
= ioremap_nocache(pdata
->i2c_base
, pdata
->i2c_len
);
659 err
= devm_request_irq(&pdev
->dev
, pdev
->irq
, ioc
, 0, "intel_scu_ipc",
664 /* Assign device at last */
665 scu
->dev
= &pdev
->dev
;
667 intel_scu_devices_create();
669 pci_set_drvdata(pdev
, scu
);
673 #define SCU_DEVICE(id, pdata) {PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&pdata}
675 static const struct pci_device_id pci_ids
[] = {
676 SCU_DEVICE(PCI_DEVICE_ID_LINCROFT
, intel_scu_ipc_lincroft_pdata
),
677 SCU_DEVICE(PCI_DEVICE_ID_PENWELL
, intel_scu_ipc_penwell_pdata
),
678 SCU_DEVICE(PCI_DEVICE_ID_CLOVERVIEW
, intel_scu_ipc_penwell_pdata
),
679 SCU_DEVICE(PCI_DEVICE_ID_TANGIER
, intel_scu_ipc_tangier_pdata
),
683 static struct pci_driver ipc_driver
= {
685 .suppress_bind_attrs
= true,
687 .name
= "intel_scu_ipc",
691 builtin_pci_driver(ipc_driver
);