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be2net: Bug fix to avoid disabling bottom half during firmware upgrade.
[linux/fpc-iii.git] / drivers / net / mv643xx_eth.c
blobe345ec8cb473cda0d3454d5f2711b08c55fe8bdf
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
54 #include <linux/io.h>
55 #include <linux/types.h>
56 #include <linux/inet_lro.h>
57 #include <linux/slab.h>
58 #include <asm/system.h>
59
60 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
61 static char mv643xx_eth_driver_version[] = "1.4";
62
63
64 /*
65 * Registers shared between all ports.
66 */
67 #define PHY_ADDR 0x0000
68 #define SMI_REG 0x0004
69 #define SMI_BUSY 0x10000000
70 #define SMI_READ_VALID 0x08000000
71 #define SMI_OPCODE_READ 0x04000000
72 #define SMI_OPCODE_WRITE 0x00000000
73 #define ERR_INT_CAUSE 0x0080
74 #define ERR_INT_SMI_DONE 0x00000010
75 #define ERR_INT_MASK 0x0084
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
81
82 /*
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 */
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define TX_BW_RATE 0x0050
123 #define TX_BW_MTU 0x0058
124 #define TX_BW_BURST 0x005c
125 #define INT_CAUSE 0x0060
126 #define INT_TX_END 0x07f80000
127 #define INT_TX_END_0 0x00080000
128 #define INT_RX 0x000003fc
129 #define INT_RX_0 0x00000004
130 #define INT_EXT 0x00000002
131 #define INT_CAUSE_EXT 0x0064
132 #define INT_EXT_LINK_PHY 0x00110000
133 #define INT_EXT_TX 0x000000ff
134 #define INT_MASK 0x0068
135 #define INT_MASK_EXT 0x006c
136 #define TX_FIFO_URGENT_THRESHOLD 0x0074
137 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
138 #define TX_BW_RATE_MOVED 0x00e0
139 #define TX_BW_MTU_MOVED 0x00e8
140 #define TX_BW_BURST_MOVED 0x00ec
141 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
142 #define RXQ_COMMAND 0x0280
143 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
144 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
145 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
146 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
147
148 /*
149 * Misc per-port registers.
150 */
151 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
152 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
153 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
154 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
155
156
157 /*
158 * SDMA configuration register default value.
159 */
160 #if defined(__BIG_ENDIAN)
161 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
162 (RX_BURST_SIZE_4_64BIT | \
163 TX_BURST_SIZE_4_64BIT)
164 #elif defined(__LITTLE_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 BLM_RX_NO_SWAP | \
168 BLM_TX_NO_SWAP | \
169 TX_BURST_SIZE_4_64BIT)
170 #else
171 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
172 #endif
173
174
175 /*
176 * Misc definitions.
177 */
178 #define DEFAULT_RX_QUEUE_SIZE 128
179 #define DEFAULT_TX_QUEUE_SIZE 256
180 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
181
182
183 /*
184 * RX/TX descriptors.
185 */
186 #if defined(__BIG_ENDIAN)
187 struct rx_desc {
188 u16 byte_cnt; /* Descriptor buffer byte count */
189 u16 buf_size; /* Buffer size */
190 u32 cmd_sts; /* Descriptor command status */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192 u32 buf_ptr; /* Descriptor buffer pointer */
193 };
194
195 struct tx_desc {
196 u16 byte_cnt; /* buffer byte count */
197 u16 l4i_chk; /* CPU provided TCP checksum */
198 u32 cmd_sts; /* Command/status field */
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200 u32 buf_ptr; /* pointer to buffer for this descriptor*/
201 };
202 #elif defined(__LITTLE_ENDIAN)
203 struct rx_desc {
204 u32 cmd_sts; /* Descriptor command status */
205 u16 buf_size; /* Buffer size */
206 u16 byte_cnt; /* Descriptor buffer byte count */
207 u32 buf_ptr; /* Descriptor buffer pointer */
208 u32 next_desc_ptr; /* Next descriptor pointer */
209 };
210
211 struct tx_desc {
212 u32 cmd_sts; /* Command/status field */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u16 byte_cnt; /* buffer byte count */
215 u32 buf_ptr; /* pointer to buffer for this descriptor*/
216 u32 next_desc_ptr; /* Pointer to next descriptor */
217 };
218 #else
219 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
220 #endif
221
222 /* RX & TX descriptor command */
223 #define BUFFER_OWNED_BY_DMA 0x80000000
224
225 /* RX & TX descriptor status */
226 #define ERROR_SUMMARY 0x00000001
227
228 /* RX descriptor status */
229 #define LAYER_4_CHECKSUM_OK 0x40000000
230 #define RX_ENABLE_INTERRUPT 0x20000000
231 #define RX_FIRST_DESC 0x08000000
232 #define RX_LAST_DESC 0x04000000
233 #define RX_IP_HDR_OK 0x02000000
234 #define RX_PKT_IS_IPV4 0x01000000
235 #define RX_PKT_IS_ETHERNETV2 0x00800000
236 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
237 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
238 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
239
240 /* TX descriptor command */
241 #define TX_ENABLE_INTERRUPT 0x00800000
242 #define GEN_CRC 0x00400000
243 #define TX_FIRST_DESC 0x00200000
244 #define TX_LAST_DESC 0x00100000
245 #define ZERO_PADDING 0x00080000
246 #define GEN_IP_V4_CHECKSUM 0x00040000
247 #define GEN_TCP_UDP_CHECKSUM 0x00020000
248 #define UDP_FRAME 0x00010000
249 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
250 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
251
252 #define TX_IHL_SHIFT 11
253
254
255 /* global *******************************************************************/
256 struct mv643xx_eth_shared_private {
257 /*
258 * Ethernet controller base address.
259 */
260 void __iomem *base;
261
262 /*
263 * Points at the right SMI instance to use.
264 */
265 struct mv643xx_eth_shared_private *smi;
266
267 /*
268 * Provides access to local SMI interface.
269 */
270 struct mii_bus *smi_bus;
271
272 /*
273 * If we have access to the error interrupt pin (which is
274 * somewhat misnamed as it not only reflects internal errors
275 * but also reflects SMI completion), use that to wait for
276 * SMI access completion instead of polling the SMI busy bit.
277 */
278 int err_interrupt;
279 wait_queue_head_t smi_busy_wait;
280
281 /*
282 * Per-port MBUS window access register value.
283 */
284 u32 win_protect;
285
286 /*
287 * Hardware-specific parameters.
288 */
289 unsigned int t_clk;
290 int extended_rx_coal_limit;
291 int tx_bw_control;
292 };
293
294 #define TX_BW_CONTROL_ABSENT 0
295 #define TX_BW_CONTROL_OLD_LAYOUT 1
296 #define TX_BW_CONTROL_NEW_LAYOUT 2
297
298 static int mv643xx_eth_open(struct net_device *dev);
299 static int mv643xx_eth_stop(struct net_device *dev);
300
301
302 /* per-port *****************************************************************/
303 struct mib_counters {
304 u64 good_octets_received;
305 u32 bad_octets_received;
306 u32 internal_mac_transmit_err;
307 u32 good_frames_received;
308 u32 bad_frames_received;
309 u32 broadcast_frames_received;
310 u32 multicast_frames_received;
311 u32 frames_64_octets;
312 u32 frames_65_to_127_octets;
313 u32 frames_128_to_255_octets;
314 u32 frames_256_to_511_octets;
315 u32 frames_512_to_1023_octets;
316 u32 frames_1024_to_max_octets;
317 u64 good_octets_sent;
318 u32 good_frames_sent;
319 u32 excessive_collision;
320 u32 multicast_frames_sent;
321 u32 broadcast_frames_sent;
322 u32 unrec_mac_control_received;
323 u32 fc_sent;
324 u32 good_fc_received;
325 u32 bad_fc_received;
326 u32 undersize_received;
327 u32 fragments_received;
328 u32 oversize_received;
329 u32 jabber_received;
330 u32 mac_receive_error;
331 u32 bad_crc_event;
332 u32 collision;
333 u32 late_collision;
334 };
335
336 struct lro_counters {
337 u32 lro_aggregated;
338 u32 lro_flushed;
339 u32 lro_no_desc;
340 };
341
342 struct rx_queue {
343 int index;
344
345 int rx_ring_size;
346
347 int rx_desc_count;
348 int rx_curr_desc;
349 int rx_used_desc;
350
351 struct rx_desc *rx_desc_area;
352 dma_addr_t rx_desc_dma;
353 int rx_desc_area_size;
354 struct sk_buff **rx_skb;
355
356 struct net_lro_mgr lro_mgr;
357 struct net_lro_desc lro_arr[8];
358 };
359
360 struct tx_queue {
361 int index;
362
363 int tx_ring_size;
364
365 int tx_desc_count;
366 int tx_curr_desc;
367 int tx_used_desc;
368
369 struct tx_desc *tx_desc_area;
370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
372
373 struct sk_buff_head tx_skb;
374
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
378 };
379
380 struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
382 void __iomem *base;
383 int port_num;
384
385 struct net_device *dev;
386
387 struct phy_device *phy;
388
389 struct timer_list mib_counters_timer;
390 spinlock_t mib_counters_lock;
391 struct mib_counters mib_counters;
392
393 struct lro_counters lro_counters;
394
395 struct work_struct tx_timeout_task;
396
397 struct napi_struct napi;
398 u32 int_mask;
399 u8 oom;
400 u8 work_link;
401 u8 work_tx;
402 u8 work_tx_end;
403 u8 work_rx;
404 u8 work_rx_refill;
405
406 int skb_size;
407 struct sk_buff_head rx_recycle;
408
409 /*
410 * RX state.
411 */
412 int rx_ring_size;
413 unsigned long rx_desc_sram_addr;
414 int rx_desc_sram_size;
415 int rxq_count;
416 struct timer_list rx_oom;
417 struct rx_queue rxq[8];
418
419 /*
420 * TX state.
421 */
422 int tx_ring_size;
423 unsigned long tx_desc_sram_addr;
424 int tx_desc_sram_size;
425 int txq_count;
426 struct tx_queue txq[8];
427 };
428
429
430 /* port register accessors **************************************************/
431 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
432 {
433 return readl(mp->shared->base + offset);
434 }
435
436 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
437 {
438 return readl(mp->base + offset);
439 }
440
441 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
442 {
443 writel(data, mp->shared->base + offset);
444 }
445
446 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
447 {
448 writel(data, mp->base + offset);
449 }
450
451
452 /* rxq/txq helper functions *************************************************/
453 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
454 {
455 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
456 }
457
458 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
459 {
460 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
461 }
462
463 static void rxq_enable(struct rx_queue *rxq)
464 {
465 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
466 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
467 }
468
469 static void rxq_disable(struct rx_queue *rxq)
470 {
471 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
472 u8 mask = 1 << rxq->index;
473
474 wrlp(mp, RXQ_COMMAND, mask << 8);
475 while (rdlp(mp, RXQ_COMMAND) & mask)
476 udelay(10);
477 }
478
479 static void txq_reset_hw_ptr(struct tx_queue *txq)
480 {
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
482 u32 addr;
483
484 addr = (u32)txq->tx_desc_dma;
485 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
486 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
487 }
488
489 static void txq_enable(struct tx_queue *txq)
490 {
491 struct mv643xx_eth_private *mp = txq_to_mp(txq);
492 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
493 }
494
495 static void txq_disable(struct tx_queue *txq)
496 {
497 struct mv643xx_eth_private *mp = txq_to_mp(txq);
498 u8 mask = 1 << txq->index;
499
500 wrlp(mp, TXQ_COMMAND, mask << 8);
501 while (rdlp(mp, TXQ_COMMAND) & mask)
502 udelay(10);
503 }
504
505 static void txq_maybe_wake(struct tx_queue *txq)
506 {
507 struct mv643xx_eth_private *mp = txq_to_mp(txq);
508 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
509
510 if (netif_tx_queue_stopped(nq)) {
511 __netif_tx_lock(nq, smp_processor_id());
512 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
513 netif_tx_wake_queue(nq);
514 __netif_tx_unlock(nq);
515 }
516 }
517
518
519 /* rx napi ******************************************************************/
520 static int
521 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
522 u64 *hdr_flags, void *priv)
523 {
524 unsigned long cmd_sts = (unsigned long)priv;
525
526 /*
527 * Make sure that this packet is Ethernet II, is not VLAN
528 * tagged, is IPv4, has a valid IP header, and is TCP.
529 */
530 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
531 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
532 RX_PKT_IS_VLAN_TAGGED)) !=
533 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
535 return -1;
536
537 skb_reset_network_header(skb);
538 skb_set_transport_header(skb, ip_hdrlen(skb));
539 *iphdr = ip_hdr(skb);
540 *tcph = tcp_hdr(skb);
541 *hdr_flags = LRO_IPV4 | LRO_TCP;
542
543 return 0;
544 }
545
546 static int rxq_process(struct rx_queue *rxq, int budget)
547 {
548 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
549 struct net_device_stats *stats = &mp->dev->stats;
550 int lro_flush_needed;
551 int rx;
552
553 lro_flush_needed = 0;
554 rx = 0;
555 while (rx < budget && rxq->rx_desc_count) {
556 struct rx_desc *rx_desc;
557 unsigned int cmd_sts;
558 struct sk_buff *skb;
559 u16 byte_cnt;
560
561 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
562
563 cmd_sts = rx_desc->cmd_sts;
564 if (cmd_sts & BUFFER_OWNED_BY_DMA)
565 break;
566 rmb();
567
568 skb = rxq->rx_skb[rxq->rx_curr_desc];
569 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
570
571 rxq->rx_curr_desc++;
572 if (rxq->rx_curr_desc == rxq->rx_ring_size)
573 rxq->rx_curr_desc = 0;
574
575 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
576 rx_desc->buf_size, DMA_FROM_DEVICE);
577 rxq->rx_desc_count--;
578 rx++;
579
580 mp->work_rx_refill |= 1 << rxq->index;
581
582 byte_cnt = rx_desc->byte_cnt;
583
584 /*
585 * Update statistics.
586 *
587 * Note that the descriptor byte count includes 2 dummy
588 * bytes automatically inserted by the hardware at the
589 * start of the packet (which we don't count), and a 4
590 * byte CRC at the end of the packet (which we do count).
591 */
592 stats->rx_packets++;
593 stats->rx_bytes += byte_cnt - 2;
594
595 /*
596 * In case we received a packet without first / last bits
597 * on, or the error summary bit is set, the packet needs
598 * to be dropped.
599 */
600 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
601 != (RX_FIRST_DESC | RX_LAST_DESC))
602 goto err;
603
604 /*
605 * The -4 is for the CRC in the trailer of the
606 * received packet
607 */
608 skb_put(skb, byte_cnt - 2 - 4);
609
610 if (cmd_sts & LAYER_4_CHECKSUM_OK)
611 skb->ip_summed = CHECKSUM_UNNECESSARY;
612 skb->protocol = eth_type_trans(skb, mp->dev);
613
614 if (skb->dev->features & NETIF_F_LRO &&
615 skb->ip_summed == CHECKSUM_UNNECESSARY) {
616 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
617 lro_flush_needed = 1;
618 } else
619 netif_receive_skb(skb);
620
621 continue;
622
623 err:
624 stats->rx_dropped++;
625
626 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
627 (RX_FIRST_DESC | RX_LAST_DESC)) {
628 if (net_ratelimit())
629 dev_printk(KERN_ERR, &mp->dev->dev,
630 "received packet spanning "
631 "multiple descriptors\n");
632 }
633
634 if (cmd_sts & ERROR_SUMMARY)
635 stats->rx_errors++;
636
637 dev_kfree_skb(skb);
638 }
639
640 if (lro_flush_needed)
641 lro_flush_all(&rxq->lro_mgr);
642
643 if (rx < budget)
644 mp->work_rx &= ~(1 << rxq->index);
645
646 return rx;
647 }
648
649 static int rxq_refill(struct rx_queue *rxq, int budget)
650 {
651 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
652 int refilled;
653
654 refilled = 0;
655 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
656 struct sk_buff *skb;
657 int rx;
658 struct rx_desc *rx_desc;
659 int size;
660
661 skb = __skb_dequeue(&mp->rx_recycle);
662 if (skb == NULL)
663 skb = dev_alloc_skb(mp->skb_size);
664
665 if (skb == NULL) {
666 mp->oom = 1;
667 goto oom;
668 }
669
670 if (SKB_DMA_REALIGN)
671 skb_reserve(skb, SKB_DMA_REALIGN);
672
673 refilled++;
674 rxq->rx_desc_count++;
675
676 rx = rxq->rx_used_desc++;
677 if (rxq->rx_used_desc == rxq->rx_ring_size)
678 rxq->rx_used_desc = 0;
679
680 rx_desc = rxq->rx_desc_area + rx;
681
682 size = skb->end - skb->data;
683 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
684 skb->data, size,
685 DMA_FROM_DEVICE);
686 rx_desc->buf_size = size;
687 rxq->rx_skb[rx] = skb;
688 wmb();
689 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
690 wmb();
691
692 /*
693 * The hardware automatically prepends 2 bytes of
694 * dummy data to each received packet, so that the
695 * IP header ends up 16-byte aligned.
696 */
697 skb_reserve(skb, 2);
698 }
699
700 if (refilled < budget)
701 mp->work_rx_refill &= ~(1 << rxq->index);
702
703 oom:
704 return refilled;
705 }
706
707
708 /* tx ***********************************************************************/
709 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
710 {
711 int frag;
712
713 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
714 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
715 if (fragp->size <= 8 && fragp->page_offset & 7)
716 return 1;
717 }
718
719 return 0;
720 }
721
722 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
723 {
724 struct mv643xx_eth_private *mp = txq_to_mp(txq);
725 int nr_frags = skb_shinfo(skb)->nr_frags;
726 int frag;
727
728 for (frag = 0; frag < nr_frags; frag++) {
729 skb_frag_t *this_frag;
730 int tx_index;
731 struct tx_desc *desc;
732
733 this_frag = &skb_shinfo(skb)->frags[frag];
734 tx_index = txq->tx_curr_desc++;
735 if (txq->tx_curr_desc == txq->tx_ring_size)
736 txq->tx_curr_desc = 0;
737 desc = &txq->tx_desc_area[tx_index];
738
739 /*
740 * The last fragment will generate an interrupt
741 * which will free the skb on TX completion.
742 */
743 if (frag == nr_frags - 1) {
744 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
745 ZERO_PADDING | TX_LAST_DESC |
746 TX_ENABLE_INTERRUPT;
747 } else {
748 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
749 }
750
751 desc->l4i_chk = 0;
752 desc->byte_cnt = this_frag->size;
753 desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
754 this_frag->page,
755 this_frag->page_offset,
756 this_frag->size, DMA_TO_DEVICE);
757 }
758 }
759
760 static inline __be16 sum16_as_be(__sum16 sum)
761 {
762 return (__force __be16)sum;
763 }
764
765 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
766 {
767 struct mv643xx_eth_private *mp = txq_to_mp(txq);
768 int nr_frags = skb_shinfo(skb)->nr_frags;
769 int tx_index;
770 struct tx_desc *desc;
771 u32 cmd_sts;
772 u16 l4i_chk;
773 int length;
774
775 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
776 l4i_chk = 0;
777
778 if (skb->ip_summed == CHECKSUM_PARTIAL) {
779 int tag_bytes;
780
781 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
782 skb->protocol != htons(ETH_P_8021Q));
783
784 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
785 if (unlikely(tag_bytes & ~12)) {
786 if (skb_checksum_help(skb) == 0)
787 goto no_csum;
788 kfree_skb(skb);
789 return 1;
790 }
791
792 if (tag_bytes & 4)
793 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
794 if (tag_bytes & 8)
795 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
796
797 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
798 GEN_IP_V4_CHECKSUM |
799 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
800
801 switch (ip_hdr(skb)->protocol) {
802 case IPPROTO_UDP:
803 cmd_sts |= UDP_FRAME;
804 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
805 break;
806 case IPPROTO_TCP:
807 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
808 break;
809 default:
810 BUG();
811 }
812 } else {
813 no_csum:
814 /* Errata BTS #50, IHL must be 5 if no HW checksum */
815 cmd_sts |= 5 << TX_IHL_SHIFT;
816 }
817
818 tx_index = txq->tx_curr_desc++;
819 if (txq->tx_curr_desc == txq->tx_ring_size)
820 txq->tx_curr_desc = 0;
821 desc = &txq->tx_desc_area[tx_index];
822
823 if (nr_frags) {
824 txq_submit_frag_skb(txq, skb);
825 length = skb_headlen(skb);
826 } else {
827 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
828 length = skb->len;
829 }
830
831 desc->l4i_chk = l4i_chk;
832 desc->byte_cnt = length;
833 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
834 length, DMA_TO_DEVICE);
835
836 __skb_queue_tail(&txq->tx_skb, skb);
837
838 /* ensure all other descriptors are written before first cmd_sts */
839 wmb();
840 desc->cmd_sts = cmd_sts;
841
842 /* clear TX_END status */
843 mp->work_tx_end &= ~(1 << txq->index);
844
845 /* ensure all descriptors are written before poking hardware */
846 wmb();
847 txq_enable(txq);
848
849 txq->tx_desc_count += nr_frags + 1;
850
851 return 0;
852 }
853
854 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
855 {
856 struct mv643xx_eth_private *mp = netdev_priv(dev);
857 int queue;
858 struct tx_queue *txq;
859 struct netdev_queue *nq;
860
861 queue = skb_get_queue_mapping(skb);
862 txq = mp->txq + queue;
863 nq = netdev_get_tx_queue(dev, queue);
864
865 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
866 txq->tx_dropped++;
867 dev_printk(KERN_DEBUG, &dev->dev,
868 "failed to linearize skb with tiny "
869 "unaligned fragment\n");
870 return NETDEV_TX_BUSY;
871 }
872
873 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
874 if (net_ratelimit())
875 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
876 kfree_skb(skb);
877 return NETDEV_TX_OK;
878 }
879
880 if (!txq_submit_skb(txq, skb)) {
881 int entries_left;
882
883 txq->tx_bytes += skb->len;
884 txq->tx_packets++;
885
886 entries_left = txq->tx_ring_size - txq->tx_desc_count;
887 if (entries_left < MAX_SKB_FRAGS + 1)
888 netif_tx_stop_queue(nq);
889 }
890
891 return NETDEV_TX_OK;
892 }
893
894
895 /* tx napi ******************************************************************/
896 static void txq_kick(struct tx_queue *txq)
897 {
898 struct mv643xx_eth_private *mp = txq_to_mp(txq);
899 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
900 u32 hw_desc_ptr;
901 u32 expected_ptr;
902
903 __netif_tx_lock(nq, smp_processor_id());
904
905 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
906 goto out;
907
908 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
909 expected_ptr = (u32)txq->tx_desc_dma +
910 txq->tx_curr_desc * sizeof(struct tx_desc);
911
912 if (hw_desc_ptr != expected_ptr)
913 txq_enable(txq);
914
915 out:
916 __netif_tx_unlock(nq);
917
918 mp->work_tx_end &= ~(1 << txq->index);
919 }
920
921 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
922 {
923 struct mv643xx_eth_private *mp = txq_to_mp(txq);
924 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
925 int reclaimed;
926
927 __netif_tx_lock(nq, smp_processor_id());
928
929 reclaimed = 0;
930 while (reclaimed < budget && txq->tx_desc_count > 0) {
931 int tx_index;
932 struct tx_desc *desc;
933 u32 cmd_sts;
934 struct sk_buff *skb;
935
936 tx_index = txq->tx_used_desc;
937 desc = &txq->tx_desc_area[tx_index];
938 cmd_sts = desc->cmd_sts;
939
940 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
941 if (!force)
942 break;
943 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
944 }
945
946 txq->tx_used_desc = tx_index + 1;
947 if (txq->tx_used_desc == txq->tx_ring_size)
948 txq->tx_used_desc = 0;
949
950 reclaimed++;
951 txq->tx_desc_count--;
952
953 skb = NULL;
954 if (cmd_sts & TX_LAST_DESC)
955 skb = __skb_dequeue(&txq->tx_skb);
956
957 if (cmd_sts & ERROR_SUMMARY) {
958 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
959 mp->dev->stats.tx_errors++;
960 }
961
962 if (cmd_sts & TX_FIRST_DESC) {
963 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
964 desc->byte_cnt, DMA_TO_DEVICE);
965 } else {
966 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
967 desc->byte_cnt, DMA_TO_DEVICE);
968 }
969
970 if (skb != NULL) {
971 if (skb_queue_len(&mp->rx_recycle) <
972 mp->rx_ring_size &&
973 skb_recycle_check(skb, mp->skb_size))
974 __skb_queue_head(&mp->rx_recycle, skb);
975 else
976 dev_kfree_skb(skb);
977 }
978 }
979
980 __netif_tx_unlock(nq);
981
982 if (reclaimed < budget)
983 mp->work_tx &= ~(1 << txq->index);
984
985 return reclaimed;
986 }
987
988
989 /* tx rate control **********************************************************/
990 /*
991 * Set total maximum TX rate (shared by all TX queues for this port)
992 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
993 */
994 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
995 {
996 int token_rate;
997 int mtu;
998 int bucket_size;
999
1000 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1001 if (token_rate > 1023)
1002 token_rate = 1023;
1003
1004 mtu = (mp->dev->mtu + 255) >> 8;
1005 if (mtu > 63)
1006 mtu = 63;
1007
1008 bucket_size = (burst + 255) >> 8;
1009 if (bucket_size > 65535)
1010 bucket_size = 65535;
1011
1012 switch (mp->shared->tx_bw_control) {
1013 case TX_BW_CONTROL_OLD_LAYOUT:
1014 wrlp(mp, TX_BW_RATE, token_rate);
1015 wrlp(mp, TX_BW_MTU, mtu);
1016 wrlp(mp, TX_BW_BURST, bucket_size);
1017 break;
1018 case TX_BW_CONTROL_NEW_LAYOUT:
1019 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1020 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1021 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1022 break;
1023 }
1024 }
1025
1026 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1027 {
1028 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1029 int token_rate;
1030 int bucket_size;
1031
1032 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1033 if (token_rate > 1023)
1034 token_rate = 1023;
1035
1036 bucket_size = (burst + 255) >> 8;
1037 if (bucket_size > 65535)
1038 bucket_size = 65535;
1039
1040 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1041 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1042 }
1043
1044 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1045 {
1046 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1047 int off;
1048 u32 val;
1049
1050 /*
1051 * Turn on fixed priority mode.
1052 */
1053 off = 0;
1054 switch (mp->shared->tx_bw_control) {
1055 case TX_BW_CONTROL_OLD_LAYOUT:
1056 off = TXQ_FIX_PRIO_CONF;
1057 break;
1058 case TX_BW_CONTROL_NEW_LAYOUT:
1059 off = TXQ_FIX_PRIO_CONF_MOVED;
1060 break;
1061 }
1062
1063 if (off) {
1064 val = rdlp(mp, off);
1065 val |= 1 << txq->index;
1066 wrlp(mp, off, val);
1067 }
1068 }
1069
1070
1071 /* mii management interface *************************************************/
1072 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1073 {
1074 struct mv643xx_eth_shared_private *msp = dev_id;
1075
1076 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1077 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1078 wake_up(&msp->smi_busy_wait);
1079 return IRQ_HANDLED;
1080 }
1081
1082 return IRQ_NONE;
1083 }
1084
1085 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1086 {
1087 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1088 }
1089
1090 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1091 {
1092 if (msp->err_interrupt == NO_IRQ) {
1093 int i;
1094
1095 for (i = 0; !smi_is_done(msp); i++) {
1096 if (i == 10)
1097 return -ETIMEDOUT;
1098 msleep(10);
1099 }
1100
1101 return 0;
1102 }
1103
1104 if (!smi_is_done(msp)) {
1105 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1106 msecs_to_jiffies(100));
1107 if (!smi_is_done(msp))
1108 return -ETIMEDOUT;
1109 }
1110
1111 return 0;
1112 }
1113
1114 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1115 {
1116 struct mv643xx_eth_shared_private *msp = bus->priv;
1117 void __iomem *smi_reg = msp->base + SMI_REG;
1118 int ret;
1119
1120 if (smi_wait_ready(msp)) {
1121 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1122 return -ETIMEDOUT;
1123 }
1124
1125 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1126
1127 if (smi_wait_ready(msp)) {
1128 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1129 return -ETIMEDOUT;
1130 }
1131
1132 ret = readl(smi_reg);
1133 if (!(ret & SMI_READ_VALID)) {
1134 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1135 return -ENODEV;
1136 }
1137
1138 return ret & 0xffff;
1139 }
1140
1141 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1142 {
1143 struct mv643xx_eth_shared_private *msp = bus->priv;
1144 void __iomem *smi_reg = msp->base + SMI_REG;
1145
1146 if (smi_wait_ready(msp)) {
1147 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1148 return -ETIMEDOUT;
1149 }
1150
1151 writel(SMI_OPCODE_WRITE | (reg << 21) |
1152 (addr << 16) | (val & 0xffff), smi_reg);
1153
1154 if (smi_wait_ready(msp)) {
1155 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1156 return -ETIMEDOUT;
1157 }
1158
1159 return 0;
1160 }
1161
1162
1163 /* statistics ***************************************************************/
1164 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1165 {
1166 struct mv643xx_eth_private *mp = netdev_priv(dev);
1167 struct net_device_stats *stats = &dev->stats;
1168 unsigned long tx_packets = 0;
1169 unsigned long tx_bytes = 0;
1170 unsigned long tx_dropped = 0;
1171 int i;
1172
1173 for (i = 0; i < mp->txq_count; i++) {
1174 struct tx_queue *txq = mp->txq + i;
1175
1176 tx_packets += txq->tx_packets;
1177 tx_bytes += txq->tx_bytes;
1178 tx_dropped += txq->tx_dropped;
1179 }
1180
1181 stats->tx_packets = tx_packets;
1182 stats->tx_bytes = tx_bytes;
1183 stats->tx_dropped = tx_dropped;
1184
1185 return stats;
1186 }
1187
1188 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1189 {
1190 u32 lro_aggregated = 0;
1191 u32 lro_flushed = 0;
1192 u32 lro_no_desc = 0;
1193 int i;
1194
1195 for (i = 0; i < mp->rxq_count; i++) {
1196 struct rx_queue *rxq = mp->rxq + i;
1197
1198 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1199 lro_flushed += rxq->lro_mgr.stats.flushed;
1200 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1201 }
1202
1203 mp->lro_counters.lro_aggregated = lro_aggregated;
1204 mp->lro_counters.lro_flushed = lro_flushed;
1205 mp->lro_counters.lro_no_desc = lro_no_desc;
1206 }
1207
1208 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1209 {
1210 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1211 }
1212
1213 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1214 {
1215 int i;
1216
1217 for (i = 0; i < 0x80; i += 4)
1218 mib_read(mp, i);
1219 }
1220
1221 static void mib_counters_update(struct mv643xx_eth_private *mp)
1222 {
1223 struct mib_counters *p = &mp->mib_counters;
1224
1225 spin_lock_bh(&mp->mib_counters_lock);
1226 p->good_octets_received += mib_read(mp, 0x00);
1227 p->bad_octets_received += mib_read(mp, 0x08);
1228 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1229 p->good_frames_received += mib_read(mp, 0x10);
1230 p->bad_frames_received += mib_read(mp, 0x14);
1231 p->broadcast_frames_received += mib_read(mp, 0x18);
1232 p->multicast_frames_received += mib_read(mp, 0x1c);
1233 p->frames_64_octets += mib_read(mp, 0x20);
1234 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1235 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1236 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1237 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1238 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1239 p->good_octets_sent += mib_read(mp, 0x38);
1240 p->good_frames_sent += mib_read(mp, 0x40);
1241 p->excessive_collision += mib_read(mp, 0x44);
1242 p->multicast_frames_sent += mib_read(mp, 0x48);
1243 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1244 p->unrec_mac_control_received += mib_read(mp, 0x50);
1245 p->fc_sent += mib_read(mp, 0x54);
1246 p->good_fc_received += mib_read(mp, 0x58);
1247 p->bad_fc_received += mib_read(mp, 0x5c);
1248 p->undersize_received += mib_read(mp, 0x60);
1249 p->fragments_received += mib_read(mp, 0x64);
1250 p->oversize_received += mib_read(mp, 0x68);
1251 p->jabber_received += mib_read(mp, 0x6c);
1252 p->mac_receive_error += mib_read(mp, 0x70);
1253 p->bad_crc_event += mib_read(mp, 0x74);
1254 p->collision += mib_read(mp, 0x78);
1255 p->late_collision += mib_read(mp, 0x7c);
1256 spin_unlock_bh(&mp->mib_counters_lock);
1257
1258 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1259 }
1260
1261 static void mib_counters_timer_wrapper(unsigned long _mp)
1262 {
1263 struct mv643xx_eth_private *mp = (void *)_mp;
1264
1265 mib_counters_update(mp);
1266 }
1267
1268
1269 /* interrupt coalescing *****************************************************/
1270 /*
1271 * Hardware coalescing parameters are set in units of 64 t_clk
1272 * cycles. I.e.:
1273 *
1274 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1275 *
1276 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1277 *
1278 * In the ->set*() methods, we round the computed register value
1279 * to the nearest integer.
1280 */
1281 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1282 {
1283 u32 val = rdlp(mp, SDMA_CONFIG);
1284 u64 temp;
1285
1286 if (mp->shared->extended_rx_coal_limit)
1287 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1288 else
1289 temp = (val & 0x003fff00) >> 8;
1290
1291 temp *= 64000000;
1292 do_div(temp, mp->shared->t_clk);
1293
1294 return (unsigned int)temp;
1295 }
1296
1297 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1298 {
1299 u64 temp;
1300 u32 val;
1301
1302 temp = (u64)usec * mp->shared->t_clk;
1303 temp += 31999999;
1304 do_div(temp, 64000000);
1305
1306 val = rdlp(mp, SDMA_CONFIG);
1307 if (mp->shared->extended_rx_coal_limit) {
1308 if (temp > 0xffff)
1309 temp = 0xffff;
1310 val &= ~0x023fff80;
1311 val |= (temp & 0x8000) << 10;
1312 val |= (temp & 0x7fff) << 7;
1313 } else {
1314 if (temp > 0x3fff)
1315 temp = 0x3fff;
1316 val &= ~0x003fff00;
1317 val |= (temp & 0x3fff) << 8;
1318 }
1319 wrlp(mp, SDMA_CONFIG, val);
1320 }
1321
1322 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1323 {
1324 u64 temp;
1325
1326 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1327 temp *= 64000000;
1328 do_div(temp, mp->shared->t_clk);
1329
1330 return (unsigned int)temp;
1331 }
1332
1333 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1334 {
1335 u64 temp;
1336
1337 temp = (u64)usec * mp->shared->t_clk;
1338 temp += 31999999;
1339 do_div(temp, 64000000);
1340
1341 if (temp > 0x3fff)
1342 temp = 0x3fff;
1343
1344 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1345 }
1346
1347
1348 /* ethtool ******************************************************************/
1349 struct mv643xx_eth_stats {
1350 char stat_string[ETH_GSTRING_LEN];
1351 int sizeof_stat;
1352 int netdev_off;
1353 int mp_off;
1354 };
1355
1356 #define SSTAT(m) \
1357 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1358 offsetof(struct net_device, stats.m), -1 }
1359
1360 #define MIBSTAT(m) \
1361 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1362 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1363
1364 #define LROSTAT(m) \
1365 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1366 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1367
1368 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1369 SSTAT(rx_packets),
1370 SSTAT(tx_packets),
1371 SSTAT(rx_bytes),
1372 SSTAT(tx_bytes),
1373 SSTAT(rx_errors),
1374 SSTAT(tx_errors),
1375 SSTAT(rx_dropped),
1376 SSTAT(tx_dropped),
1377 MIBSTAT(good_octets_received),
1378 MIBSTAT(bad_octets_received),
1379 MIBSTAT(internal_mac_transmit_err),
1380 MIBSTAT(good_frames_received),
1381 MIBSTAT(bad_frames_received),
1382 MIBSTAT(broadcast_frames_received),
1383 MIBSTAT(multicast_frames_received),
1384 MIBSTAT(frames_64_octets),
1385 MIBSTAT(frames_65_to_127_octets),
1386 MIBSTAT(frames_128_to_255_octets),
1387 MIBSTAT(frames_256_to_511_octets),
1388 MIBSTAT(frames_512_to_1023_octets),
1389 MIBSTAT(frames_1024_to_max_octets),
1390 MIBSTAT(good_octets_sent),
1391 MIBSTAT(good_frames_sent),
1392 MIBSTAT(excessive_collision),
1393 MIBSTAT(multicast_frames_sent),
1394 MIBSTAT(broadcast_frames_sent),
1395 MIBSTAT(unrec_mac_control_received),
1396 MIBSTAT(fc_sent),
1397 MIBSTAT(good_fc_received),
1398 MIBSTAT(bad_fc_received),
1399 MIBSTAT(undersize_received),
1400 MIBSTAT(fragments_received),
1401 MIBSTAT(oversize_received),
1402 MIBSTAT(jabber_received),
1403 MIBSTAT(mac_receive_error),
1404 MIBSTAT(bad_crc_event),
1405 MIBSTAT(collision),
1406 MIBSTAT(late_collision),
1407 LROSTAT(lro_aggregated),
1408 LROSTAT(lro_flushed),
1409 LROSTAT(lro_no_desc),
1410 };
1411
1412 static int
1413 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1414 struct ethtool_cmd *cmd)
1415 {
1416 int err;
1417
1418 err = phy_read_status(mp->phy);
1419 if (err == 0)
1420 err = phy_ethtool_gset(mp->phy, cmd);
1421
1422 /*
1423 * The MAC does not support 1000baseT_Half.
1424 */
1425 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1426 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1427
1428 return err;
1429 }
1430
1431 static int
1432 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1433 struct ethtool_cmd *cmd)
1434 {
1435 u32 port_status;
1436
1437 port_status = rdlp(mp, PORT_STATUS);
1438
1439 cmd->supported = SUPPORTED_MII;
1440 cmd->advertising = ADVERTISED_MII;
1441 switch (port_status & PORT_SPEED_MASK) {
1442 case PORT_SPEED_10:
1443 cmd->speed = SPEED_10;
1444 break;
1445 case PORT_SPEED_100:
1446 cmd->speed = SPEED_100;
1447 break;
1448 case PORT_SPEED_1000:
1449 cmd->speed = SPEED_1000;
1450 break;
1451 default:
1452 cmd->speed = -1;
1453 break;
1454 }
1455 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1456 cmd->port = PORT_MII;
1457 cmd->phy_address = 0;
1458 cmd->transceiver = XCVR_INTERNAL;
1459 cmd->autoneg = AUTONEG_DISABLE;
1460 cmd->maxtxpkt = 1;
1461 cmd->maxrxpkt = 1;
1462
1463 return 0;
1464 }
1465
1466 static int
1467 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1468 {
1469 struct mv643xx_eth_private *mp = netdev_priv(dev);
1470
1471 if (mp->phy != NULL)
1472 return mv643xx_eth_get_settings_phy(mp, cmd);
1473 else
1474 return mv643xx_eth_get_settings_phyless(mp, cmd);
1475 }
1476
1477 static int
1478 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1479 {
1480 struct mv643xx_eth_private *mp = netdev_priv(dev);
1481
1482 if (mp->phy == NULL)
1483 return -EINVAL;
1484
1485 /*
1486 * The MAC does not support 1000baseT_Half.
1487 */
1488 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1489
1490 return phy_ethtool_sset(mp->phy, cmd);
1491 }
1492
1493 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1494 struct ethtool_drvinfo *drvinfo)
1495 {
1496 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1497 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1498 strncpy(drvinfo->fw_version, "N/A", 32);
1499 strncpy(drvinfo->bus_info, "platform", 32);
1500 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1501 }
1502
1503 static int mv643xx_eth_nway_reset(struct net_device *dev)
1504 {
1505 struct mv643xx_eth_private *mp = netdev_priv(dev);
1506
1507 if (mp->phy == NULL)
1508 return -EINVAL;
1509
1510 return genphy_restart_aneg(mp->phy);
1511 }
1512
1513 static u32 mv643xx_eth_get_link(struct net_device *dev)
1514 {
1515 return !!netif_carrier_ok(dev);
1516 }
1517
1518 static int
1519 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1520 {
1521 struct mv643xx_eth_private *mp = netdev_priv(dev);
1522
1523 ec->rx_coalesce_usecs = get_rx_coal(mp);
1524 ec->tx_coalesce_usecs = get_tx_coal(mp);
1525
1526 return 0;
1527 }
1528
1529 static int
1530 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1531 {
1532 struct mv643xx_eth_private *mp = netdev_priv(dev);
1533
1534 set_rx_coal(mp, ec->rx_coalesce_usecs);
1535 set_tx_coal(mp, ec->tx_coalesce_usecs);
1536
1537 return 0;
1538 }
1539
1540 static void
1541 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1542 {
1543 struct mv643xx_eth_private *mp = netdev_priv(dev);
1544
1545 er->rx_max_pending = 4096;
1546 er->tx_max_pending = 4096;
1547 er->rx_mini_max_pending = 0;
1548 er->rx_jumbo_max_pending = 0;
1549
1550 er->rx_pending = mp->rx_ring_size;
1551 er->tx_pending = mp->tx_ring_size;
1552 er->rx_mini_pending = 0;
1553 er->rx_jumbo_pending = 0;
1554 }
1555
1556 static int
1557 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1558 {
1559 struct mv643xx_eth_private *mp = netdev_priv(dev);
1560
1561 if (er->rx_mini_pending || er->rx_jumbo_pending)
1562 return -EINVAL;
1563
1564 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1565 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1566
1567 if (netif_running(dev)) {
1568 mv643xx_eth_stop(dev);
1569 if (mv643xx_eth_open(dev)) {
1570 dev_printk(KERN_ERR, &dev->dev,
1571 "fatal error on re-opening device after "
1572 "ring param change\n");
1573 return -ENOMEM;
1574 }
1575 }
1576
1577 return 0;
1578 }
1579
1580 static u32
1581 mv643xx_eth_get_rx_csum(struct net_device *dev)
1582 {
1583 struct mv643xx_eth_private *mp = netdev_priv(dev);
1584
1585 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1586 }
1587
1588 static int
1589 mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1590 {
1591 struct mv643xx_eth_private *mp = netdev_priv(dev);
1592
1593 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1594
1595 return 0;
1596 }
1597
1598 static void mv643xx_eth_get_strings(struct net_device *dev,
1599 uint32_t stringset, uint8_t *data)
1600 {
1601 int i;
1602
1603 if (stringset == ETH_SS_STATS) {
1604 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1605 memcpy(data + i * ETH_GSTRING_LEN,
1606 mv643xx_eth_stats[i].stat_string,
1607 ETH_GSTRING_LEN);
1608 }
1609 }
1610 }
1611
1612 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1613 struct ethtool_stats *stats,
1614 uint64_t *data)
1615 {
1616 struct mv643xx_eth_private *mp = netdev_priv(dev);
1617 int i;
1618
1619 mv643xx_eth_get_stats(dev);
1620 mib_counters_update(mp);
1621 mv643xx_eth_grab_lro_stats(mp);
1622
1623 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1624 const struct mv643xx_eth_stats *stat;
1625 void *p;
1626
1627 stat = mv643xx_eth_stats + i;
1628
1629 if (stat->netdev_off >= 0)
1630 p = ((void *)mp->dev) + stat->netdev_off;
1631 else
1632 p = ((void *)mp) + stat->mp_off;
1633
1634 data[i] = (stat->sizeof_stat == 8) ?
1635 *(uint64_t *)p : *(uint32_t *)p;
1636 }
1637 }
1638
1639 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1640 {
1641 if (sset == ETH_SS_STATS)
1642 return ARRAY_SIZE(mv643xx_eth_stats);
1643
1644 return -EOPNOTSUPP;
1645 }
1646
1647 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1648 .get_settings = mv643xx_eth_get_settings,
1649 .set_settings = mv643xx_eth_set_settings,
1650 .get_drvinfo = mv643xx_eth_get_drvinfo,
1651 .nway_reset = mv643xx_eth_nway_reset,
1652 .get_link = mv643xx_eth_get_link,
1653 .get_coalesce = mv643xx_eth_get_coalesce,
1654 .set_coalesce = mv643xx_eth_set_coalesce,
1655 .get_ringparam = mv643xx_eth_get_ringparam,
1656 .set_ringparam = mv643xx_eth_set_ringparam,
1657 .get_rx_csum = mv643xx_eth_get_rx_csum,
1658 .set_rx_csum = mv643xx_eth_set_rx_csum,
1659 .set_tx_csum = ethtool_op_set_tx_csum,
1660 .set_sg = ethtool_op_set_sg,
1661 .get_strings = mv643xx_eth_get_strings,
1662 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1663 .get_flags = ethtool_op_get_flags,
1664 .set_flags = ethtool_op_set_flags,
1665 .get_sset_count = mv643xx_eth_get_sset_count,
1666 };
1667
1668
1669 /* address handling *********************************************************/
1670 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1671 {
1672 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1673 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1674
1675 addr[0] = (mac_h >> 24) & 0xff;
1676 addr[1] = (mac_h >> 16) & 0xff;
1677 addr[2] = (mac_h >> 8) & 0xff;
1678 addr[3] = mac_h & 0xff;
1679 addr[4] = (mac_l >> 8) & 0xff;
1680 addr[5] = mac_l & 0xff;
1681 }
1682
1683 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1684 {
1685 wrlp(mp, MAC_ADDR_HIGH,
1686 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1687 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1688 }
1689
1690 static u32 uc_addr_filter_mask(struct net_device *dev)
1691 {
1692 struct netdev_hw_addr *ha;
1693 u32 nibbles;
1694
1695 if (dev->flags & IFF_PROMISC)
1696 return 0;
1697
1698 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1699 netdev_for_each_uc_addr(ha, dev) {
1700 if (memcmp(dev->dev_addr, ha->addr, 5))
1701 return 0;
1702 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1703 return 0;
1704
1705 nibbles |= 1 << (ha->addr[5] & 0x0f);
1706 }
1707
1708 return nibbles;
1709 }
1710
1711 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1712 {
1713 struct mv643xx_eth_private *mp = netdev_priv(dev);
1714 u32 port_config;
1715 u32 nibbles;
1716 int i;
1717
1718 uc_addr_set(mp, dev->dev_addr);
1719
1720 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1721
1722 nibbles = uc_addr_filter_mask(dev);
1723 if (!nibbles) {
1724 port_config |= UNICAST_PROMISCUOUS_MODE;
1725 nibbles = 0xffff;
1726 }
1727
1728 for (i = 0; i < 16; i += 4) {
1729 int off = UNICAST_TABLE(mp->port_num) + i;
1730 u32 v;
1731
1732 v = 0;
1733 if (nibbles & 1)
1734 v |= 0x00000001;
1735 if (nibbles & 2)
1736 v |= 0x00000100;
1737 if (nibbles & 4)
1738 v |= 0x00010000;
1739 if (nibbles & 8)
1740 v |= 0x01000000;
1741 nibbles >>= 4;
1742
1743 wrl(mp, off, v);
1744 }
1745
1746 wrlp(mp, PORT_CONFIG, port_config);
1747 }
1748
1749 static int addr_crc(unsigned char *addr)
1750 {
1751 int crc = 0;
1752 int i;
1753
1754 for (i = 0; i < 6; i++) {
1755 int j;
1756
1757 crc = (crc ^ addr[i]) << 8;
1758 for (j = 7; j >= 0; j--) {
1759 if (crc & (0x100 << j))
1760 crc ^= 0x107 << j;
1761 }
1762 }
1763
1764 return crc;
1765 }
1766
1767 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1768 {
1769 struct mv643xx_eth_private *mp = netdev_priv(dev);
1770 u32 *mc_spec;
1771 u32 *mc_other;
1772 struct netdev_hw_addr *ha;
1773 int i;
1774
1775 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1776 int port_num;
1777 u32 accept;
1778
1779 oom:
1780 port_num = mp->port_num;
1781 accept = 0x01010101;
1782 for (i = 0; i < 0x100; i += 4) {
1783 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1784 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1785 }
1786 return;
1787 }
1788
1789 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1790 if (mc_spec == NULL)
1791 goto oom;
1792 mc_other = mc_spec + (0x100 >> 2);
1793
1794 memset(mc_spec, 0, 0x100);
1795 memset(mc_other, 0, 0x100);
1796
1797 netdev_for_each_mc_addr(ha, dev) {
1798 u8 *a = ha->addr;
1799 u32 *table;
1800 int entry;
1801
1802 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1803 table = mc_spec;
1804 entry = a[5];
1805 } else {
1806 table = mc_other;
1807 entry = addr_crc(a);
1808 }
1809
1810 table[entry >> 2] |= 1 << (8 * (entry & 3));
1811 }
1812
1813 for (i = 0; i < 0x100; i += 4) {
1814 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1815 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1816 }
1817
1818 kfree(mc_spec);
1819 }
1820
1821 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1822 {
1823 mv643xx_eth_program_unicast_filter(dev);
1824 mv643xx_eth_program_multicast_filter(dev);
1825 }
1826
1827 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1828 {
1829 struct sockaddr *sa = addr;
1830
1831 if (!is_valid_ether_addr(sa->sa_data))
1832 return -EINVAL;
1833
1834 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1835
1836 netif_addr_lock_bh(dev);
1837 mv643xx_eth_program_unicast_filter(dev);
1838 netif_addr_unlock_bh(dev);
1839
1840 return 0;
1841 }
1842
1843
1844 /* rx/tx queue initialisation ***********************************************/
1845 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1846 {
1847 struct rx_queue *rxq = mp->rxq + index;
1848 struct rx_desc *rx_desc;
1849 int size;
1850 int i;
1851
1852 rxq->index = index;
1853
1854 rxq->rx_ring_size = mp->rx_ring_size;
1855
1856 rxq->rx_desc_count = 0;
1857 rxq->rx_curr_desc = 0;
1858 rxq->rx_used_desc = 0;
1859
1860 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1861
1862 if (index == 0 && size <= mp->rx_desc_sram_size) {
1863 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1864 mp->rx_desc_sram_size);
1865 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1866 } else {
1867 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1868 size, &rxq->rx_desc_dma,
1869 GFP_KERNEL);
1870 }
1871
1872 if (rxq->rx_desc_area == NULL) {
1873 dev_printk(KERN_ERR, &mp->dev->dev,
1874 "can't allocate rx ring (%d bytes)\n", size);
1875 goto out;
1876 }
1877 memset(rxq->rx_desc_area, 0, size);
1878
1879 rxq->rx_desc_area_size = size;
1880 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1881 GFP_KERNEL);
1882 if (rxq->rx_skb == NULL) {
1883 dev_printk(KERN_ERR, &mp->dev->dev,
1884 "can't allocate rx skb ring\n");
1885 goto out_free;
1886 }
1887
1888 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1889 for (i = 0; i < rxq->rx_ring_size; i++) {
1890 int nexti;
1891
1892 nexti = i + 1;
1893 if (nexti == rxq->rx_ring_size)
1894 nexti = 0;
1895
1896 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1897 nexti * sizeof(struct rx_desc);
1898 }
1899
1900 rxq->lro_mgr.dev = mp->dev;
1901 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1902 rxq->lro_mgr.features = LRO_F_NAPI;
1903 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1904 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1905 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1906 rxq->lro_mgr.max_aggr = 32;
1907 rxq->lro_mgr.frag_align_pad = 0;
1908 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1909 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1910
1911 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1912
1913 return 0;
1914
1915
1916 out_free:
1917 if (index == 0 && size <= mp->rx_desc_sram_size)
1918 iounmap(rxq->rx_desc_area);
1919 else
1920 dma_free_coherent(mp->dev->dev.parent, size,
1921 rxq->rx_desc_area,
1922 rxq->rx_desc_dma);
1923
1924 out:
1925 return -ENOMEM;
1926 }
1927
1928 static void rxq_deinit(struct rx_queue *rxq)
1929 {
1930 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1931 int i;
1932
1933 rxq_disable(rxq);
1934
1935 for (i = 0; i < rxq->rx_ring_size; i++) {
1936 if (rxq->rx_skb[i]) {
1937 dev_kfree_skb(rxq->rx_skb[i]);
1938 rxq->rx_desc_count--;
1939 }
1940 }
1941
1942 if (rxq->rx_desc_count) {
1943 dev_printk(KERN_ERR, &mp->dev->dev,
1944 "error freeing rx ring -- %d skbs stuck\n",
1945 rxq->rx_desc_count);
1946 }
1947
1948 if (rxq->index == 0 &&
1949 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1950 iounmap(rxq->rx_desc_area);
1951 else
1952 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1953 rxq->rx_desc_area, rxq->rx_desc_dma);
1954
1955 kfree(rxq->rx_skb);
1956 }
1957
1958 static int txq_init(struct mv643xx_eth_private *mp, int index)
1959 {
1960 struct tx_queue *txq = mp->txq + index;
1961 struct tx_desc *tx_desc;
1962 int size;
1963 int i;
1964
1965 txq->index = index;
1966
1967 txq->tx_ring_size = mp->tx_ring_size;
1968
1969 txq->tx_desc_count = 0;
1970 txq->tx_curr_desc = 0;
1971 txq->tx_used_desc = 0;
1972
1973 size = txq->tx_ring_size * sizeof(struct tx_desc);
1974
1975 if (index == 0 && size <= mp->tx_desc_sram_size) {
1976 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1977 mp->tx_desc_sram_size);
1978 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1979 } else {
1980 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1981 size, &txq->tx_desc_dma,
1982 GFP_KERNEL);
1983 }
1984
1985 if (txq->tx_desc_area == NULL) {
1986 dev_printk(KERN_ERR, &mp->dev->dev,
1987 "can't allocate tx ring (%d bytes)\n", size);
1988 return -ENOMEM;
1989 }
1990 memset(txq->tx_desc_area, 0, size);
1991
1992 txq->tx_desc_area_size = size;
1993
1994 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1995 for (i = 0; i < txq->tx_ring_size; i++) {
1996 struct tx_desc *txd = tx_desc + i;
1997 int nexti;
1998
1999 nexti = i + 1;
2000 if (nexti == txq->tx_ring_size)
2001 nexti = 0;
2002
2003 txd->cmd_sts = 0;
2004 txd->next_desc_ptr = txq->tx_desc_dma +
2005 nexti * sizeof(struct tx_desc);
2006 }
2007
2008 skb_queue_head_init(&txq->tx_skb);
2009
2010 return 0;
2011 }
2012
2013 static void txq_deinit(struct tx_queue *txq)
2014 {
2015 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2016
2017 txq_disable(txq);
2018 txq_reclaim(txq, txq->tx_ring_size, 1);
2019
2020 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2021
2022 if (txq->index == 0 &&
2023 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2024 iounmap(txq->tx_desc_area);
2025 else
2026 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2027 txq->tx_desc_area, txq->tx_desc_dma);
2028 }
2029
2030
2031 /* netdev ops and related ***************************************************/
2032 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2033 {
2034 u32 int_cause;
2035 u32 int_cause_ext;
2036
2037 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2038 if (int_cause == 0)
2039 return 0;
2040
2041 int_cause_ext = 0;
2042 if (int_cause & INT_EXT) {
2043 int_cause &= ~INT_EXT;
2044 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2045 }
2046
2047 if (int_cause) {
2048 wrlp(mp, INT_CAUSE, ~int_cause);
2049 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2050 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2051 mp->work_rx |= (int_cause & INT_RX) >> 2;
2052 }
2053
2054 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2055 if (int_cause_ext) {
2056 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2057 if (int_cause_ext & INT_EXT_LINK_PHY)
2058 mp->work_link = 1;
2059 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2060 }
2061
2062 return 1;
2063 }
2064
2065 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2066 {
2067 struct net_device *dev = (struct net_device *)dev_id;
2068 struct mv643xx_eth_private *mp = netdev_priv(dev);
2069
2070 if (unlikely(!mv643xx_eth_collect_events(mp)))
2071 return IRQ_NONE;
2072
2073 wrlp(mp, INT_MASK, 0);
2074 napi_schedule(&mp->napi);
2075
2076 return IRQ_HANDLED;
2077 }
2078
2079 static void handle_link_event(struct mv643xx_eth_private *mp)
2080 {
2081 struct net_device *dev = mp->dev;
2082 u32 port_status;
2083 int speed;
2084 int duplex;
2085 int fc;
2086
2087 port_status = rdlp(mp, PORT_STATUS);
2088 if (!(port_status & LINK_UP)) {
2089 if (netif_carrier_ok(dev)) {
2090 int i;
2091
2092 printk(KERN_INFO "%s: link down\n", dev->name);
2093
2094 netif_carrier_off(dev);
2095
2096 for (i = 0; i < mp->txq_count; i++) {
2097 struct tx_queue *txq = mp->txq + i;
2098
2099 txq_reclaim(txq, txq->tx_ring_size, 1);
2100 txq_reset_hw_ptr(txq);
2101 }
2102 }
2103 return;
2104 }
2105
2106 switch (port_status & PORT_SPEED_MASK) {
2107 case PORT_SPEED_10:
2108 speed = 10;
2109 break;
2110 case PORT_SPEED_100:
2111 speed = 100;
2112 break;
2113 case PORT_SPEED_1000:
2114 speed = 1000;
2115 break;
2116 default:
2117 speed = -1;
2118 break;
2119 }
2120 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2121 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2122
2123 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2124 "flow control %sabled\n", dev->name,
2125 speed, duplex ? "full" : "half",
2126 fc ? "en" : "dis");
2127
2128 if (!netif_carrier_ok(dev))
2129 netif_carrier_on(dev);
2130 }
2131
2132 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2133 {
2134 struct mv643xx_eth_private *mp;
2135 int work_done;
2136
2137 mp = container_of(napi, struct mv643xx_eth_private, napi);
2138
2139 if (unlikely(mp->oom)) {
2140 mp->oom = 0;
2141 del_timer(&mp->rx_oom);
2142 }
2143
2144 work_done = 0;
2145 while (work_done < budget) {
2146 u8 queue_mask;
2147 int queue;
2148 int work_tbd;
2149
2150 if (mp->work_link) {
2151 mp->work_link = 0;
2152 handle_link_event(mp);
2153 work_done++;
2154 continue;
2155 }
2156
2157 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2158 if (likely(!mp->oom))
2159 queue_mask |= mp->work_rx_refill;
2160
2161 if (!queue_mask) {
2162 if (mv643xx_eth_collect_events(mp))
2163 continue;
2164 break;
2165 }
2166
2167 queue = fls(queue_mask) - 1;
2168 queue_mask = 1 << queue;
2169
2170 work_tbd = budget - work_done;
2171 if (work_tbd > 16)
2172 work_tbd = 16;
2173
2174 if (mp->work_tx_end & queue_mask) {
2175 txq_kick(mp->txq + queue);
2176 } else if (mp->work_tx & queue_mask) {
2177 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2178 txq_maybe_wake(mp->txq + queue);
2179 } else if (mp->work_rx & queue_mask) {
2180 work_done += rxq_process(mp->rxq + queue, work_tbd);
2181 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2182 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2183 } else {
2184 BUG();
2185 }
2186 }
2187
2188 if (work_done < budget) {
2189 if (mp->oom)
2190 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2191 napi_complete(napi);
2192 wrlp(mp, INT_MASK, mp->int_mask);
2193 }
2194
2195 return work_done;
2196 }
2197
2198 static inline void oom_timer_wrapper(unsigned long data)
2199 {
2200 struct mv643xx_eth_private *mp = (void *)data;
2201
2202 napi_schedule(&mp->napi);
2203 }
2204
2205 static void phy_reset(struct mv643xx_eth_private *mp)
2206 {
2207 int data;
2208
2209 data = phy_read(mp->phy, MII_BMCR);
2210 if (data < 0)
2211 return;
2212
2213 data |= BMCR_RESET;
2214 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2215 return;
2216
2217 do {
2218 data = phy_read(mp->phy, MII_BMCR);
2219 } while (data >= 0 && data & BMCR_RESET);
2220 }
2221
2222 static void port_start(struct mv643xx_eth_private *mp)
2223 {
2224 u32 pscr;
2225 int i;
2226
2227 /*
2228 * Perform PHY reset, if there is a PHY.
2229 */
2230 if (mp->phy != NULL) {
2231 struct ethtool_cmd cmd;
2232
2233 mv643xx_eth_get_settings(mp->dev, &cmd);
2234 phy_reset(mp);
2235 mv643xx_eth_set_settings(mp->dev, &cmd);
2236 }
2237
2238 /*
2239 * Configure basic link parameters.
2240 */
2241 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2242
2243 pscr |= SERIAL_PORT_ENABLE;
2244 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2245
2246 pscr |= DO_NOT_FORCE_LINK_FAIL;
2247 if (mp->phy == NULL)
2248 pscr |= FORCE_LINK_PASS;
2249 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2250
2251 /*
2252 * Configure TX path and queues.
2253 */
2254 tx_set_rate(mp, 1000000000, 16777216);
2255 for (i = 0; i < mp->txq_count; i++) {
2256 struct tx_queue *txq = mp->txq + i;
2257
2258 txq_reset_hw_ptr(txq);
2259 txq_set_rate(txq, 1000000000, 16777216);
2260 txq_set_fixed_prio_mode(txq);
2261 }
2262
2263 /*
2264 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2265 * frames to RX queue #0, and include the pseudo-header when
2266 * calculating receive checksums.
2267 */
2268 wrlp(mp, PORT_CONFIG, 0x02000000);
2269
2270 /*
2271 * Treat BPDUs as normal multicasts, and disable partition mode.
2272 */
2273 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2274
2275 /*
2276 * Add configured unicast addresses to address filter table.
2277 */
2278 mv643xx_eth_program_unicast_filter(mp->dev);
2279
2280 /*
2281 * Enable the receive queues.
2282 */
2283 for (i = 0; i < mp->rxq_count; i++) {
2284 struct rx_queue *rxq = mp->rxq + i;
2285 u32 addr;
2286
2287 addr = (u32)rxq->rx_desc_dma;
2288 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2289 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2290
2291 rxq_enable(rxq);
2292 }
2293 }
2294
2295 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2296 {
2297 int skb_size;
2298
2299 /*
2300 * Reserve 2+14 bytes for an ethernet header (the hardware
2301 * automatically prepends 2 bytes of dummy data to each
2302 * received packet), 16 bytes for up to four VLAN tags, and
2303 * 4 bytes for the trailing FCS -- 36 bytes total.
2304 */
2305 skb_size = mp->dev->mtu + 36;
2306
2307 /*
2308 * Make sure that the skb size is a multiple of 8 bytes, as
2309 * the lower three bits of the receive descriptor's buffer
2310 * size field are ignored by the hardware.
2311 */
2312 mp->skb_size = (skb_size + 7) & ~7;
2313
2314 /*
2315 * If NET_SKB_PAD is smaller than a cache line,
2316 * netdev_alloc_skb() will cause skb->data to be misaligned
2317 * to a cache line boundary. If this is the case, include
2318 * some extra space to allow re-aligning the data area.
2319 */
2320 mp->skb_size += SKB_DMA_REALIGN;
2321 }
2322
2323 static int mv643xx_eth_open(struct net_device *dev)
2324 {
2325 struct mv643xx_eth_private *mp = netdev_priv(dev);
2326 int err;
2327 int i;
2328
2329 wrlp(mp, INT_CAUSE, 0);
2330 wrlp(mp, INT_CAUSE_EXT, 0);
2331 rdlp(mp, INT_CAUSE_EXT);
2332
2333 err = request_irq(dev->irq, mv643xx_eth_irq,
2334 IRQF_SHARED, dev->name, dev);
2335 if (err) {
2336 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2337 return -EAGAIN;
2338 }
2339
2340 mv643xx_eth_recalc_skb_size(mp);
2341
2342 napi_enable(&mp->napi);
2343
2344 skb_queue_head_init(&mp->rx_recycle);
2345
2346 mp->int_mask = INT_EXT;
2347
2348 for (i = 0; i < mp->rxq_count; i++) {
2349 err = rxq_init(mp, i);
2350 if (err) {
2351 while (--i >= 0)
2352 rxq_deinit(mp->rxq + i);
2353 goto out;
2354 }
2355
2356 rxq_refill(mp->rxq + i, INT_MAX);
2357 mp->int_mask |= INT_RX_0 << i;
2358 }
2359
2360 if (mp->oom) {
2361 mp->rx_oom.expires = jiffies + (HZ / 10);
2362 add_timer(&mp->rx_oom);
2363 }
2364
2365 for (i = 0; i < mp->txq_count; i++) {
2366 err = txq_init(mp, i);
2367 if (err) {
2368 while (--i >= 0)
2369 txq_deinit(mp->txq + i);
2370 goto out_free;
2371 }
2372 mp->int_mask |= INT_TX_END_0 << i;
2373 }
2374
2375 port_start(mp);
2376
2377 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2378 wrlp(mp, INT_MASK, mp->int_mask);
2379
2380 return 0;
2381
2382
2383 out_free:
2384 for (i = 0; i < mp->rxq_count; i++)
2385 rxq_deinit(mp->rxq + i);
2386 out:
2387 free_irq(dev->irq, dev);
2388
2389 return err;
2390 }
2391
2392 static void port_reset(struct mv643xx_eth_private *mp)
2393 {
2394 unsigned int data;
2395 int i;
2396
2397 for (i = 0; i < mp->rxq_count; i++)
2398 rxq_disable(mp->rxq + i);
2399 for (i = 0; i < mp->txq_count; i++)
2400 txq_disable(mp->txq + i);
2401
2402 while (1) {
2403 u32 ps = rdlp(mp, PORT_STATUS);
2404
2405 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2406 break;
2407 udelay(10);
2408 }
2409
2410 /* Reset the Enable bit in the Configuration Register */
2411 data = rdlp(mp, PORT_SERIAL_CONTROL);
2412 data &= ~(SERIAL_PORT_ENABLE |
2413 DO_NOT_FORCE_LINK_FAIL |
2414 FORCE_LINK_PASS);
2415 wrlp(mp, PORT_SERIAL_CONTROL, data);
2416 }
2417
2418 static int mv643xx_eth_stop(struct net_device *dev)
2419 {
2420 struct mv643xx_eth_private *mp = netdev_priv(dev);
2421 int i;
2422
2423 wrlp(mp, INT_MASK_EXT, 0x00000000);
2424 wrlp(mp, INT_MASK, 0x00000000);
2425 rdlp(mp, INT_MASK);
2426
2427 napi_disable(&mp->napi);
2428
2429 del_timer_sync(&mp->rx_oom);
2430
2431 netif_carrier_off(dev);
2432
2433 free_irq(dev->irq, dev);
2434
2435 port_reset(mp);
2436 mv643xx_eth_get_stats(dev);
2437 mib_counters_update(mp);
2438 del_timer_sync(&mp->mib_counters_timer);
2439
2440 skb_queue_purge(&mp->rx_recycle);
2441
2442 for (i = 0; i < mp->rxq_count; i++)
2443 rxq_deinit(mp->rxq + i);
2444 for (i = 0; i < mp->txq_count; i++)
2445 txq_deinit(mp->txq + i);
2446
2447 return 0;
2448 }
2449
2450 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2451 {
2452 struct mv643xx_eth_private *mp = netdev_priv(dev);
2453
2454 if (mp->phy != NULL)
2455 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2456
2457 return -EOPNOTSUPP;
2458 }
2459
2460 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2461 {
2462 struct mv643xx_eth_private *mp = netdev_priv(dev);
2463
2464 if (new_mtu < 64 || new_mtu > 9500)
2465 return -EINVAL;
2466
2467 dev->mtu = new_mtu;
2468 mv643xx_eth_recalc_skb_size(mp);
2469 tx_set_rate(mp, 1000000000, 16777216);
2470
2471 if (!netif_running(dev))
2472 return 0;
2473
2474 /*
2475 * Stop and then re-open the interface. This will allocate RX
2476 * skbs of the new MTU.
2477 * There is a possible danger that the open will not succeed,
2478 * due to memory being full.
2479 */
2480 mv643xx_eth_stop(dev);
2481 if (mv643xx_eth_open(dev)) {
2482 dev_printk(KERN_ERR, &dev->dev,
2483 "fatal error on re-opening device after "
2484 "MTU change\n");
2485 }
2486
2487 return 0;
2488 }
2489
2490 static void tx_timeout_task(struct work_struct *ugly)
2491 {
2492 struct mv643xx_eth_private *mp;
2493
2494 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2495 if (netif_running(mp->dev)) {
2496 netif_tx_stop_all_queues(mp->dev);
2497 port_reset(mp);
2498 port_start(mp);
2499 netif_tx_wake_all_queues(mp->dev);
2500 }
2501 }
2502
2503 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2504 {
2505 struct mv643xx_eth_private *mp = netdev_priv(dev);
2506
2507 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2508
2509 schedule_work(&mp->tx_timeout_task);
2510 }
2511
2512 #ifdef CONFIG_NET_POLL_CONTROLLER
2513 static void mv643xx_eth_netpoll(struct net_device *dev)
2514 {
2515 struct mv643xx_eth_private *mp = netdev_priv(dev);
2516
2517 wrlp(mp, INT_MASK, 0x00000000);
2518 rdlp(mp, INT_MASK);
2519
2520 mv643xx_eth_irq(dev->irq, dev);
2521
2522 wrlp(mp, INT_MASK, mp->int_mask);
2523 }
2524 #endif
2525
2526
2527 /* platform glue ************************************************************/
2528 static void
2529 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2530 struct mbus_dram_target_info *dram)
2531 {
2532 void __iomem *base = msp->base;
2533 u32 win_enable;
2534 u32 win_protect;
2535 int i;
2536
2537 for (i = 0; i < 6; i++) {
2538 writel(0, base + WINDOW_BASE(i));
2539 writel(0, base + WINDOW_SIZE(i));
2540 if (i < 4)
2541 writel(0, base + WINDOW_REMAP_HIGH(i));
2542 }
2543
2544 win_enable = 0x3f;
2545 win_protect = 0;
2546
2547 for (i = 0; i < dram->num_cs; i++) {
2548 struct mbus_dram_window *cs = dram->cs + i;
2549
2550 writel((cs->base & 0xffff0000) |
2551 (cs->mbus_attr << 8) |
2552 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2553 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2554
2555 win_enable &= ~(1 << i);
2556 win_protect |= 3 << (2 * i);
2557 }
2558
2559 writel(win_enable, base + WINDOW_BAR_ENABLE);
2560 msp->win_protect = win_protect;
2561 }
2562
2563 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2564 {
2565 /*
2566 * Check whether we have a 14-bit coal limit field in bits
2567 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2568 * SDMA config register.
2569 */
2570 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2571 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2572 msp->extended_rx_coal_limit = 1;
2573 else
2574 msp->extended_rx_coal_limit = 0;
2575
2576 /*
2577 * Check whether the MAC supports TX rate control, and if
2578 * yes, whether its associated registers are in the old or
2579 * the new place.
2580 */
2581 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2582 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2583 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2584 } else {
2585 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2586 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2587 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2588 else
2589 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2590 }
2591 }
2592
2593 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2594 {
2595 static int mv643xx_eth_version_printed;
2596 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2597 struct mv643xx_eth_shared_private *msp;
2598 struct resource *res;
2599 int ret;
2600
2601 if (!mv643xx_eth_version_printed++)
2602 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2603 "driver version %s\n", mv643xx_eth_driver_version);
2604
2605 ret = -EINVAL;
2606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2607 if (res == NULL)
2608 goto out;
2609
2610 ret = -ENOMEM;
2611 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
2612 if (msp == NULL)
2613 goto out;
2614
2615 msp->base = ioremap(res->start, res->end - res->start + 1);
2616 if (msp->base == NULL)
2617 goto out_free;
2618
2619 /*
2620 * Set up and register SMI bus.
2621 */
2622 if (pd == NULL || pd->shared_smi == NULL) {
2623 msp->smi_bus = mdiobus_alloc();
2624 if (msp->smi_bus == NULL)
2625 goto out_unmap;
2626
2627 msp->smi_bus->priv = msp;
2628 msp->smi_bus->name = "mv643xx_eth smi";
2629 msp->smi_bus->read = smi_bus_read;
2630 msp->smi_bus->write = smi_bus_write,
2631 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2632 msp->smi_bus->parent = &pdev->dev;
2633 msp->smi_bus->phy_mask = 0xffffffff;
2634 if (mdiobus_register(msp->smi_bus) < 0)
2635 goto out_free_mii_bus;
2636 msp->smi = msp;
2637 } else {
2638 msp->smi = platform_get_drvdata(pd->shared_smi);
2639 }
2640
2641 msp->err_interrupt = NO_IRQ;
2642 init_waitqueue_head(&msp->smi_busy_wait);
2643
2644 /*
2645 * Check whether the error interrupt is hooked up.
2646 */
2647 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2648 if (res != NULL) {
2649 int err;
2650
2651 err = request_irq(res->start, mv643xx_eth_err_irq,
2652 IRQF_SHARED, "mv643xx_eth", msp);
2653 if (!err) {
2654 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2655 msp->err_interrupt = res->start;
2656 }
2657 }
2658
2659 /*
2660 * (Re-)program MBUS remapping windows if we are asked to.
2661 */
2662 if (pd != NULL && pd->dram != NULL)
2663 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2664
2665 /*
2666 * Detect hardware parameters.
2667 */
2668 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2669 infer_hw_params(msp);
2670
2671 platform_set_drvdata(pdev, msp);
2672
2673 return 0;
2674
2675 out_free_mii_bus:
2676 mdiobus_free(msp->smi_bus);
2677 out_unmap:
2678 iounmap(msp->base);
2679 out_free:
2680 kfree(msp);
2681 out:
2682 return ret;
2683 }
2684
2685 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2686 {
2687 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2688 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2689
2690 if (pd == NULL || pd->shared_smi == NULL) {
2691 mdiobus_unregister(msp->smi_bus);
2692 mdiobus_free(msp->smi_bus);
2693 }
2694 if (msp->err_interrupt != NO_IRQ)
2695 free_irq(msp->err_interrupt, msp);
2696 iounmap(msp->base);
2697 kfree(msp);
2698
2699 return 0;
2700 }
2701
2702 static struct platform_driver mv643xx_eth_shared_driver = {
2703 .probe = mv643xx_eth_shared_probe,
2704 .remove = mv643xx_eth_shared_remove,
2705 .driver = {
2706 .name = MV643XX_ETH_SHARED_NAME,
2707 .owner = THIS_MODULE,
2708 },
2709 };
2710
2711 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2712 {
2713 int addr_shift = 5 * mp->port_num;
2714 u32 data;
2715
2716 data = rdl(mp, PHY_ADDR);
2717 data &= ~(0x1f << addr_shift);
2718 data |= (phy_addr & 0x1f) << addr_shift;
2719 wrl(mp, PHY_ADDR, data);
2720 }
2721
2722 static int phy_addr_get(struct mv643xx_eth_private *mp)
2723 {
2724 unsigned int data;
2725
2726 data = rdl(mp, PHY_ADDR);
2727
2728 return (data >> (5 * mp->port_num)) & 0x1f;
2729 }
2730
2731 static void set_params(struct mv643xx_eth_private *mp,
2732 struct mv643xx_eth_platform_data *pd)
2733 {
2734 struct net_device *dev = mp->dev;
2735
2736 if (is_valid_ether_addr(pd->mac_addr))
2737 memcpy(dev->dev_addr, pd->mac_addr, 6);
2738 else
2739 uc_addr_get(mp, dev->dev_addr);
2740
2741 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2742 if (pd->rx_queue_size)
2743 mp->rx_ring_size = pd->rx_queue_size;
2744 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2745 mp->rx_desc_sram_size = pd->rx_sram_size;
2746
2747 mp->rxq_count = pd->rx_queue_count ? : 1;
2748
2749 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2750 if (pd->tx_queue_size)
2751 mp->tx_ring_size = pd->tx_queue_size;
2752 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2753 mp->tx_desc_sram_size = pd->tx_sram_size;
2754
2755 mp->txq_count = pd->tx_queue_count ? : 1;
2756 }
2757
2758 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2759 int phy_addr)
2760 {
2761 struct mii_bus *bus = mp->shared->smi->smi_bus;
2762 struct phy_device *phydev;
2763 int start;
2764 int num;
2765 int i;
2766
2767 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2768 start = phy_addr_get(mp) & 0x1f;
2769 num = 32;
2770 } else {
2771 start = phy_addr & 0x1f;
2772 num = 1;
2773 }
2774
2775 phydev = NULL;
2776 for (i = 0; i < num; i++) {
2777 int addr = (start + i) & 0x1f;
2778
2779 if (bus->phy_map[addr] == NULL)
2780 mdiobus_scan(bus, addr);
2781
2782 if (phydev == NULL) {
2783 phydev = bus->phy_map[addr];
2784 if (phydev != NULL)
2785 phy_addr_set(mp, addr);
2786 }
2787 }
2788
2789 return phydev;
2790 }
2791
2792 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2793 {
2794 struct phy_device *phy = mp->phy;
2795
2796 phy_reset(mp);
2797
2798 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2799
2800 if (speed == 0) {
2801 phy->autoneg = AUTONEG_ENABLE;
2802 phy->speed = 0;
2803 phy->duplex = 0;
2804 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2805 } else {
2806 phy->autoneg = AUTONEG_DISABLE;
2807 phy->advertising = 0;
2808 phy->speed = speed;
2809 phy->duplex = duplex;
2810 }
2811 phy_start_aneg(phy);
2812 }
2813
2814 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2815 {
2816 u32 pscr;
2817
2818 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2819 if (pscr & SERIAL_PORT_ENABLE) {
2820 pscr &= ~SERIAL_PORT_ENABLE;
2821 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2822 }
2823
2824 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2825 if (mp->phy == NULL) {
2826 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2827 if (speed == SPEED_1000)
2828 pscr |= SET_GMII_SPEED_TO_1000;
2829 else if (speed == SPEED_100)
2830 pscr |= SET_MII_SPEED_TO_100;
2831
2832 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2833
2834 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2835 if (duplex == DUPLEX_FULL)
2836 pscr |= SET_FULL_DUPLEX_MODE;
2837 }
2838
2839 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2840 }
2841
2842 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2843 .ndo_open = mv643xx_eth_open,
2844 .ndo_stop = mv643xx_eth_stop,
2845 .ndo_start_xmit = mv643xx_eth_xmit,
2846 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2847 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2848 .ndo_validate_addr = eth_validate_addr,
2849 .ndo_do_ioctl = mv643xx_eth_ioctl,
2850 .ndo_change_mtu = mv643xx_eth_change_mtu,
2851 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2852 .ndo_get_stats = mv643xx_eth_get_stats,
2853 #ifdef CONFIG_NET_POLL_CONTROLLER
2854 .ndo_poll_controller = mv643xx_eth_netpoll,
2855 #endif
2856 };
2857
2858 static int mv643xx_eth_probe(struct platform_device *pdev)
2859 {
2860 struct mv643xx_eth_platform_data *pd;
2861 struct mv643xx_eth_private *mp;
2862 struct net_device *dev;
2863 struct resource *res;
2864 int err;
2865
2866 pd = pdev->dev.platform_data;
2867 if (pd == NULL) {
2868 dev_printk(KERN_ERR, &pdev->dev,
2869 "no mv643xx_eth_platform_data\n");
2870 return -ENODEV;
2871 }
2872
2873 if (pd->shared == NULL) {
2874 dev_printk(KERN_ERR, &pdev->dev,
2875 "no mv643xx_eth_platform_data->shared\n");
2876 return -ENODEV;
2877 }
2878
2879 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2880 if (!dev)
2881 return -ENOMEM;
2882
2883 mp = netdev_priv(dev);
2884 platform_set_drvdata(pdev, mp);
2885
2886 mp->shared = platform_get_drvdata(pd->shared);
2887 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2888 mp->port_num = pd->port_number;
2889
2890 mp->dev = dev;
2891
2892 set_params(mp, pd);
2893 dev->real_num_tx_queues = mp->txq_count;
2894
2895 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2896 mp->phy = phy_scan(mp, pd->phy_addr);
2897
2898 if (mp->phy != NULL)
2899 phy_init(mp, pd->speed, pd->duplex);
2900
2901 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2902
2903 init_pscr(mp, pd->speed, pd->duplex);
2904
2905
2906 mib_counters_clear(mp);
2907
2908 init_timer(&mp->mib_counters_timer);
2909 mp->mib_counters_timer.data = (unsigned long)mp;
2910 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2911 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2912 add_timer(&mp->mib_counters_timer);
2913
2914 spin_lock_init(&mp->mib_counters_lock);
2915
2916 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2917
2918 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2919
2920 init_timer(&mp->rx_oom);
2921 mp->rx_oom.data = (unsigned long)mp;
2922 mp->rx_oom.function = oom_timer_wrapper;
2923
2924
2925 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2926 BUG_ON(!res);
2927 dev->irq = res->start;
2928
2929 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2930
2931 dev->watchdog_timeo = 2 * HZ;
2932 dev->base_addr = 0;
2933
2934 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2935 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2936
2937 SET_NETDEV_DEV(dev, &pdev->dev);
2938
2939 if (mp->shared->win_protect)
2940 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2941
2942 netif_carrier_off(dev);
2943
2944 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2945
2946 set_rx_coal(mp, 250);
2947 set_tx_coal(mp, 0);
2948
2949 err = register_netdev(dev);
2950 if (err)
2951 goto out;
2952
2953 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2954 mp->port_num, dev->dev_addr);
2955
2956 if (mp->tx_desc_sram_size > 0)
2957 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2958
2959 return 0;
2960
2961 out:
2962 free_netdev(dev);
2963
2964 return err;
2965 }
2966
2967 static int mv643xx_eth_remove(struct platform_device *pdev)
2968 {
2969 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2970
2971 unregister_netdev(mp->dev);
2972 if (mp->phy != NULL)
2973 phy_detach(mp->phy);
2974 flush_scheduled_work();
2975 free_netdev(mp->dev);
2976
2977 platform_set_drvdata(pdev, NULL);
2978
2979 return 0;
2980 }
2981
2982 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2983 {
2984 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2985
2986 /* Mask all interrupts on ethernet port */
2987 wrlp(mp, INT_MASK, 0);
2988 rdlp(mp, INT_MASK);
2989
2990 if (netif_running(mp->dev))
2991 port_reset(mp);
2992 }
2993
2994 static struct platform_driver mv643xx_eth_driver = {
2995 .probe = mv643xx_eth_probe,
2996 .remove = mv643xx_eth_remove,
2997 .shutdown = mv643xx_eth_shutdown,
2998 .driver = {
2999 .name = MV643XX_ETH_NAME,
3000 .owner = THIS_MODULE,
3001 },
3002 };
3003
3004 static int __init mv643xx_eth_init_module(void)
3005 {
3006 int rc;
3007
3008 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3009 if (!rc) {
3010 rc = platform_driver_register(&mv643xx_eth_driver);
3011 if (rc)
3012 platform_driver_unregister(&mv643xx_eth_shared_driver);
3013 }
3014
3015 return rc;
3016 }
3017 module_init(mv643xx_eth_init_module);
3018
3019 static void __exit mv643xx_eth_cleanup_module(void)
3020 {
3021 platform_driver_unregister(&mv643xx_eth_driver);
3022 platform_driver_unregister(&mv643xx_eth_shared_driver);
3023 }
3024 module_exit(mv643xx_eth_cleanup_module);
3025
3026 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3027 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3028 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3029 MODULE_LICENSE("GPL");
3030 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3031 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux with added FPC-III support