arch/microblaze/include/asm/pci-bridge.h

   1 #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
   2 #define _ASM_MICROBLAZE_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13
  14 struct device_node;
  15
  16 #ifdef CONFIG_PCI
  17 extern struct list_head hose_list;
  18 extern int pcibios_vaddr_is_ioport(void __iomem *address);
  19 #else
  20 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
  21 {
  22         return 0;
  23 }
  24 #endif
  25
  26 /*
  27  * Structure of a PCI controller (host bridge)
  28  */
  29 struct pci_controller {
  30         struct pci_bus *bus;
  31         char is_dynamic;
  32         struct device_node *dn;
  33         struct list_head list_node;
  34         struct device *parent;
  35
  36         int first_busno;
  37         int last_busno;
  38
  39         int self_busno;
  40
  41         void __iomem *io_base_virt;
  42         resource_size_t io_base_phys;
  43
  44         resource_size_t pci_io_size;
  45
  46         /* Some machines (PReP) have a non 1:1 mapping of
  47          * the PCI memory space in the CPU bus space
  48          */
  49         resource_size_t pci_mem_offset;
  50
  51         /* Some machines have a special region to forward the ISA
  52          * "memory" cycles such as VGA memory regions. Left to 0
  53          * if unsupported
  54          */
  55         resource_size_t isa_mem_phys;
  56         resource_size_t isa_mem_size;
  57
  58         struct pci_ops *ops;
  59         unsigned int __iomem *cfg_addr;
  60         void __iomem *cfg_data;
  61
  62         /*
  63          * Used for variants of PCI indirect handling and possible quirks:
  64          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  65          *  EXT_REG - provides access to PCI-e extended registers
  66          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  67          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  68          *   to determine which bus number to match on when generating type0
  69          *   config cycles
  70          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  71          *   hanging if we don't have link and try to do config cycles to
  72          *   anything but the PHB.  Only allow talking to the PHB if this is
  73          *   set.
  74          *  BIG_ENDIAN - cfg_addr is a big endian register
  75          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
  76          *   on the PLB4.  Effectively disable MRM commands by setting this.
  77          */
  78 #define INDIRECT_TYPE_SET_CFG_TYPE              0x00000001
  79 #define INDIRECT_TYPE_EXT_REG           0x00000002
  80 #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS      0x00000004
  81 #define INDIRECT_TYPE_NO_PCIE_LINK              0x00000008
  82 #define INDIRECT_TYPE_BIG_ENDIAN                0x00000010
  83 #define INDIRECT_TYPE_BROKEN_MRM                0x00000020
  84         u32 indirect_type;
  85
  86         /* Currently, we limit ourselves to 1 IO range and 3 mem
  87          * ranges since the common pci_bus structure can't handle more
  88          */
  89         struct resource io_resource;
  90         struct resource mem_resources[3];
  91         int global_number;      /* PCI domain number */
  92 };
  93
  94 #ifdef CONFIG_PCI
  95 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
  96 {
  97         return bus->sysdata;
  98 }
  99
 100 static inline int isa_vaddr_is_ioport(void __iomem *address)
 101 {
 102         /* No specific ISA handling on ppc32 at this stage, it
 103          * all goes through PCI
 104          */
 105         return 0;
 106 }
 107 #endif /* CONFIG_PCI */
 108
 109 /* These are used for config access before all the PCI probing
 110    has been done. */
 111 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 112                         int dev_fn, int where, u8 *val);
 113 extern int early_read_config_word(struct pci_controller *hose, int bus,
 114                         int dev_fn, int where, u16 *val);
 115 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 116                         int dev_fn, int where, u32 *val);
 117 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 118                         int dev_fn, int where, u8 val);
 119 extern int early_write_config_word(struct pci_controller *hose, int bus,
 120                         int dev_fn, int where, u16 val);
 121 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 122                         int dev_fn, int where, u32 val);
 123
 124 extern int early_find_capability(struct pci_controller *hose, int bus,
 125                                  int dev_fn, int cap);
 126
 127 extern void setup_indirect_pci(struct pci_controller *hose,
 128                                resource_size_t cfg_addr,
 129                                resource_size_t cfg_data, u32 flags);
 130
 131 /* Get the PCI host controller for an OF device */
 132 extern struct pci_controller *pci_find_hose_for_OF_device(
 133                         struct device_node *node);
 134
 135 /* Fill up host controller resources from the OF node */
 136 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 137                         struct device_node *dev, int primary);
 138
 139 /* Allocate & free a PCI host bridge structure */
 140 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 141 extern void pcibios_free_controller(struct pci_controller *phb);
 142
 143 #endif  /* __KERNEL__ */
 144 #endif  /* _ASM_MICROBLAZE_PCI_BRIDGE_H */