arch/microblaze/kernel/intc.c

   1 /*
   2  * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2012-2013 Xilinx, Inc.
   4  * Copyright (C) 2007-2009 PetaLogix
   5  * Copyright (C) 2006 Atmark Techno, Inc.
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License. See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #include <linux/irqdomain.h>
  13 #include <linux/irq.h>
  14 #include <linux/of_address.h>
  15 #include <linux/io.h>
  16 #include <linux/bug.h>
  17
  18 #include "../../drivers/irqchip/irqchip.h"
  19
  20 static void __iomem *intc_baseaddr;
  21
  22 /* No one else should require these constants, so define them locally here. */
  23 #define ISR 0x00                        /* Interrupt Status Register */
  24 #define IPR 0x04                        /* Interrupt Pending Register */
  25 #define IER 0x08                        /* Interrupt Enable Register */
  26 #define IAR 0x0c                        /* Interrupt Acknowledge Register */
  27 #define SIE 0x10                        /* Set Interrupt Enable bits */
  28 #define CIE 0x14                        /* Clear Interrupt Enable bits */
  29 #define IVR 0x18                        /* Interrupt Vector Register */
  30 #define MER 0x1c                        /* Master Enable Register */
  31
  32 #define MER_ME (1<<0)
  33 #define MER_HIE (1<<1)
  34
  35 static unsigned int (*read_fn)(void __iomem *);
  36 static void (*write_fn)(u32, void __iomem *);
  37
  38 static void intc_write32(u32 val, void __iomem *addr)
  39 {
  40         iowrite32(val, addr);
  41 }
  42
  43 static unsigned int intc_read32(void __iomem *addr)
  44 {
  45         return ioread32(addr);
  46 }
  47
  48 static void intc_write32_be(u32 val, void __iomem *addr)
  49 {
  50         iowrite32be(val, addr);
  51 }
  52
  53 static unsigned int intc_read32_be(void __iomem *addr)
  54 {
  55         return ioread32be(addr);
  56 }
  57
  58 static void intc_enable_or_unmask(struct irq_data *d)
  59 {
  60         unsigned long mask = 1 << d->hwirq;
  61
  62         pr_debug("enable_or_unmask: %ld\n", d->hwirq);
  63
  64         /* ack level irqs because they can't be acked during
  65          * ack function since the handle_level_irq function
  66          * acks the irq before calling the interrupt handler
  67          */
  68         if (irqd_is_level_type(d))
  69                 write_fn(mask, intc_baseaddr + IAR);
  70
  71         write_fn(mask, intc_baseaddr + SIE);
  72 }
  73
  74 static void intc_disable_or_mask(struct irq_data *d)
  75 {
  76         pr_debug("disable: %ld\n", d->hwirq);
  77         write_fn(1 << d->hwirq, intc_baseaddr + CIE);
  78 }
  79
  80 static void intc_ack(struct irq_data *d)
  81 {
  82         pr_debug("ack: %ld\n", d->hwirq);
  83         write_fn(1 << d->hwirq, intc_baseaddr + IAR);
  84 }
  85
  86 static void intc_mask_ack(struct irq_data *d)
  87 {
  88         unsigned long mask = 1 << d->hwirq;
  89
  90         pr_debug("disable_and_ack: %ld\n", d->hwirq);
  91         write_fn(mask, intc_baseaddr + CIE);
  92         write_fn(mask, intc_baseaddr + IAR);
  93 }
  94
  95 static struct irq_chip intc_dev = {
  96         .name = "Xilinx INTC",
  97         .irq_unmask = intc_enable_or_unmask,
  98         .irq_mask = intc_disable_or_mask,
  99         .irq_ack = intc_ack,
 100         .irq_mask_ack = intc_mask_ack,
 101 };
 102
 103 static struct irq_domain *root_domain;
 104
 105 unsigned int get_irq(void)
 106 {
 107         unsigned int hwirq, irq = -1;
 108
 109         hwirq = read_fn(intc_baseaddr + IVR);
 110         if (hwirq != -1U)
 111                 irq = irq_find_mapping(root_domain, hwirq);
 112
 113         pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
 114
 115         return irq;
 116 }
 117
 118 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 119 {
 120         u32 intr_mask = (u32)d->host_data;
 121
 122         if (intr_mask & (1 << hw)) {
 123                 irq_set_chip_and_handler_name(irq, &intc_dev,
 124                                                 handle_edge_irq, "edge");
 125                 irq_clear_status_flags(irq, IRQ_LEVEL);
 126         } else {
 127                 irq_set_chip_and_handler_name(irq, &intc_dev,
 128                                                 handle_level_irq, "level");
 129                 irq_set_status_flags(irq, IRQ_LEVEL);
 130         }
 131         return 0;
 132 }
 133
 134 static const struct irq_domain_ops xintc_irq_domain_ops = {
 135         .xlate = irq_domain_xlate_onetwocell,
 136         .map = xintc_map,
 137 };
 138
 139 static int __init xilinx_intc_of_init(struct device_node *intc,
 140                                              struct device_node *parent)
 141 {
 142         u32 nr_irq, intr_mask;
 143         int ret;
 144
 145         intc_baseaddr = of_iomap(intc, 0);
 146         BUG_ON(!intc_baseaddr);
 147
 148         ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
 149         if (ret < 0) {
 150                 pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__);
 151                 return ret;
 152         }
 153
 154         ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask);
 155         if (ret < 0) {
 156                 pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
 157                 return ret;
 158         }
 159
 160         if (intr_mask >> nr_irq)
 161                 pr_warn("%s: mismatch in kind-of-intr param\n", __func__);
 162
 163         pr_info("%s: num_irq=%d, edge=0x%x\n",
 164                 intc->full_name, nr_irq, intr_mask);
 165
 166         write_fn = intc_write32;
 167         read_fn = intc_read32;
 168
 169         /*
 170          * Disable all external interrupts until they are
 171          * explicity requested.
 172          */
 173         write_fn(0, intc_baseaddr + IER);
 174
 175         /* Acknowledge any pending interrupts just in case. */
 176         write_fn(0xffffffff, intc_baseaddr + IAR);
 177
 178         /* Turn on the Master Enable. */
 179         write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
 180         if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
 181                 write_fn = intc_write32_be;
 182                 read_fn = intc_read32_be;
 183                 write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
 184         }
 185
 186         /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
 187          * lazy and Michal can clean it up to something nicer when he tests
 188          * and commits this patch.  ~~gcl */
 189         root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
 190                                                         (void *)intr_mask);
 191
 192         irq_set_default_host(root_domain);
 193
 194         return 0;
 195 }
 196
 197 IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);