arch/xtensa/boot/dts/xtfpga.dtsi

   1 / {
   2         compatible = "cdns,xtensa-xtfpga";
   3         #address-cells = <1>;
   4         #size-cells = <1>;
   5         interrupt-parent = <&pic>;
   6
   7         chosen {
   8                 bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
   9         };
  10
  11         memory@0 {
  12                 device_type = "memory";
  13                 reg = <0x00000000 0x06000000>;
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 cpu@0 {
  20                         compatible = "cdns,xtensa-cpu";
  21                         reg = <0>;
  22                         /* Filled in by platform_setup from FPGA register
  23                          * clock-frequency = <100000000>;
  24                          */
  25                 };
  26         };
  27
  28         pic: pic {
  29                 compatible = "cdns,xtensa-pic";
  30                 /* one cell: internal irq number,
  31                  * two cells: second cell == 0: internal irq number
  32                  *            second cell == 1: external irq number
  33                  */
  34                 #interrupt-cells = <2>;
  35                 interrupt-controller;
  36         };
  37
  38         clocks {
  39                 osc: main-oscillator {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                 };
  43         };
  44
  45         soc {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 compatible = "simple-bus";
  49                 ranges = <0x00000000 0xf0000000 0x10000000>;
  50
  51                 serial0: serial@0d050020 {
  52                         device_type = "serial";
  53                         compatible = "ns16550a";
  54                         no-loopback-test;
  55                         reg = <0x0d050020 0x20>;
  56                         reg-shift = <2>;
  57                         interrupts = <0 1>; /* external irq 0 */
  58                         clocks = <&osc>;
  59                 };
  60
  61                 enet0: ethoc@0d030000 {
  62                         compatible = "opencores,ethoc";
  63                         reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
  64                         interrupts = <1 1>; /* external irq 1 */
  65                         local-mac-address = [00 50 c2 13 6f 00];
  66                         clocks = <&osc>;
  67                 };
  68         };
  69 };