tick/idle/powerpc: Do not register idle states with CPUIDLE_FLAG_TIMER_STOP set in...
[linux/fpc-iii.git] / arch / xtensa / include / asm / vectors.h
bloba46c53f3611336bd2367f675ea0dba9943f66c3e
1 /*
2 * arch/xtensa/include/asm/xchal_vaddr_remap.h
4 * Xtensa macros for MMU V3 Support. Deals with re-mapping the Virtual
5 * Memory Addresses from "Virtual == Physical" to their prevvious V2 MMU
6 * mappings (KSEG at 0xD0000000 and KIO at 0XF0000000).
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
12 * Copyright (C) 2008 - 2012 Tensilica Inc.
14 * Pete Delaney <piet@tensilica.com>
15 * Marc Gauthier <marc@tensilica.com
18 #ifndef _XTENSA_VECTORS_H
19 #define _XTENSA_VECTORS_H
21 #include <variant/core.h>
22 #include <platform/hardware.h>
24 #define XCHAL_KIO_CACHED_VADDR 0xe0000000
25 #define XCHAL_KIO_BYPASS_VADDR 0xf0000000
26 #define XCHAL_KIO_DEFAULT_PADDR 0xf0000000
27 #define XCHAL_KIO_SIZE 0x10000000
29 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
30 #define XCHAL_KIO_PADDR xtensa_get_kio_paddr()
31 #else
32 #define XCHAL_KIO_PADDR XCHAL_KIO_DEFAULT_PADDR
33 #endif
35 #if defined(CONFIG_MMU)
37 /* Will Become VECBASE */
38 #define VIRTUAL_MEMORY_ADDRESS 0xD0000000
40 /* Image Virtual Start Address */
41 #define KERNELOFFSET 0xD0003000
43 #if defined(XCHAL_HAVE_PTP_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
44 /* MMU v3 - XCHAL_HAVE_PTP_MMU == 1 */
45 #define LOAD_MEMORY_ADDRESS 0x00003000
46 #else
47 /* MMU V2 - XCHAL_HAVE_PTP_MMU == 0 */
48 #define LOAD_MEMORY_ADDRESS 0xD0003000
49 #endif
51 #else /* !defined(CONFIG_MMU) */
52 /* MMU Not being used - Virtual == Physical */
54 /* VECBASE */
55 #define VIRTUAL_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x2000)
57 /* Location of the start of the kernel text, _start */
58 #define KERNELOFFSET (PLATFORM_DEFAULT_MEM_START + 0x3000)
60 /* Loaded just above possibly live vectors */
61 #define LOAD_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x3000)
63 #endif /* CONFIG_MMU */
65 #define XC_VADDR(offset) (VIRTUAL_MEMORY_ADDRESS + offset)
67 /* Used to set VECBASE register */
68 #define VECBASE_RESET_VADDR VIRTUAL_MEMORY_ADDRESS
70 #define RESET_VECTOR_VECOFS (XCHAL_RESET_VECTOR_VADDR - \
71 VECBASE_RESET_VADDR)
72 #define RESET_VECTOR_VADDR XC_VADDR(RESET_VECTOR_VECOFS)
74 #define RESET_VECTOR1_VECOFS (XCHAL_RESET_VECTOR1_VADDR - \
75 VECBASE_RESET_VADDR)
76 #define RESET_VECTOR1_VADDR XC_VADDR(RESET_VECTOR1_VECOFS)
78 #if defined(XCHAL_HAVE_VECBASE) && XCHAL_HAVE_VECBASE
80 #define USER_VECTOR_VADDR XC_VADDR(XCHAL_USER_VECOFS)
81 #define KERNEL_VECTOR_VADDR XC_VADDR(XCHAL_KERNEL_VECOFS)
82 #define DOUBLEEXC_VECTOR_VADDR XC_VADDR(XCHAL_DOUBLEEXC_VECOFS)
83 #define WINDOW_VECTORS_VADDR XC_VADDR(XCHAL_WINDOW_OF4_VECOFS)
84 #define INTLEVEL2_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL2_VECOFS)
85 #define INTLEVEL3_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL3_VECOFS)
86 #define INTLEVEL4_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL4_VECOFS)
87 #define INTLEVEL5_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL5_VECOFS)
88 #define INTLEVEL6_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL6_VECOFS)
90 #define DEBUG_VECTOR_VADDR XC_VADDR(XCHAL_DEBUG_VECOFS)
92 #define NMI_VECTOR_VADDR XC_VADDR(XCHAL_NMI_VECOFS)
94 #define INTLEVEL7_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL7_VECOFS)
97 * These XCHAL_* #defines from varian/core.h
98 * are not valid to use with V3 MMU. Non-XCHAL
99 * constants are defined above and should be used.
101 #undef XCHAL_VECBASE_RESET_VADDR
102 #undef XCHAL_RESET_VECTOR0_VADDR
103 #undef XCHAL_USER_VECTOR_VADDR
104 #undef XCHAL_KERNEL_VECTOR_VADDR
105 #undef XCHAL_DOUBLEEXC_VECTOR_VADDR
106 #undef XCHAL_WINDOW_VECTORS_VADDR
107 #undef XCHAL_INTLEVEL2_VECTOR_VADDR
108 #undef XCHAL_INTLEVEL3_VECTOR_VADDR
109 #undef XCHAL_INTLEVEL4_VECTOR_VADDR
110 #undef XCHAL_INTLEVEL5_VECTOR_VADDR
111 #undef XCHAL_INTLEVEL6_VECTOR_VADDR
112 #undef XCHAL_DEBUG_VECTOR_VADDR
113 #undef XCHAL_NMI_VECTOR_VADDR
114 #undef XCHAL_INTLEVEL7_VECTOR_VADDR
116 #else
118 #define USER_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
119 #define KERNEL_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
120 #define DOUBLEEXC_VECTOR_VADDR XCHAL_DOUBLEEXC_VECTOR_VADDR
121 #define WINDOW_VECTORS_VADDR XCHAL_WINDOW_VECTORS_VADDR
122 #define INTLEVEL2_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
123 #define INTLEVEL3_VECTOR_VADDR XCHAL_INTLEVEL3_VECTOR_VADDR
124 #define INTLEVEL4_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
125 #define INTLEVEL5_VECTOR_VADDR XCHAL_INTLEVEL5_VECTOR_VADDR
126 #define INTLEVEL6_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
127 #define DEBUG_VECTOR_VADDR XCHAL_DEBUG_VECTOR_VADDR
129 #endif
131 #endif /* _XTENSA_VECTORS_H */