?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mpls_iptunnel: fix sparse warn: remove incorrect rcu_dereference
[linux/fpc-iii.git] / drivers / dma / xgene-dma.c
blob620fd55ec7660b053a511b8237e54fc46118f407
1 /*
2 * Applied Micro X-Gene SoC DMA engine Driver
3 *
4 * Copyright (c) 2015, Applied Micro Circuits Corporation
5 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
6 * Loc Ho <lho@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 * NOTE: PM support is currently not available.
22 */
23
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/dmapool.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/module.h>
32 #include <linux/of_device.h>
33
34 #include "dmaengine.h"
35
36 /* X-Gene DMA ring csr registers and bit definations */
37 #define XGENE_DMA_RING_CONFIG 0x04
38 #define XGENE_DMA_RING_ENABLE BIT(31)
39 #define XGENE_DMA_RING_ID 0x08
40 #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
41 #define XGENE_DMA_RING_ID_BUF 0x0C
42 #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
43 #define XGENE_DMA_RING_THRESLD0_SET1 0x30
44 #define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
45 #define XGENE_DMA_RING_THRESLD1_SET1 0x34
46 #define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8
47 #define XGENE_DMA_RING_HYSTERESIS 0x68
48 #define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF
49 #define XGENE_DMA_RING_STATE 0x6C
50 #define XGENE_DMA_RING_STATE_WR_BASE 0x70
51 #define XGENE_DMA_RING_NE_INT_MODE 0x017C
52 #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
53 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
54 #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
55 ((m) &= (~BIT(31 - (v))))
56 #define XGENE_DMA_RING_CLKEN 0xC208
57 #define XGENE_DMA_RING_SRST 0xC200
58 #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070
59 #define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
60 #define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF
61 #define XGENE_DMA_RING_DESC_CNT(v) (((v) & 0x0001FFFE) >> 1)
62 #define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
63 #define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
64 #define XGENE_DMA_RING_CMD_OFFSET 0x2C
65 #define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
66 #define XGENE_DMA_RING_COHERENT_SET(m) \
67 (((u32 *)(m))[2] |= BIT(4))
68 #define XGENE_DMA_RING_ADDRL_SET(m, v) \
69 (((u32 *)(m))[2] |= (((v) >> 8) << 5))
70 #define XGENE_DMA_RING_ADDRH_SET(m, v) \
71 (((u32 *)(m))[3] |= ((v) >> 35))
72 #define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
73 (((u32 *)(m))[3] |= BIT(19))
74 #define XGENE_DMA_RING_SIZE_SET(m, v) \
75 (((u32 *)(m))[3] |= ((v) << 23))
76 #define XGENE_DMA_RING_RECOMBBUF_SET(m) \
77 (((u32 *)(m))[3] |= BIT(27))
78 #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \
79 (((u32 *)(m))[3] |= (0x7 << 28))
80 #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \
81 (((u32 *)(m))[4] |= 0x3)
82 #define XGENE_DMA_RING_SELTHRSH_SET(m) \
83 (((u32 *)(m))[4] |= BIT(3))
84 #define XGENE_DMA_RING_TYPE_SET(m, v) \
85 (((u32 *)(m))[4] |= ((v) << 19))
86
87 /* X-Gene DMA device csr registers and bit definitions */
88 #define XGENE_DMA_IPBRR 0x0
89 #define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
90 #define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
91 #define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
92 #define XGENE_DMA_GCR 0x10
93 #define XGENE_DMA_CH_SETUP(v) \
94 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
95 #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
96 #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
97 #define XGENE_DMA_RAID6_CONT 0x14
98 #define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
99 #define XGENE_DMA_INT 0x70
100 #define XGENE_DMA_INT_MASK 0x74
101 #define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF
102 #define XGENE_DMA_INT_ALL_UNMASK 0x0
103 #define XGENE_DMA_INT_MASK_SHIFT 0x14
104 #define XGENE_DMA_RING_INT0_MASK 0x90A0
105 #define XGENE_DMA_RING_INT1_MASK 0x90A8
106 #define XGENE_DMA_RING_INT2_MASK 0x90B0
107 #define XGENE_DMA_RING_INT3_MASK 0x90B8
108 #define XGENE_DMA_RING_INT4_MASK 0x90C0
109 #define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0
110 #define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF
111 #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
112 #define XGENE_DMA_BLK_MEM_RDY 0xD074
113 #define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF
114
115 /* X-Gene SoC EFUSE csr register and bit defination */
116 #define XGENE_SOC_JTAG1_SHADOW 0x18
117 #define XGENE_DMA_PQ_DISABLE_MASK BIT(13)
118
119 /* X-Gene DMA Descriptor format */
120 #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
121 #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
122 #define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
123 #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
124 #define XGENE_DMA_DESC_ELERR_POS 46
125 #define XGENE_DMA_DESC_RTYPE_POS 56
126 #define XGENE_DMA_DESC_LERR_POS 60
127 #define XGENE_DMA_DESC_BUFLEN_POS 48
128 #define XGENE_DMA_DESC_HOENQ_NUM_POS 48
129 #define XGENE_DMA_DESC_ELERR_RD(m) \
130 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
131 #define XGENE_DMA_DESC_LERR_RD(m) \
132 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
133 #define XGENE_DMA_DESC_STATUS(elerr, lerr) \
134 (((elerr) << 4) | (lerr))
135
136 /* X-Gene DMA descriptor empty s/w signature */
137 #define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
138
139 /* X-Gene DMA configurable parameters defines */
140 #define XGENE_DMA_RING_NUM 512
141 #define XGENE_DMA_BUFNUM 0x0
142 #define XGENE_DMA_CPU_BUFNUM 0x18
143 #define XGENE_DMA_RING_OWNER_DMA 0x03
144 #define XGENE_DMA_RING_OWNER_CPU 0x0F
145 #define XGENE_DMA_RING_TYPE_REGULAR 0x01
146 #define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */
147 #define XGENE_DMA_RING_NUM_CONFIG 5
148 #define XGENE_DMA_MAX_CHANNEL 4
149 #define XGENE_DMA_XOR_CHANNEL 0
150 #define XGENE_DMA_PQ_CHANNEL 1
151 #define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
152 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
153 #define XGENE_DMA_XOR_ALIGNMENT 6 /* 64 Bytes */
154 #define XGENE_DMA_MAX_XOR_SRC 5
155 #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
156 #define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL
157
158 /* X-Gene DMA descriptor error codes */
159 #define ERR_DESC_AXI 0x01
160 #define ERR_BAD_DESC 0x02
161 #define ERR_READ_DATA_AXI 0x03
162 #define ERR_WRITE_DATA_AXI 0x04
163 #define ERR_FBP_TIMEOUT 0x05
164 #define ERR_ECC 0x06
165 #define ERR_DIFF_SIZE 0x08
166 #define ERR_SCT_GAT_LEN 0x09
167 #define ERR_CRC_ERR 0x11
168 #define ERR_CHKSUM 0x12
169 #define ERR_DIF 0x13
170
171 /* X-Gene DMA error interrupt codes */
172 #define ERR_DIF_SIZE_INT 0x0
173 #define ERR_GS_ERR_INT 0x1
174 #define ERR_FPB_TIMEO_INT 0x2
175 #define ERR_WFIFO_OVF_INT 0x3
176 #define ERR_RFIFO_OVF_INT 0x4
177 #define ERR_WR_TIMEO_INT 0x5
178 #define ERR_RD_TIMEO_INT 0x6
179 #define ERR_WR_ERR_INT 0x7
180 #define ERR_RD_ERR_INT 0x8
181 #define ERR_BAD_DESC_INT 0x9
182 #define ERR_DESC_DST_INT 0xA
183 #define ERR_DESC_SRC_INT 0xB
184
185 /* X-Gene DMA flyby operation code */
186 #define FLYBY_2SRC_XOR 0x80
187 #define FLYBY_3SRC_XOR 0x90
188 #define FLYBY_4SRC_XOR 0xA0
189 #define FLYBY_5SRC_XOR 0xB0
190
191 /* X-Gene DMA SW descriptor flags */
192 #define XGENE_DMA_FLAG_64B_DESC BIT(0)
193
194 /* Define to dump X-Gene DMA descriptor */
195 #define XGENE_DMA_DESC_DUMP(desc, m) \
196 print_hex_dump(KERN_ERR, (m), \
197 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
198
199 #define to_dma_desc_sw(tx) \
200 container_of(tx, struct xgene_dma_desc_sw, tx)
201 #define to_dma_chan(dchan) \
202 container_of(dchan, struct xgene_dma_chan, dma_chan)
203
204 #define chan_dbg(chan, fmt, arg...) \
205 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
206 #define chan_err(chan, fmt, arg...) \
207 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
208
209 struct xgene_dma_desc_hw {
210 __le64 m0;
211 __le64 m1;
212 __le64 m2;
213 __le64 m3;
214 };
215
216 enum xgene_dma_ring_cfgsize {
217 XGENE_DMA_RING_CFG_SIZE_512B,
218 XGENE_DMA_RING_CFG_SIZE_2KB,
219 XGENE_DMA_RING_CFG_SIZE_16KB,
220 XGENE_DMA_RING_CFG_SIZE_64KB,
221 XGENE_DMA_RING_CFG_SIZE_512KB,
222 XGENE_DMA_RING_CFG_SIZE_INVALID
223 };
224
225 struct xgene_dma_ring {
226 struct xgene_dma *pdma;
227 u8 buf_num;
228 u16 id;
229 u16 num;
230 u16 head;
231 u16 owner;
232 u16 slots;
233 u16 dst_ring_num;
234 u32 size;
235 void __iomem *cmd;
236 void __iomem *cmd_base;
237 dma_addr_t desc_paddr;
238 u32 state[XGENE_DMA_RING_NUM_CONFIG];
239 enum xgene_dma_ring_cfgsize cfgsize;
240 union {
241 void *desc_vaddr;
242 struct xgene_dma_desc_hw *desc_hw;
243 };
244 };
245
246 struct xgene_dma_desc_sw {
247 struct xgene_dma_desc_hw desc1;
248 struct xgene_dma_desc_hw desc2;
249 u32 flags;
250 struct list_head node;
251 struct list_head tx_list;
252 struct dma_async_tx_descriptor tx;
253 };
254
255 /**
256 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
257 * @dma_chan: dmaengine channel object member
258 * @pdma: X-Gene DMA device structure reference
259 * @dev: struct device reference for dma mapping api
260 * @id: raw id of this channel
261 * @rx_irq: channel IRQ
262 * @name: name of X-Gene DMA channel
263 * @lock: serializes enqueue/dequeue operations to the descriptor pool
264 * @pending: number of transaction request pushed to DMA controller for
265 * execution, but still waiting for completion,
266 * @max_outstanding: max number of outstanding request we can push to channel
267 * @ld_pending: descriptors which are queued to run, but have not yet been
268 * submitted to the hardware for execution
269 * @ld_running: descriptors which are currently being executing by the hardware
270 * @ld_completed: descriptors which have finished execution by the hardware.
271 * These descriptors have already had their cleanup actions run. They
272 * are waiting for the ACK bit to be set by the async tx API.
273 * @desc_pool: descriptor pool for DMA operations
274 * @tasklet: bottom half where all completed descriptors cleans
275 * @tx_ring: transmit ring descriptor that we use to prepare actual
276 * descriptors for further executions
277 * @rx_ring: receive ring descriptor that we use to get completed DMA
278 * descriptors during cleanup time
279 */
280 struct xgene_dma_chan {
281 struct dma_chan dma_chan;
282 struct xgene_dma *pdma;
283 struct device *dev;
284 int id;
285 int rx_irq;
286 char name[10];
287 spinlock_t lock;
288 int pending;
289 int max_outstanding;
290 struct list_head ld_pending;
291 struct list_head ld_running;
292 struct list_head ld_completed;
293 struct dma_pool *desc_pool;
294 struct tasklet_struct tasklet;
295 struct xgene_dma_ring tx_ring;
296 struct xgene_dma_ring rx_ring;
297 };
298
299 /**
300 * struct xgene_dma - internal representation of an X-Gene DMA device
301 * @err_irq: DMA error irq number
302 * @ring_num: start id number for DMA ring
303 * @csr_dma: base for DMA register access
304 * @csr_ring: base for DMA ring register access
305 * @csr_ring_cmd: base for DMA ring command register access
306 * @csr_efuse: base for efuse register access
307 * @dma_dev: embedded struct dma_device
308 * @chan: reference to X-Gene DMA channels
309 */
310 struct xgene_dma {
311 struct device *dev;
312 struct clk *clk;
313 int err_irq;
314 int ring_num;
315 void __iomem *csr_dma;
316 void __iomem *csr_ring;
317 void __iomem *csr_ring_cmd;
318 void __iomem *csr_efuse;
319 struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
320 struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
321 };
322
323 static const char * const xgene_dma_desc_err[] = {
324 [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
325 [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
326 [ERR_READ_DATA_AXI] = "AXI error when reading data",
327 [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
328 [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
329 [ERR_ECC] = "ECC double bit error",
330 [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
331 [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
332 [ERR_CRC_ERR] = "CRC error",
333 [ERR_CHKSUM] = "Checksum error",
334 [ERR_DIF] = "DIF error",
335 };
336
337 static const char * const xgene_dma_err[] = {
338 [ERR_DIF_SIZE_INT] = "DIF size error",
339 [ERR_GS_ERR_INT] = "Gather scatter not same size error",
340 [ERR_FPB_TIMEO_INT] = "Free pool time out error",
341 [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
342 [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
343 [ERR_WR_TIMEO_INT] = "Write time out error",
344 [ERR_RD_TIMEO_INT] = "Read time out error",
345 [ERR_WR_ERR_INT] = "HBF bus write error",
346 [ERR_RD_ERR_INT] = "HBF bus read error",
347 [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
348 [ERR_DESC_DST_INT] = "HFB reading dst link address error",
349 [ERR_DESC_SRC_INT] = "HFB reading src link address error",
350 };
351
352 static bool is_pq_enabled(struct xgene_dma *pdma)
353 {
354 u32 val;
355
356 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
357 return !(val & XGENE_DMA_PQ_DISABLE_MASK);
358 }
359
360 static u64 xgene_dma_encode_len(size_t len)
361 {
362 return (len < XGENE_DMA_MAX_BYTE_CNT) ?
363 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
364 XGENE_DMA_16K_BUFFER_LEN_CODE;
365 }
366
367 static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
368 {
369 static u8 flyby_type[] = {
370 FLYBY_2SRC_XOR, /* Dummy */
371 FLYBY_2SRC_XOR, /* Dummy */
372 FLYBY_2SRC_XOR,
373 FLYBY_3SRC_XOR,
374 FLYBY_4SRC_XOR,
375 FLYBY_5SRC_XOR
376 };
377
378 return flyby_type[src_cnt];
379 }
380
381 static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring *ring)
382 {
383 u32 __iomem *cmd_base = ring->cmd_base;
384 u32 ring_state = ioread32(&cmd_base[1]);
385
386 return XGENE_DMA_RING_DESC_CNT(ring_state);
387 }
388
389 static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
390 dma_addr_t *paddr)
391 {
392 size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
393 *len : XGENE_DMA_MAX_BYTE_CNT;
394
395 *ext8 |= cpu_to_le64(*paddr);
396 *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
397 *len -= nbytes;
398 *paddr += nbytes;
399 }
400
401 static void xgene_dma_invalidate_buffer(__le64 *ext8)
402 {
403 *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE);
404 }
405
406 static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
407 {
408 switch (idx) {
409 case 0:
410 return &desc->m1;
411 case 1:
412 return &desc->m0;
413 case 2:
414 return &desc->m3;
415 case 3:
416 return &desc->m2;
417 default:
418 pr_err("Invalid dma descriptor index\n");
419 }
420
421 return NULL;
422 }
423
424 static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
425 u16 dst_ring_num)
426 {
427 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
428 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
429 XGENE_DMA_DESC_RTYPE_POS);
430 desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
431 desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
432 XGENE_DMA_DESC_HOENQ_NUM_POS);
433 }
434
435 static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan,
436 struct xgene_dma_desc_sw *desc_sw,
437 dma_addr_t dst, dma_addr_t src,
438 size_t len)
439 {
440 struct xgene_dma_desc_hw *desc1, *desc2;
441 int i;
442
443 /* Get 1st descriptor */
444 desc1 = &desc_sw->desc1;
445 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
446
447 /* Set destination address */
448 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
449 desc1->m3 |= cpu_to_le64(dst);
450
451 /* Set 1st source address */
452 xgene_dma_set_src_buffer(&desc1->m1, &len, &src);
453
454 if (!len)
455 return;
456
457 /*
458 * We need to split this source buffer,
459 * and need to use 2nd descriptor
460 */
461 desc2 = &desc_sw->desc2;
462 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
463
464 /* Set 2nd to 5th source address */
465 for (i = 0; i < 4 && len; i++)
466 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i),
467 &len, &src);
468
469 /* Invalidate unused source address field */
470 for (; i < 4; i++)
471 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
472
473 /* Updated flag that we have prepared 64B descriptor */
474 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
475 }
476
477 static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
478 struct xgene_dma_desc_sw *desc_sw,
479 dma_addr_t *dst, dma_addr_t *src,
480 u32 src_cnt, size_t *nbytes,
481 const u8 *scf)
482 {
483 struct xgene_dma_desc_hw *desc1, *desc2;
484 size_t len = *nbytes;
485 int i;
486
487 desc1 = &desc_sw->desc1;
488 desc2 = &desc_sw->desc2;
489
490 /* Initialize DMA descriptor */
491 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
492
493 /* Set destination address */
494 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
495 desc1->m3 |= cpu_to_le64(*dst);
496
497 /* We have multiple source addresses, so need to set NV bit*/
498 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
499
500 /* Set flyby opcode */
501 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
502
503 /* Set 1st to 5th source addresses */
504 for (i = 0; i < src_cnt; i++) {
505 len = *nbytes;
506 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
507 xgene_dma_lookup_ext8(desc2, i - 1),
508 &len, &src[i]);
509 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
510 }
511
512 /* Update meta data */
513 *nbytes = len;
514 *dst += XGENE_DMA_MAX_BYTE_CNT;
515
516 /* We need always 64B descriptor to perform xor or pq operations */
517 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
518 }
519
520 static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
521 {
522 struct xgene_dma_desc_sw *desc;
523 struct xgene_dma_chan *chan;
524 dma_cookie_t cookie;
525
526 if (unlikely(!tx))
527 return -EINVAL;
528
529 chan = to_dma_chan(tx->chan);
530 desc = to_dma_desc_sw(tx);
531
532 spin_lock_bh(&chan->lock);
533
534 cookie = dma_cookie_assign(tx);
535
536 /* Add this transaction list onto the tail of the pending queue */
537 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
538
539 spin_unlock_bh(&chan->lock);
540
541 return cookie;
542 }
543
544 static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
545 struct xgene_dma_desc_sw *desc)
546 {
547 list_del(&desc->node);
548 chan_dbg(chan, "LD %p free\n", desc);
549 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
550 }
551
552 static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
553 struct xgene_dma_chan *chan)
554 {
555 struct xgene_dma_desc_sw *desc;
556 dma_addr_t phys;
557
558 desc = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &phys);
559 if (!desc) {
560 chan_err(chan, "Failed to allocate LDs\n");
561 return NULL;
562 }
563
564 memset(desc, 0, sizeof(*desc));
565
566 INIT_LIST_HEAD(&desc->tx_list);
567 desc->tx.phys = phys;
568 desc->tx.tx_submit = xgene_dma_tx_submit;
569 dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
570
571 chan_dbg(chan, "LD %p allocated\n", desc);
572
573 return desc;
574 }
575
576 /**
577 * xgene_dma_clean_completed_descriptor - free all descriptors which
578 * has been completed and acked
579 * @chan: X-Gene DMA channel
580 *
581 * This function is used on all completed and acked descriptors.
582 */
583 static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
584 {
585 struct xgene_dma_desc_sw *desc, *_desc;
586
587 /* Run the callback for each descriptor, in order */
588 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
589 if (async_tx_test_ack(&desc->tx))
590 xgene_dma_clean_descriptor(chan, desc);
591 }
592 }
593
594 /**
595 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
596 * @chan: X-Gene DMA channel
597 * @desc: descriptor to cleanup and free
598 *
599 * This function is used on a descriptor which has been executed by the DMA
600 * controller. It will run any callbacks, submit any dependencies.
601 */
602 static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
603 struct xgene_dma_desc_sw *desc)
604 {
605 struct dma_async_tx_descriptor *tx = &desc->tx;
606
607 /*
608 * If this is not the last transaction in the group,
609 * then no need to complete cookie and run any callback as
610 * this is not the tx_descriptor which had been sent to caller
611 * of this DMA request
612 */
613
614 if (tx->cookie == 0)
615 return;
616
617 dma_cookie_complete(tx);
618
619 /* Run the link descriptor callback function */
620 if (tx->callback)
621 tx->callback(tx->callback_param);
622
623 dma_descriptor_unmap(tx);
624
625 /* Run any dependencies */
626 dma_run_dependencies(tx);
627 }
628
629 /**
630 * xgene_dma_clean_running_descriptor - move the completed descriptor from
631 * ld_running to ld_completed
632 * @chan: X-Gene DMA channel
633 * @desc: the descriptor which is completed
634 *
635 * Free the descriptor directly if acked by async_tx api,
636 * else move it to queue ld_completed.
637 */
638 static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
639 struct xgene_dma_desc_sw *desc)
640 {
641 /* Remove from the list of running transactions */
642 list_del(&desc->node);
643
644 /*
645 * the client is allowed to attach dependent operations
646 * until 'ack' is set
647 */
648 if (!async_tx_test_ack(&desc->tx)) {
649 /*
650 * Move this descriptor to the list of descriptors which is
651 * completed, but still awaiting the 'ack' bit to be set.
652 */
653 list_add_tail(&desc->node, &chan->ld_completed);
654 return;
655 }
656
657 chan_dbg(chan, "LD %p free\n", desc);
658 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
659 }
660
661 static int xgene_chan_xfer_request(struct xgene_dma_ring *ring,
662 struct xgene_dma_desc_sw *desc_sw)
663 {
664 struct xgene_dma_desc_hw *desc_hw;
665
666 /* Check if can push more descriptor to hw for execution */
667 if (xgene_dma_ring_desc_cnt(ring) > (ring->slots - 2))
668 return -EBUSY;
669
670 /* Get hw descriptor from DMA tx ring */
671 desc_hw = &ring->desc_hw[ring->head];
672
673 /*
674 * Increment the head count to point next
675 * descriptor for next time
676 */
677 if (++ring->head == ring->slots)
678 ring->head = 0;
679
680 /* Copy prepared sw descriptor data to hw descriptor */
681 memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
682
683 /*
684 * Check if we have prepared 64B descriptor,
685 * in this case we need one more hw descriptor
686 */
687 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
688 desc_hw = &ring->desc_hw[ring->head];
689
690 if (++ring->head == ring->slots)
691 ring->head = 0;
692
693 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
694 }
695
696 /* Notify the hw that we have descriptor ready for execution */
697 iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
698 2 : 1, ring->cmd);
699
700 return 0;
701 }
702
703 /**
704 * xgene_chan_xfer_ld_pending - push any pending transactions to hw
705 * @chan : X-Gene DMA channel
706 *
707 * LOCKING: must hold chan->lock
708 */
709 static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
710 {
711 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
712 int ret;
713
714 /*
715 * If the list of pending descriptors is empty, then we
716 * don't need to do any work at all
717 */
718 if (list_empty(&chan->ld_pending)) {
719 chan_dbg(chan, "No pending LDs\n");
720 return;
721 }
722
723 /*
724 * Move elements from the queue of pending transactions onto the list
725 * of running transactions and push it to hw for further executions
726 */
727 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
728 /*
729 * Check if have pushed max number of transactions to hw
730 * as capable, so let's stop here and will push remaining
731 * elements from pening ld queue after completing some
732 * descriptors that we have already pushed
733 */
734 if (chan->pending >= chan->max_outstanding)
735 return;
736
737 ret = xgene_chan_xfer_request(&chan->tx_ring, desc_sw);
738 if (ret)
739 return;
740
741 /*
742 * Delete this element from ld pending queue and append it to
743 * ld running queue
744 */
745 list_move_tail(&desc_sw->node, &chan->ld_running);
746
747 /* Increment the pending transaction count */
748 chan->pending++;
749 }
750 }
751
752 /**
753 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
754 * and move them to ld_completed to free until flag 'ack' is set
755 * @chan: X-Gene DMA channel
756 *
757 * This function is used on descriptors which have been executed by the DMA
758 * controller. It will run any callbacks, submit any dependencies, then
759 * free these descriptors if flag 'ack' is set.
760 */
761 static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
762 {
763 struct xgene_dma_ring *ring = &chan->rx_ring;
764 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
765 struct xgene_dma_desc_hw *desc_hw;
766 u8 status;
767
768 /* Clean already completed and acked descriptors */
769 xgene_dma_clean_completed_descriptor(chan);
770
771 /* Run the callback for each descriptor, in order */
772 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
773 /* Get subsequent hw descriptor from DMA rx ring */
774 desc_hw = &ring->desc_hw[ring->head];
775
776 /* Check if this descriptor has been completed */
777 if (unlikely(le64_to_cpu(desc_hw->m0) ==
778 XGENE_DMA_DESC_EMPTY_SIGNATURE))
779 break;
780
781 if (++ring->head == ring->slots)
782 ring->head = 0;
783
784 /* Check if we have any error with DMA transactions */
785 status = XGENE_DMA_DESC_STATUS(
786 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
787 desc_hw->m0)),
788 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
789 desc_hw->m0)));
790 if (status) {
791 /* Print the DMA error type */
792 chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
793
794 /*
795 * We have DMA transactions error here. Dump DMA Tx
796 * and Rx descriptors for this request */
797 XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
798 "X-Gene DMA TX DESC1: ");
799
800 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
801 XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
802 "X-Gene DMA TX DESC2: ");
803
804 XGENE_DMA_DESC_DUMP(desc_hw,
805 "X-Gene DMA RX ERR DESC: ");
806 }
807
808 /* Notify the hw about this completed descriptor */
809 iowrite32(-1, ring->cmd);
810
811 /* Mark this hw descriptor as processed */
812 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
813
814 xgene_dma_run_tx_complete_actions(chan, desc_sw);
815
816 xgene_dma_clean_running_descriptor(chan, desc_sw);
817
818 /*
819 * Decrement the pending transaction count
820 * as we have processed one
821 */
822 chan->pending--;
823 }
824
825 /*
826 * Start any pending transactions automatically
827 * In the ideal case, we keep the DMA controller busy while we go
828 * ahead and free the descriptors below.
829 */
830 xgene_chan_xfer_ld_pending(chan);
831 }
832
833 static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
834 {
835 struct xgene_dma_chan *chan = to_dma_chan(dchan);
836
837 /* Has this channel already been allocated? */
838 if (chan->desc_pool)
839 return 1;
840
841 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
842 sizeof(struct xgene_dma_desc_sw),
843 0, 0);
844 if (!chan->desc_pool) {
845 chan_err(chan, "Failed to allocate descriptor pool\n");
846 return -ENOMEM;
847 }
848
849 chan_dbg(chan, "Allocate descripto pool\n");
850
851 return 1;
852 }
853
854 /**
855 * xgene_dma_free_desc_list - Free all descriptors in a queue
856 * @chan: X-Gene DMA channel
857 * @list: the list to free
858 *
859 * LOCKING: must hold chan->lock
860 */
861 static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
862 struct list_head *list)
863 {
864 struct xgene_dma_desc_sw *desc, *_desc;
865
866 list_for_each_entry_safe(desc, _desc, list, node)
867 xgene_dma_clean_descriptor(chan, desc);
868 }
869
870 static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
871 {
872 struct xgene_dma_chan *chan = to_dma_chan(dchan);
873
874 chan_dbg(chan, "Free all resources\n");
875
876 if (!chan->desc_pool)
877 return;
878
879 spin_lock_bh(&chan->lock);
880
881 /* Process all running descriptor */
882 xgene_dma_cleanup_descriptors(chan);
883
884 /* Clean all link descriptor queues */
885 xgene_dma_free_desc_list(chan, &chan->ld_pending);
886 xgene_dma_free_desc_list(chan, &chan->ld_running);
887 xgene_dma_free_desc_list(chan, &chan->ld_completed);
888
889 spin_unlock_bh(&chan->lock);
890
891 /* Delete this channel DMA pool */
892 dma_pool_destroy(chan->desc_pool);
893 chan->desc_pool = NULL;
894 }
895
896 static struct dma_async_tx_descriptor *xgene_dma_prep_memcpy(
897 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
898 size_t len, unsigned long flags)
899 {
900 struct xgene_dma_desc_sw *first = NULL, *new;
901 struct xgene_dma_chan *chan;
902 size_t copy;
903
904 if (unlikely(!dchan || !len))
905 return NULL;
906
907 chan = to_dma_chan(dchan);
908
909 do {
910 /* Allocate the link descriptor from DMA pool */
911 new = xgene_dma_alloc_descriptor(chan);
912 if (!new)
913 goto fail;
914
915 /* Create the largest transaction possible */
916 copy = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
917
918 /* Prepare DMA descriptor */
919 xgene_dma_prep_cpy_desc(chan, new, dst, src, copy);
920
921 if (!first)
922 first = new;
923
924 new->tx.cookie = 0;
925 async_tx_ack(&new->tx);
926
927 /* Update metadata */
928 len -= copy;
929 dst += copy;
930 src += copy;
931
932 /* Insert the link descriptor to the LD ring */
933 list_add_tail(&new->node, &first->tx_list);
934 } while (len);
935
936 new->tx.flags = flags; /* client is in control of this ack */
937 new->tx.cookie = -EBUSY;
938 list_splice(&first->tx_list, &new->tx_list);
939
940 return &new->tx;
941
942 fail:
943 if (!first)
944 return NULL;
945
946 xgene_dma_free_desc_list(chan, &first->tx_list);
947 return NULL;
948 }
949
950 static struct dma_async_tx_descriptor *xgene_dma_prep_sg(
951 struct dma_chan *dchan, struct scatterlist *dst_sg,
952 u32 dst_nents, struct scatterlist *src_sg,
953 u32 src_nents, unsigned long flags)
954 {
955 struct xgene_dma_desc_sw *first = NULL, *new = NULL;
956 struct xgene_dma_chan *chan;
957 size_t dst_avail, src_avail;
958 dma_addr_t dst, src;
959 size_t len;
960
961 if (unlikely(!dchan))
962 return NULL;
963
964 if (unlikely(!dst_nents || !src_nents))
965 return NULL;
966
967 if (unlikely(!dst_sg || !src_sg))
968 return NULL;
969
970 chan = to_dma_chan(dchan);
971
972 /* Get prepared for the loop */
973 dst_avail = sg_dma_len(dst_sg);
974 src_avail = sg_dma_len(src_sg);
975 dst_nents--;
976 src_nents--;
977
978 /* Run until we are out of scatterlist entries */
979 while (true) {
980 /* Create the largest transaction possible */
981 len = min_t(size_t, src_avail, dst_avail);
982 len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
983 if (len == 0)
984 goto fetch;
985
986 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
987 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
988
989 /* Allocate the link descriptor from DMA pool */
990 new = xgene_dma_alloc_descriptor(chan);
991 if (!new)
992 goto fail;
993
994 /* Prepare DMA descriptor */
995 xgene_dma_prep_cpy_desc(chan, new, dst, src, len);
996
997 if (!first)
998 first = new;
999
1000 new->tx.cookie = 0;
1001 async_tx_ack(&new->tx);
1002
1003 /* update metadata */
1004 dst_avail -= len;
1005 src_avail -= len;
1006
1007 /* Insert the link descriptor to the LD ring */
1008 list_add_tail(&new->node, &first->tx_list);
1009
1010 fetch:
1011 /* fetch the next dst scatterlist entry */
1012 if (dst_avail == 0) {
1013 /* no more entries: we're done */
1014 if (dst_nents == 0)
1015 break;
1016
1017 /* fetch the next entry: if there are no more: done */
1018 dst_sg = sg_next(dst_sg);
1019 if (!dst_sg)
1020 break;
1021
1022 dst_nents--;
1023 dst_avail = sg_dma_len(dst_sg);
1024 }
1025
1026 /* fetch the next src scatterlist entry */
1027 if (src_avail == 0) {
1028 /* no more entries: we're done */
1029 if (src_nents == 0)
1030 break;
1031
1032 /* fetch the next entry: if there are no more: done */
1033 src_sg = sg_next(src_sg);
1034 if (!src_sg)
1035 break;
1036
1037 src_nents--;
1038 src_avail = sg_dma_len(src_sg);
1039 }
1040 }
1041
1042 if (!new)
1043 return NULL;
1044
1045 new->tx.flags = flags; /* client is in control of this ack */
1046 new->tx.cookie = -EBUSY;
1047 list_splice(&first->tx_list, &new->tx_list);
1048
1049 return &new->tx;
1050 fail:
1051 if (!first)
1052 return NULL;
1053
1054 xgene_dma_free_desc_list(chan, &first->tx_list);
1055 return NULL;
1056 }
1057
1058 static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
1059 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
1060 u32 src_cnt, size_t len, unsigned long flags)
1061 {
1062 struct xgene_dma_desc_sw *first = NULL, *new;
1063 struct xgene_dma_chan *chan;
1064 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
1065 0x01, 0x01, 0x01, 0x01, 0x01};
1066
1067 if (unlikely(!dchan || !len))
1068 return NULL;
1069
1070 chan = to_dma_chan(dchan);
1071
1072 do {
1073 /* Allocate the link descriptor from DMA pool */
1074 new = xgene_dma_alloc_descriptor(chan);
1075 if (!new)
1076 goto fail;
1077
1078 /* Prepare xor DMA descriptor */
1079 xgene_dma_prep_xor_desc(chan, new, &dst, src,
1080 src_cnt, &len, multi);
1081
1082 if (!first)
1083 first = new;
1084
1085 new->tx.cookie = 0;
1086 async_tx_ack(&new->tx);
1087
1088 /* Insert the link descriptor to the LD ring */
1089 list_add_tail(&new->node, &first->tx_list);
1090 } while (len);
1091
1092 new->tx.flags = flags; /* client is in control of this ack */
1093 new->tx.cookie = -EBUSY;
1094 list_splice(&first->tx_list, &new->tx_list);
1095
1096 return &new->tx;
1097
1098 fail:
1099 if (!first)
1100 return NULL;
1101
1102 xgene_dma_free_desc_list(chan, &first->tx_list);
1103 return NULL;
1104 }
1105
1106 static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
1107 struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1108 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1109 {
1110 struct xgene_dma_desc_sw *first = NULL, *new;
1111 struct xgene_dma_chan *chan;
1112 size_t _len = len;
1113 dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
1114 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
1115
1116 if (unlikely(!dchan || !len))
1117 return NULL;
1118
1119 chan = to_dma_chan(dchan);
1120
1121 /*
1122 * Save source addresses on local variable, may be we have to
1123 * prepare two descriptor to generate P and Q if both enabled
1124 * in the flags by client
1125 */
1126 memcpy(_src, src, sizeof(*src) * src_cnt);
1127
1128 if (flags & DMA_PREP_PQ_DISABLE_P)
1129 len = 0;
1130
1131 if (flags & DMA_PREP_PQ_DISABLE_Q)
1132 _len = 0;
1133
1134 do {
1135 /* Allocate the link descriptor from DMA pool */
1136 new = xgene_dma_alloc_descriptor(chan);
1137 if (!new)
1138 goto fail;
1139
1140 if (!first)
1141 first = new;
1142
1143 new->tx.cookie = 0;
1144 async_tx_ack(&new->tx);
1145
1146 /* Insert the link descriptor to the LD ring */
1147 list_add_tail(&new->node, &first->tx_list);
1148
1149 /*
1150 * Prepare DMA descriptor to generate P,
1151 * if DMA_PREP_PQ_DISABLE_P flag is not set
1152 */
1153 if (len) {
1154 xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
1155 src_cnt, &len, multi);
1156 continue;
1157 }
1158
1159 /*
1160 * Prepare DMA descriptor to generate Q,
1161 * if DMA_PREP_PQ_DISABLE_Q flag is not set
1162 */
1163 if (_len) {
1164 xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
1165 src_cnt, &_len, scf);
1166 }
1167 } while (len || _len);
1168
1169 new->tx.flags = flags; /* client is in control of this ack */
1170 new->tx.cookie = -EBUSY;
1171 list_splice(&first->tx_list, &new->tx_list);
1172
1173 return &new->tx;
1174
1175 fail:
1176 if (!first)
1177 return NULL;
1178
1179 xgene_dma_free_desc_list(chan, &first->tx_list);
1180 return NULL;
1181 }
1182
1183 static void xgene_dma_issue_pending(struct dma_chan *dchan)
1184 {
1185 struct xgene_dma_chan *chan = to_dma_chan(dchan);
1186
1187 spin_lock_bh(&chan->lock);
1188 xgene_chan_xfer_ld_pending(chan);
1189 spin_unlock_bh(&chan->lock);
1190 }
1191
1192 static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
1193 dma_cookie_t cookie,
1194 struct dma_tx_state *txstate)
1195 {
1196 return dma_cookie_status(dchan, cookie, txstate);
1197 }
1198
1199 static void xgene_dma_tasklet_cb(unsigned long data)
1200 {
1201 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
1202
1203 spin_lock_bh(&chan->lock);
1204
1205 /* Run all cleanup for descriptors which have been completed */
1206 xgene_dma_cleanup_descriptors(chan);
1207
1208 /* Re-enable DMA channel IRQ */
1209 enable_irq(chan->rx_irq);
1210
1211 spin_unlock_bh(&chan->lock);
1212 }
1213
1214 static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
1215 {
1216 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
1217
1218 BUG_ON(!chan);
1219
1220 /*
1221 * Disable DMA channel IRQ until we process completed
1222 * descriptors
1223 */
1224 disable_irq_nosync(chan->rx_irq);
1225
1226 /*
1227 * Schedule the tasklet to handle all cleanup of the current
1228 * transaction. It will start a new transaction if there is
1229 * one pending.
1230 */
1231 tasklet_schedule(&chan->tasklet);
1232
1233 return IRQ_HANDLED;
1234 }
1235
1236 static irqreturn_t xgene_dma_err_isr(int irq, void *id)
1237 {
1238 struct xgene_dma *pdma = (struct xgene_dma *)id;
1239 unsigned long int_mask;
1240 u32 val, i;
1241
1242 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1243
1244 /* Clear DMA interrupts */
1245 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1246
1247 /* Print DMA error info */
1248 int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
1249 for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
1250 dev_err(pdma->dev,
1251 "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
1252
1253 return IRQ_HANDLED;
1254 }
1255
1256 static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
1257 {
1258 int i;
1259
1260 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1261
1262 for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
1263 iowrite32(ring->state[i], ring->pdma->csr_ring +
1264 XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
1265 }
1266
1267 static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
1268 {
1269 memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
1270 xgene_dma_wr_ring_state(ring);
1271 }
1272
1273 static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
1274 {
1275 void *ring_cfg = ring->state;
1276 u64 addr = ring->desc_paddr;
1277 u32 i, val;
1278
1279 ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
1280
1281 /* Clear DMA ring state */
1282 xgene_dma_clr_ring_state(ring);
1283
1284 /* Set DMA ring type */
1285 XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
1286
1287 if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
1288 /* Set recombination buffer and timeout */
1289 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
1290 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
1291 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
1292 }
1293
1294 /* Initialize DMA ring state */
1295 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
1296 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
1297 XGENE_DMA_RING_COHERENT_SET(ring_cfg);
1298 XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
1299 XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
1300 XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
1301
1302 /* Write DMA ring configurations */
1303 xgene_dma_wr_ring_state(ring);
1304
1305 /* Set DMA ring id */
1306 iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
1307 ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1308
1309 /* Set DMA ring buffer */
1310 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
1311 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1312
1313 if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
1314 return;
1315
1316 /* Set empty signature to DMA Rx ring descriptors */
1317 for (i = 0; i < ring->slots; i++) {
1318 struct xgene_dma_desc_hw *desc;
1319
1320 desc = &ring->desc_hw[i];
1321 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
1322 }
1323
1324 /* Enable DMA Rx ring interrupt */
1325 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1326 XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
1327 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1328 }
1329
1330 static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
1331 {
1332 u32 ring_id, val;
1333
1334 if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
1335 /* Disable DMA Rx ring interrupt */
1336 val = ioread32(ring->pdma->csr_ring +
1337 XGENE_DMA_RING_NE_INT_MODE);
1338 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
1339 iowrite32(val, ring->pdma->csr_ring +
1340 XGENE_DMA_RING_NE_INT_MODE);
1341 }
1342
1343 /* Clear DMA ring state */
1344 ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
1345 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1346
1347 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1348 xgene_dma_clr_ring_state(ring);
1349 }
1350
1351 static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
1352 {
1353 ring->cmd_base = ring->pdma->csr_ring_cmd +
1354 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
1355 XGENE_DMA_RING_NUM));
1356
1357 ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
1358 }
1359
1360 static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
1361 enum xgene_dma_ring_cfgsize cfgsize)
1362 {
1363 int size;
1364
1365 switch (cfgsize) {
1366 case XGENE_DMA_RING_CFG_SIZE_512B:
1367 size = 0x200;
1368 break;
1369 case XGENE_DMA_RING_CFG_SIZE_2KB:
1370 size = 0x800;
1371 break;
1372 case XGENE_DMA_RING_CFG_SIZE_16KB:
1373 size = 0x4000;
1374 break;
1375 case XGENE_DMA_RING_CFG_SIZE_64KB:
1376 size = 0x10000;
1377 break;
1378 case XGENE_DMA_RING_CFG_SIZE_512KB:
1379 size = 0x80000;
1380 break;
1381 default:
1382 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
1383 return -EINVAL;
1384 }
1385
1386 return size;
1387 }
1388
1389 static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
1390 {
1391 /* Clear DMA ring configurations */
1392 xgene_dma_clear_ring(ring);
1393
1394 /* De-allocate DMA ring descriptor */
1395 if (ring->desc_vaddr) {
1396 dma_free_coherent(ring->pdma->dev, ring->size,
1397 ring->desc_vaddr, ring->desc_paddr);
1398 ring->desc_vaddr = NULL;
1399 }
1400 }
1401
1402 static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
1403 {
1404 xgene_dma_delete_ring_one(&chan->rx_ring);
1405 xgene_dma_delete_ring_one(&chan->tx_ring);
1406 }
1407
1408 static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
1409 struct xgene_dma_ring *ring,
1410 enum xgene_dma_ring_cfgsize cfgsize)
1411 {
1412 /* Setup DMA ring descriptor variables */
1413 ring->pdma = chan->pdma;
1414 ring->cfgsize = cfgsize;
1415 ring->num = chan->pdma->ring_num++;
1416 ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
1417
1418 ring->size = xgene_dma_get_ring_size(chan, cfgsize);
1419 if (ring->size <= 0)
1420 return ring->size;
1421
1422 /* Allocate memory for DMA ring descriptor */
1423 ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size,
1424 &ring->desc_paddr, GFP_KERNEL);
1425 if (!ring->desc_vaddr) {
1426 chan_err(chan, "Failed to allocate ring desc\n");
1427 return -ENOMEM;
1428 }
1429
1430 /* Configure and enable DMA ring */
1431 xgene_dma_set_ring_cmd(ring);
1432 xgene_dma_setup_ring(ring);
1433
1434 return 0;
1435 }
1436
1437 static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
1438 {
1439 struct xgene_dma_ring *rx_ring = &chan->rx_ring;
1440 struct xgene_dma_ring *tx_ring = &chan->tx_ring;
1441 int ret;
1442
1443 /* Create DMA Rx ring descriptor */
1444 rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
1445 rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
1446
1447 ret = xgene_dma_create_ring_one(chan, rx_ring,
1448 XGENE_DMA_RING_CFG_SIZE_64KB);
1449 if (ret)
1450 return ret;
1451
1452 chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
1453 rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
1454
1455 /* Create DMA Tx ring descriptor */
1456 tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
1457 tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
1458
1459 ret = xgene_dma_create_ring_one(chan, tx_ring,
1460 XGENE_DMA_RING_CFG_SIZE_64KB);
1461 if (ret) {
1462 xgene_dma_delete_ring_one(rx_ring);
1463 return ret;
1464 }
1465
1466 tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
1467
1468 chan_dbg(chan,
1469 "Tx ring id 0x%X num %d desc 0x%p\n",
1470 tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
1471
1472 /* Set the max outstanding request possible to this channel */
1473 chan->max_outstanding = rx_ring->slots;
1474
1475 return ret;
1476 }
1477
1478 static int xgene_dma_init_rings(struct xgene_dma *pdma)
1479 {
1480 int ret, i, j;
1481
1482 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1483 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1484 if (ret) {
1485 for (j = 0; j < i; j++)
1486 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1487 return ret;
1488 }
1489 }
1490
1491 return ret;
1492 }
1493
1494 static void xgene_dma_enable(struct xgene_dma *pdma)
1495 {
1496 u32 val;
1497
1498 /* Configure and enable DMA engine */
1499 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1500 XGENE_DMA_CH_SETUP(val);
1501 XGENE_DMA_ENABLE(val);
1502 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1503 }
1504
1505 static void xgene_dma_disable(struct xgene_dma *pdma)
1506 {
1507 u32 val;
1508
1509 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1510 XGENE_DMA_DISABLE(val);
1511 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1512 }
1513
1514 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1515 {
1516 /*
1517 * Mask DMA ring overflow, underflow and
1518 * AXI write/read error interrupts
1519 */
1520 iowrite32(XGENE_DMA_INT_ALL_MASK,
1521 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1522 iowrite32(XGENE_DMA_INT_ALL_MASK,
1523 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1524 iowrite32(XGENE_DMA_INT_ALL_MASK,
1525 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1526 iowrite32(XGENE_DMA_INT_ALL_MASK,
1527 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1528 iowrite32(XGENE_DMA_INT_ALL_MASK,
1529 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1530
1531 /* Mask DMA error interrupts */
1532 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1533 }
1534
1535 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1536 {
1537 /*
1538 * Unmask DMA ring overflow, underflow and
1539 * AXI write/read error interrupts
1540 */
1541 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1542 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1543 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1544 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1545 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1546 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1547 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1548 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1549 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1550 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1551
1552 /* Unmask DMA error interrupts */
1553 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1554 pdma->csr_dma + XGENE_DMA_INT_MASK);
1555 }
1556
1557 static void xgene_dma_init_hw(struct xgene_dma *pdma)
1558 {
1559 u32 val;
1560
1561 /* Associate DMA ring to corresponding ring HW */
1562 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
1563 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1564
1565 /* Configure RAID6 polynomial control setting */
1566 if (is_pq_enabled(pdma))
1567 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1568 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1569 else
1570 dev_info(pdma->dev, "PQ is disabled in HW\n");
1571
1572 xgene_dma_enable(pdma);
1573 xgene_dma_unmask_interrupts(pdma);
1574
1575 /* Get DMA id and version info */
1576 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1577
1578 /* DMA device info */
1579 dev_info(pdma->dev,
1580 "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1581 XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
1582 XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
1583 }
1584
1585 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1586 {
1587 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1588 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1589 return 0;
1590
1591 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1592 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1593
1594 /* Bring up memory */
1595 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1596
1597 /* Force a barrier */
1598 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1599
1600 /* reset may take up to 1ms */
1601 usleep_range(1000, 1100);
1602
1603 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1604 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
1605 dev_err(pdma->dev,
1606 "Failed to release ring mngr memory from shutdown\n");
1607 return -ENODEV;
1608 }
1609
1610 /* program threshold set 1 and all hysteresis */
1611 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
1612 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1613 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
1614 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1615 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
1616 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1617
1618 /* Enable QPcore and assign error queue */
1619 iowrite32(XGENE_DMA_RING_ENABLE,
1620 pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1621
1622 return 0;
1623 }
1624
1625 static int xgene_dma_init_mem(struct xgene_dma *pdma)
1626 {
1627 int ret;
1628
1629 ret = xgene_dma_init_ring_mngr(pdma);
1630 if (ret)
1631 return ret;
1632
1633 /* Bring up memory */
1634 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1635
1636 /* Force a barrier */
1637 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1638
1639 /* reset may take up to 1ms */
1640 usleep_range(1000, 1100);
1641
1642 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1643 != XGENE_DMA_BLK_MEM_RDY_VAL) {
1644 dev_err(pdma->dev,
1645 "Failed to release DMA memory from shutdown\n");
1646 return -ENODEV;
1647 }
1648
1649 return 0;
1650 }
1651
1652 static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1653 {
1654 struct xgene_dma_chan *chan;
1655 int ret, i, j;
1656
1657 /* Register DMA error irq */
1658 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1659 0, "dma_error", pdma);
1660 if (ret) {
1661 dev_err(pdma->dev,
1662 "Failed to register error IRQ %d\n", pdma->err_irq);
1663 return ret;
1664 }
1665
1666 /* Register DMA channel rx irq */
1667 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1668 chan = &pdma->chan[i];
1669 ret = devm_request_irq(chan->dev, chan->rx_irq,
1670 xgene_dma_chan_ring_isr,
1671 0, chan->name, chan);
1672 if (ret) {
1673 chan_err(chan, "Failed to register Rx IRQ %d\n",
1674 chan->rx_irq);
1675 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1676
1677 for (j = 0; j < i; j++) {
1678 chan = &pdma->chan[i];
1679 devm_free_irq(chan->dev, chan->rx_irq, chan);
1680 }
1681
1682 return ret;
1683 }
1684 }
1685
1686 return 0;
1687 }
1688
1689 static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1690 {
1691 struct xgene_dma_chan *chan;
1692 int i;
1693
1694 /* Free DMA device error irq */
1695 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1696
1697 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1698 chan = &pdma->chan[i];
1699 devm_free_irq(chan->dev, chan->rx_irq, chan);
1700 }
1701 }
1702
1703 static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
1704 struct dma_device *dma_dev)
1705 {
1706 /* Initialize DMA device capability mask */
1707 dma_cap_zero(dma_dev->cap_mask);
1708
1709 /* Set DMA device capability */
1710 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1711 dma_cap_set(DMA_SG, dma_dev->cap_mask);
1712
1713 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1714 * and channel 1 supports XOR, PQ both. First thing here is we have
1715 * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1716 * we can make sure this by reading SoC Efuse register.
1717 * Second thing, we have hw errata that if we run channel 0 and
1718 * channel 1 simultaneously with executing XOR and PQ request,
1719 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1720 * if XOR and PQ supports on channel 1 is disabled.
1721 */
1722 if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
1723 is_pq_enabled(chan->pdma)) {
1724 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1725 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1726 } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
1727 !is_pq_enabled(chan->pdma)) {
1728 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1729 }
1730
1731 /* Set base and prep routines */
1732 dma_dev->dev = chan->dev;
1733 dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
1734 dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
1735 dma_dev->device_issue_pending = xgene_dma_issue_pending;
1736 dma_dev->device_tx_status = xgene_dma_tx_status;
1737 dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy;
1738 dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;
1739
1740 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1741 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
1742 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
1743 dma_dev->xor_align = XGENE_DMA_XOR_ALIGNMENT;
1744 }
1745
1746 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1747 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
1748 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
1749 dma_dev->pq_align = XGENE_DMA_XOR_ALIGNMENT;
1750 }
1751 }
1752
1753 static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1754 {
1755 struct xgene_dma_chan *chan = &pdma->chan[id];
1756 struct dma_device *dma_dev = &pdma->dma_dev[id];
1757 int ret;
1758
1759 chan->dma_chan.device = dma_dev;
1760
1761 spin_lock_init(&chan->lock);
1762 INIT_LIST_HEAD(&chan->ld_pending);
1763 INIT_LIST_HEAD(&chan->ld_running);
1764 INIT_LIST_HEAD(&chan->ld_completed);
1765 tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb,
1766 (unsigned long)chan);
1767
1768 chan->pending = 0;
1769 chan->desc_pool = NULL;
1770 dma_cookie_init(&chan->dma_chan);
1771
1772 /* Setup dma device capabilities and prep routines */
1773 xgene_dma_set_caps(chan, dma_dev);
1774
1775 /* Initialize DMA device list head */
1776 INIT_LIST_HEAD(&dma_dev->channels);
1777 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1778
1779 /* Register with Linux async DMA framework*/
1780 ret = dma_async_device_register(dma_dev);
1781 if (ret) {
1782 chan_err(chan, "Failed to register async device %d", ret);
1783 tasklet_kill(&chan->tasklet);
1784
1785 return ret;
1786 }
1787
1788 /* DMA capability info */
1789 dev_info(pdma->dev,
1790 "%s: CAPABILITY ( %s%s%s%s)\n", dma_chan_name(&chan->dma_chan),
1791 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "",
1792 dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",
1793 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
1794 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
1795
1796 return 0;
1797 }
1798
1799 static int xgene_dma_init_async(struct xgene_dma *pdma)
1800 {
1801 int ret, i, j;
1802
1803 for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
1804 ret = xgene_dma_async_register(pdma, i);
1805 if (ret) {
1806 for (j = 0; j < i; j++) {
1807 dma_async_device_unregister(&pdma->dma_dev[j]);
1808 tasklet_kill(&pdma->chan[j].tasklet);
1809 }
1810
1811 return ret;
1812 }
1813 }
1814
1815 return ret;
1816 }
1817
1818 static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1819 {
1820 int i;
1821
1822 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1823 dma_async_device_unregister(&pdma->dma_dev[i]);
1824 }
1825
1826 static void xgene_dma_init_channels(struct xgene_dma *pdma)
1827 {
1828 struct xgene_dma_chan *chan;
1829 int i;
1830
1831 pdma->ring_num = XGENE_DMA_RING_NUM;
1832
1833 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1834 chan = &pdma->chan[i];
1835 chan->dev = pdma->dev;
1836 chan->pdma = pdma;
1837 chan->id = i;
1838 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
1839 }
1840 }
1841
1842 static int xgene_dma_get_resources(struct platform_device *pdev,
1843 struct xgene_dma *pdma)
1844 {
1845 struct resource *res;
1846 int irq, i;
1847
1848 /* Get DMA csr region */
1849 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1850 if (!res) {
1851 dev_err(&pdev->dev, "Failed to get csr region\n");
1852 return -ENXIO;
1853 }
1854
1855 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1856 resource_size(res));
1857 if (!pdma->csr_dma) {
1858 dev_err(&pdev->dev, "Failed to ioremap csr region");
1859 return -ENOMEM;
1860 }
1861
1862 /* Get DMA ring csr region */
1863 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1864 if (!res) {
1865 dev_err(&pdev->dev, "Failed to get ring csr region\n");
1866 return -ENXIO;
1867 }
1868
1869 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
1870 resource_size(res));
1871 if (!pdma->csr_ring) {
1872 dev_err(&pdev->dev, "Failed to ioremap ring csr region");
1873 return -ENOMEM;
1874 }
1875
1876 /* Get DMA ring cmd csr region */
1877 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1878 if (!res) {
1879 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
1880 return -ENXIO;
1881 }
1882
1883 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1884 resource_size(res));
1885 if (!pdma->csr_ring_cmd) {
1886 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
1887 return -ENOMEM;
1888 }
1889
1890 /* Get efuse csr region */
1891 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1892 if (!res) {
1893 dev_err(&pdev->dev, "Failed to get efuse csr region\n");
1894 return -ENXIO;
1895 }
1896
1897 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1898 resource_size(res));
1899 if (!pdma->csr_efuse) {
1900 dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
1901 return -ENOMEM;
1902 }
1903
1904 /* Get DMA error interrupt */
1905 irq = platform_get_irq(pdev, 0);
1906 if (irq <= 0) {
1907 dev_err(&pdev->dev, "Failed to get Error IRQ\n");
1908 return -ENXIO;
1909 }
1910
1911 pdma->err_irq = irq;
1912
1913 /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1914 for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1915 irq = platform_get_irq(pdev, i);
1916 if (irq <= 0) {
1917 dev_err(&pdev->dev, "Failed to get Rx IRQ\n");
1918 return -ENXIO;
1919 }
1920
1921 pdma->chan[i - 1].rx_irq = irq;
1922 }
1923
1924 return 0;
1925 }
1926
1927 static int xgene_dma_probe(struct platform_device *pdev)
1928 {
1929 struct xgene_dma *pdma;
1930 int ret, i;
1931
1932 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1933 if (!pdma)
1934 return -ENOMEM;
1935
1936 pdma->dev = &pdev->dev;
1937 platform_set_drvdata(pdev, pdma);
1938
1939 ret = xgene_dma_get_resources(pdev, pdma);
1940 if (ret)
1941 return ret;
1942
1943 pdma->clk = devm_clk_get(&pdev->dev, NULL);
1944 if (IS_ERR(pdma->clk)) {
1945 dev_err(&pdev->dev, "Failed to get clk\n");
1946 return PTR_ERR(pdma->clk);
1947 }
1948
1949 /* Enable clk before accessing registers */
1950 ret = clk_prepare_enable(pdma->clk);
1951 if (ret) {
1952 dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
1953 return ret;
1954 }
1955
1956 /* Remove DMA RAM out of shutdown */
1957 ret = xgene_dma_init_mem(pdma);
1958 if (ret)
1959 goto err_clk_enable;
1960
1961 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
1962 if (ret) {
1963 dev_err(&pdev->dev, "No usable DMA configuration\n");
1964 goto err_dma_mask;
1965 }
1966
1967 /* Initialize DMA channels software state */
1968 xgene_dma_init_channels(pdma);
1969
1970 /* Configue DMA rings */
1971 ret = xgene_dma_init_rings(pdma);
1972 if (ret)
1973 goto err_clk_enable;
1974
1975 ret = xgene_dma_request_irqs(pdma);
1976 if (ret)
1977 goto err_request_irq;
1978
1979 /* Configure and enable DMA engine */
1980 xgene_dma_init_hw(pdma);
1981
1982 /* Register DMA device with linux async framework */
1983 ret = xgene_dma_init_async(pdma);
1984 if (ret)
1985 goto err_async_init;
1986
1987 return 0;
1988
1989 err_async_init:
1990 xgene_dma_free_irqs(pdma);
1991
1992 err_request_irq:
1993 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1994 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1995
1996 err_dma_mask:
1997 err_clk_enable:
1998 clk_disable_unprepare(pdma->clk);
1999
2000 return ret;
2001 }
2002
2003 static int xgene_dma_remove(struct platform_device *pdev)
2004 {
2005 struct xgene_dma *pdma = platform_get_drvdata(pdev);
2006 struct xgene_dma_chan *chan;
2007 int i;
2008
2009 xgene_dma_async_unregister(pdma);
2010
2011 /* Mask interrupts and disable DMA engine */
2012 xgene_dma_mask_interrupts(pdma);
2013 xgene_dma_disable(pdma);
2014 xgene_dma_free_irqs(pdma);
2015
2016 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
2017 chan = &pdma->chan[i];
2018 tasklet_kill(&chan->tasklet);
2019 xgene_dma_delete_chan_rings(chan);
2020 }
2021
2022 clk_disable_unprepare(pdma->clk);
2023
2024 return 0;
2025 }
2026
2027 static const struct of_device_id xgene_dma_of_match_ptr[] = {
2028 {.compatible = "apm,xgene-storm-dma",},
2029 {},
2030 };
2031 MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
2032
2033 static struct platform_driver xgene_dma_driver = {
2034 .probe = xgene_dma_probe,
2035 .remove = xgene_dma_remove,
2036 .driver = {
2037 .name = "X-Gene-DMA",
2038 .of_match_table = xgene_dma_of_match_ptr,
2039 },
2040 };
2041
2042 module_platform_driver(xgene_dma_driver);
2043
2044 MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
2045 MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
2046 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
2047 MODULE_LICENSE("GPL");
2048 MODULE_VERSION("1.0");
Linux with added FPC-III support