arch/arm/mach-iop13xx/irq.c

   1 /*
   2  * iop13xx IRQ handling / support functions
   3  * Copyright (c) 2005-2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  */
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/sysctl.h>
  23 #include <asm/uaccess.h>
  24 #include <asm/mach/irq.h>
  25 #include <asm/irq.h>
  26 #include <asm/hardware.h>
  27 #include <asm/mach-types.h>
  28 #include <asm/arch/irqs.h>
  29
  30 /* INTCTL0 CP6 R0 Page 4
  31  */
  32 static inline u32 read_intctl_0(void)
  33 {
  34         u32 val;
  35         asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
  36         return val;
  37 }
  38 static inline void write_intctl_0(u32 val)
  39 {
  40         asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
  41 }
  42
  43 /* INTCTL1 CP6 R1 Page 4
  44  */
  45 static inline u32 read_intctl_1(void)
  46 {
  47         u32 val;
  48         asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
  49         return val;
  50 }
  51 static inline void write_intctl_1(u32 val)
  52 {
  53         asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
  54 }
  55
  56 /* INTCTL2 CP6 R2 Page 4
  57  */
  58 static inline u32 read_intctl_2(void)
  59 {
  60         u32 val;
  61         asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
  62         return val;
  63 }
  64 static inline void write_intctl_2(u32 val)
  65 {
  66         asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
  67 }
  68
  69 /* INTCTL3 CP6 R3 Page 4
  70  */
  71 static inline u32 read_intctl_3(void)
  72 {
  73         u32 val;
  74         asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
  75         return val;
  76 }
  77 static inline void write_intctl_3(u32 val)
  78 {
  79         asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
  80 }
  81
  82 /* INTSTR0 CP6 R0 Page 5
  83  */
  84 static inline u32 read_intstr_0(void)
  85 {
  86         u32 val;
  87         asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
  88         return val;
  89 }
  90 static inline void write_intstr_0(u32 val)
  91 {
  92         asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
  93 }
  94
  95 /* INTSTR1 CP6 R1 Page 5
  96  */
  97 static inline u32 read_intstr_1(void)
  98 {
  99         u32 val;
 100         asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
 101         return val;
 102 }
 103 static void write_intstr_1(u32 val)
 104 {
 105         asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
 106 }
 107
 108 /* INTSTR2 CP6 R2 Page 5
 109  */
 110 static inline u32 read_intstr_2(void)
 111 {
 112         u32 val;
 113         asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
 114         return val;
 115 }
 116 static void write_intstr_2(u32 val)
 117 {
 118         asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
 119 }
 120
 121 /* INTSTR3 CP6 R3 Page 5
 122  */
 123 static inline u32 read_intstr_3(void)
 124 {
 125         u32 val;
 126         asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
 127         return val;
 128 }
 129 static void write_intstr_3(u32 val)
 130 {
 131         asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
 132 }
 133
 134 /* INTBASE CP6 R0 Page 2
 135  */
 136 static inline u32 read_intbase(void)
 137 {
 138         u32 val;
 139         asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
 140         return val;
 141 }
 142 static void write_intbase(u32 val)
 143 {
 144         asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
 145 }
 146
 147 /* INTSIZE CP6 R2 Page 2
 148  */
 149 static inline u32 read_intsize(void)
 150 {
 151         u32 val;
 152         asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
 153         return val;
 154 }
 155 static void write_intsize(u32 val)
 156 {
 157         asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
 158 }
 159
 160 /* 0 = Interrupt Masked and 1 = Interrupt not masked */
 161 static void
 162 iop13xx_irq_mask0 (unsigned int irq)
 163 {
 164         write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
 165 }
 166
 167 static void
 168 iop13xx_irq_mask1 (unsigned int irq)
 169 {
 170         write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
 171 }
 172
 173 static void
 174 iop13xx_irq_mask2 (unsigned int irq)
 175 {
 176         write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
 177 }
 178
 179 static void
 180 iop13xx_irq_mask3 (unsigned int irq)
 181 {
 182         write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
 183 }
 184
 185 static void
 186 iop13xx_irq_unmask0(unsigned int irq)
 187 {
 188         write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
 189 }
 190
 191 static void
 192 iop13xx_irq_unmask1(unsigned int irq)
 193 {
 194         write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
 195 }
 196
 197 static void
 198 iop13xx_irq_unmask2(unsigned int irq)
 199 {
 200         write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
 201 }
 202
 203 static void
 204 iop13xx_irq_unmask3(unsigned int irq)
 205 {
 206         write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
 207 }
 208
 209 static struct irq_chip iop13xx_irqchip1 = {
 210         .name   = "IOP13xx-1",
 211         .ack    = iop13xx_irq_mask0,
 212         .mask   = iop13xx_irq_mask0,
 213         .unmask = iop13xx_irq_unmask0,
 214 };
 215
 216 static struct irq_chip iop13xx_irqchip2 = {
 217         .name   = "IOP13xx-2",
 218         .ack    = iop13xx_irq_mask1,
 219         .mask   = iop13xx_irq_mask1,
 220         .unmask = iop13xx_irq_unmask1,
 221 };
 222
 223 static struct irq_chip iop13xx_irqchip3 = {
 224         .name   = "IOP13xx-3",
 225         .ack    = iop13xx_irq_mask2,
 226         .mask   = iop13xx_irq_mask2,
 227         .unmask = iop13xx_irq_unmask2,
 228 };
 229
 230 static struct irq_chip iop13xx_irqchip4 = {
 231         .name   = "IOP13xx-4",
 232         .ack    = iop13xx_irq_mask3,
 233         .mask   = iop13xx_irq_mask3,
 234         .unmask = iop13xx_irq_unmask3,
 235 };
 236
 237 extern void iop_init_cp6_handler(void);
 238
 239 void __init iop13xx_init_irq(void)
 240 {
 241         unsigned int i;
 242
 243         iop_init_cp6_handler();
 244
 245         /* disable all interrupts */
 246         write_intctl_0(0);
 247         write_intctl_1(0);
 248         write_intctl_2(0);
 249         write_intctl_3(0);
 250
 251         /* treat all as IRQ */
 252         write_intstr_0(0);
 253         write_intstr_1(0);
 254         write_intstr_2(0);
 255         write_intstr_3(0);
 256
 257         /* initialize the interrupt vector generator */
 258         write_intbase(INTBASE);
 259         write_intsize(INTSIZE_4);
 260
 261         for(i = 0; i < NR_IOP13XX_IRQS; i++) {
 262                 if (i < 32)
 263                         set_irq_chip(i, &iop13xx_irqchip1);
 264                 else if (i < 64)
 265                         set_irq_chip(i, &iop13xx_irqchip2);
 266                 else if (i < 96)
 267                         set_irq_chip(i, &iop13xx_irqchip3);
 268                 else
 269                         set_irq_chip(i, &iop13xx_irqchip4);
 270
 271                 set_irq_handler(i, handle_level_irq);
 272                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 273         }
 274 }