1 /* linux/arch/arm/mach-s3c2412/irq.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/ptrace.h>
27 #include <linux/sysdev.h>
29 #include <asm/hardware.h>
33 #include <asm/mach/irq.h>
35 #include <asm/arch/regs-irq.h>
36 #include <asm/arch/regs-gpio.h>
38 #include <asm/plat-s3c24xx/cpu.h>
39 #include <asm/plat-s3c24xx/irq.h>
40 #include <asm/plat-s3c24xx/pm.h>
42 /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
43 * having them turn up in both the INT* and the EINT* registers. Whilst
44 * both show the status, they both now need to be acked when the IRQs
49 s3c2412_irq_mask(unsigned int irqno
)
51 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
54 mask
= __raw_readl(S3C2410_INTMSK
);
55 __raw_writel(mask
| bitval
, S3C2410_INTMSK
);
57 mask
= __raw_readl(S3C2412_EINTMASK
);
58 __raw_writel(mask
| bitval
, S3C2412_EINTMASK
);
62 s3c2412_irq_ack(unsigned int irqno
)
64 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
66 __raw_writel(bitval
, S3C2412_EINTPEND
);
67 __raw_writel(bitval
, S3C2410_SRCPND
);
68 __raw_writel(bitval
, S3C2410_INTPND
);
72 s3c2412_irq_maskack(unsigned int irqno
)
74 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
77 mask
= __raw_readl(S3C2410_INTMSK
);
78 __raw_writel(mask
|bitval
, S3C2410_INTMSK
);
80 mask
= __raw_readl(S3C2412_EINTMASK
);
81 __raw_writel(mask
| bitval
, S3C2412_EINTMASK
);
83 __raw_writel(bitval
, S3C2412_EINTPEND
);
84 __raw_writel(bitval
, S3C2410_SRCPND
);
85 __raw_writel(bitval
, S3C2410_INTPND
);
89 s3c2412_irq_unmask(unsigned int irqno
)
91 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
94 mask
= __raw_readl(S3C2412_EINTMASK
);
95 __raw_writel(mask
& ~bitval
, S3C2412_EINTMASK
);
97 mask
= __raw_readl(S3C2410_INTMSK
);
98 __raw_writel(mask
& ~bitval
, S3C2410_INTMSK
);
101 static struct irq_chip s3c2412_irq_eint0t4
= {
102 .ack
= s3c2412_irq_ack
,
103 .mask
= s3c2412_irq_mask
,
104 .unmask
= s3c2412_irq_unmask
,
105 .set_wake
= s3c_irq_wake
,
106 .set_type
= s3c_irqext_type
,
109 static int s3c2412_irq_add(struct sys_device
*sysdev
)
113 for (irqno
= IRQ_EINT0
; irqno
<= IRQ_EINT3
; irqno
++) {
114 set_irq_chip(irqno
, &s3c2412_irq_eint0t4
);
115 set_irq_handler(irqno
, handle_edge_irq
);
116 set_irq_flags(irqno
, IRQF_VALID
);
122 static struct sysdev_driver s3c2412_irq_driver
= {
123 .add
= s3c2412_irq_add
,
124 .suspend
= s3c24xx_irq_suspend
,
125 .resume
= s3c24xx_irq_resume
,
128 static int s3c2412_irq_init(void)
130 return sysdev_driver_register(&s3c2412_sysclass
, &s3c2412_irq_driver
);
133 arch_initcall(s3c2412_irq_init
);