arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  * Copyright (C) 2004 Silicon Graphics, Inc.
  10  *
  11  * Note: Above list of copyright holders is incomplete...
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/spinlock.h>
  23
  24 #include <asm/machvec.h>
  25 #include <asm/page.h>
  26 #include <asm/system.h>
  27 #include <asm/io.h>
  28 #include <asm/sal.h>
  29 #include <asm/smp.h>
  30 #include <asm/irq.h>
  31 #include <asm/hw_irq.h>
  32
  33 /*
  34  * Low-level SAL-based PCI configuration access functions. Note that SAL
  35  * calls are already serialized (via sal_lock), so we don't need another
  36  * synchronization mechanism here.
  37  */
  38
  39 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)           \
  40         (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  41
  42 /* SAL 3.2 adds support for extended config space. */
  43
  44 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)       \
  45         (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  46
  47 static int
  48 pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
  49               int reg, int len, u32 *value)
  50 {
  51         u64 addr, data = 0;
  52         int mode, result;
  53
  54         if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  55                 return -EINVAL;
  56
  57         if ((seg | reg) <= 255) {
  58                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  59                 mode = 0;
  60         } else {
  61                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  62                 mode = 1;
  63         }
  64         result = ia64_sal_pci_config_read(addr, mode, len, &data);
  65         if (result != 0)
  66                 return -EINVAL;
  67
  68         *value = (u32) data;
  69         return 0;
  70 }
  71
  72 static int
  73 pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
  74                int reg, int len, u32 value)
  75 {
  76         u64 addr;
  77         int mode, result;
  78
  79         if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  80                 return -EINVAL;
  81
  82         if ((seg | reg) <= 255) {
  83                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  84                 mode = 0;
  85         } else {
  86                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  87                 mode = 1;
  88         }
  89         result = ia64_sal_pci_config_write(addr, mode, len, value);
  90         if (result != 0)
  91                 return -EINVAL;
  92         return 0;
  93 }
  94
  95 static struct pci_raw_ops pci_sal_ops = {
  96         .read =         pci_sal_read,
  97         .write =        pci_sal_write
  98 };
  99
 100 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
 101
 102 static int
 103 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
 104 {
 105         return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
 106                                  devfn, where, size, value);
 107 }
 108
 109 static int
 110 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 111 {
 112         return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
 113                                   devfn, where, size, value);
 114 }
 115
 116 struct pci_ops pci_root_ops = {
 117         .read = pci_read,
 118         .write = pci_write,
 119 };
 120
 121 /* Called by ACPI when it finds a new root bus.  */
 122
 123 static struct pci_controller * __devinit
 124 alloc_pci_controller (int seg)
 125 {
 126         struct pci_controller *controller;
 127
 128         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 129         if (!controller)
 130                 return NULL;
 131
 132         controller->segment = seg;
 133         controller->node = -1;
 134         return controller;
 135 }
 136
 137 struct pci_root_info {
 138         struct pci_controller *controller;
 139         char *name;
 140 };
 141
 142 static unsigned int
 143 new_space (u64 phys_base, int sparse)
 144 {
 145         u64 mmio_base;
 146         int i;
 147
 148         if (phys_base == 0)
 149                 return 0;       /* legacy I/O port space */
 150
 151         mmio_base = (u64) ioremap(phys_base, 0);
 152         for (i = 0; i < num_io_spaces; i++)
 153                 if (io_space[i].mmio_base == mmio_base &&
 154                     io_space[i].sparse == sparse)
 155                         return i;
 156
 157         if (num_io_spaces == MAX_IO_SPACES) {
 158                 printk(KERN_ERR "PCI: Too many IO port spaces "
 159                         "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
 160                 return ~0;
 161         }
 162
 163         i = num_io_spaces++;
 164         io_space[i].mmio_base = mmio_base;
 165         io_space[i].sparse = sparse;
 166
 167         return i;
 168 }
 169
 170 static u64 __devinit
 171 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
 172 {
 173         struct resource *resource;
 174         char *name;
 175         u64 base, min, max, base_port;
 176         unsigned int sparse = 0, space_nr, len;
 177
 178         resource = kzalloc(sizeof(*resource), GFP_KERNEL);
 179         if (!resource) {
 180                 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
 181                         info->name);
 182                 goto out;
 183         }
 184
 185         len = strlen(info->name) + 32;
 186         name = kzalloc(len, GFP_KERNEL);
 187         if (!name) {
 188                 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
 189                         info->name);
 190                 goto free_resource;
 191         }
 192
 193         min = addr->minimum;
 194         max = min + addr->address_length - 1;
 195         if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
 196                 sparse = 1;
 197
 198         space_nr = new_space(addr->translation_offset, sparse);
 199         if (space_nr == ~0)
 200                 goto free_name;
 201
 202         base = __pa(io_space[space_nr].mmio_base);
 203         base_port = IO_SPACE_BASE(space_nr);
 204         snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
 205                 base_port + min, base_port + max);
 206
 207         /*
 208          * The SDM guarantees the legacy 0-64K space is sparse, but if the
 209          * mapping is done by the processor (not the bridge), ACPI may not
 210          * mark it as sparse.
 211          */
 212         if (space_nr == 0)
 213                 sparse = 1;
 214
 215         resource->name  = name;
 216         resource->flags = IORESOURCE_MEM;
 217         resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
 218         resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
 219         insert_resource(&iomem_resource, resource);
 220
 221         return base_port;
 222
 223 free_name:
 224         kfree(name);
 225 free_resource:
 226         kfree(resource);
 227 out:
 228         return ~0;
 229 }
 230
 231 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
 232         struct acpi_resource_address64 *addr)
 233 {
 234         acpi_status status;
 235
 236         /*
 237          * We're only interested in _CRS descriptors that are
 238          *      - address space descriptors for memory or I/O space
 239          *      - non-zero size
 240          *      - producers, i.e., the address space is routed downstream,
 241          *        not consumed by the bridge itself
 242          */
 243         status = acpi_resource_to_address64(resource, addr);
 244         if (ACPI_SUCCESS(status) &&
 245             (addr->resource_type == ACPI_MEMORY_RANGE ||
 246              addr->resource_type == ACPI_IO_RANGE) &&
 247             addr->address_length &&
 248             addr->producer_consumer == ACPI_PRODUCER)
 249                 return AE_OK;
 250
 251         return AE_ERROR;
 252 }
 253
 254 static acpi_status __devinit
 255 count_window (struct acpi_resource *resource, void *data)
 256 {
 257         unsigned int *windows = (unsigned int *) data;
 258         struct acpi_resource_address64 addr;
 259         acpi_status status;
 260
 261         status = resource_to_window(resource, &addr);
 262         if (ACPI_SUCCESS(status))
 263                 (*windows)++;
 264
 265         return AE_OK;
 266 }
 267
 268 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 269 {
 270         struct pci_root_info *info = data;
 271         struct pci_window *window;
 272         struct acpi_resource_address64 addr;
 273         acpi_status status;
 274         unsigned long flags, offset = 0;
 275         struct resource *root;
 276
 277         /* Return AE_OK for non-window resources to keep scanning for more */
 278         status = resource_to_window(res, &addr);
 279         if (!ACPI_SUCCESS(status))
 280                 return AE_OK;
 281
 282         if (addr.resource_type == ACPI_MEMORY_RANGE) {
 283                 flags = IORESOURCE_MEM;
 284                 root = &iomem_resource;
 285                 offset = addr.translation_offset;
 286         } else if (addr.resource_type == ACPI_IO_RANGE) {
 287                 flags = IORESOURCE_IO;
 288                 root = &ioport_resource;
 289                 offset = add_io_space(info, &addr);
 290                 if (offset == ~0)
 291                         return AE_OK;
 292         } else
 293                 return AE_OK;
 294
 295         window = &info->controller->window[info->controller->windows++];
 296         window->resource.name = info->name;
 297         window->resource.flags = flags;
 298         window->resource.start = addr.minimum + offset;
 299         window->resource.end = window->resource.start + addr.address_length - 1;
 300         window->resource.child = NULL;
 301         window->offset = offset;
 302
 303         if (insert_resource(root, &window->resource)) {
 304                 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
 305                         window->resource.start, window->resource.end,
 306                         root->name, info->name);
 307         }
 308
 309         return AE_OK;
 310 }
 311
 312 static void __devinit
 313 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 314 {
 315         int i, j;
 316
 317         j = 0;
 318         for (i = 0; i < ctrl->windows; i++) {
 319                 struct resource *res = &ctrl->window[i].resource;
 320                 /* HP's firmware has a hack to work around a Windows bug.
 321                  * Ignore these tiny memory ranges */
 322                 if ((res->flags & IORESOURCE_MEM) &&
 323                     (res->end - res->start < 16))
 324                         continue;
 325                 if (j >= PCI_BUS_NUM_RESOURCES) {
 326                         printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
 327                                         res->end, res->flags);
 328                         continue;
 329                 }
 330                 bus->resource[j++] = res;
 331         }
 332 }
 333
 334 struct pci_bus * __devinit
 335 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
 336 {
 337         struct pci_root_info info;
 338         struct pci_controller *controller;
 339         unsigned int windows = 0;
 340         struct pci_bus *pbus;
 341         char *name;
 342         int pxm;
 343
 344         controller = alloc_pci_controller(domain);
 345         if (!controller)
 346                 goto out1;
 347
 348         controller->acpi_handle = device->handle;
 349
 350         pxm = acpi_get_pxm(controller->acpi_handle);
 351 #ifdef CONFIG_NUMA
 352         if (pxm >= 0)
 353                 controller->node = pxm_to_node(pxm);
 354 #endif
 355
 356         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
 357                         &windows);
 358         controller->window = kmalloc_node(sizeof(*controller->window) * windows,
 359                         GFP_KERNEL, controller->node);
 360         if (!controller->window)
 361                 goto out2;
 362
 363         name = kmalloc(16, GFP_KERNEL);
 364         if (!name)
 365                 goto out3;
 366
 367         sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 368         info.controller = controller;
 369         info.name = name;
 370         acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
 371                         &info);
 372
 373         pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
 374         if (pbus)
 375                 pcibios_setup_root_windows(pbus, controller);
 376
 377         return pbus;
 378
 379 out3:
 380         kfree(controller->window);
 381 out2:
 382         kfree(controller);
 383 out1:
 384         return NULL;
 385 }
 386
 387 void pcibios_resource_to_bus(struct pci_dev *dev,
 388                 struct pci_bus_region *region, struct resource *res)
 389 {
 390         struct pci_controller *controller = PCI_CONTROLLER(dev);
 391         unsigned long offset = 0;
 392         int i;
 393
 394         for (i = 0; i < controller->windows; i++) {
 395                 struct pci_window *window = &controller->window[i];
 396                 if (!(window->resource.flags & res->flags))
 397                         continue;
 398                 if (window->resource.start > res->start)
 399                         continue;
 400                 if (window->resource.end < res->end)
 401                         continue;
 402                 offset = window->offset;
 403                 break;
 404         }
 405
 406         region->start = res->start - offset;
 407         region->end = res->end - offset;
 408 }
 409 EXPORT_SYMBOL(pcibios_resource_to_bus);
 410
 411 void pcibios_bus_to_resource(struct pci_dev *dev,
 412                 struct resource *res, struct pci_bus_region *region)
 413 {
 414         struct pci_controller *controller = PCI_CONTROLLER(dev);
 415         unsigned long offset = 0;
 416         int i;
 417
 418         for (i = 0; i < controller->windows; i++) {
 419                 struct pci_window *window = &controller->window[i];
 420                 if (!(window->resource.flags & res->flags))
 421                         continue;
 422                 if (window->resource.start - window->offset > region->start)
 423                         continue;
 424                 if (window->resource.end - window->offset < region->end)
 425                         continue;
 426                 offset = window->offset;
 427                 break;
 428         }
 429
 430         res->start = region->start + offset;
 431         res->end = region->end + offset;
 432 }
 433 EXPORT_SYMBOL(pcibios_bus_to_resource);
 434
 435 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 436 {
 437         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 438         struct resource *devr = &dev->resource[idx];
 439
 440         if (!dev->bus)
 441                 return 0;
 442         for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
 443                 struct resource *busr = dev->bus->resource[i];
 444
 445                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
 446                         continue;
 447                 if ((devr->start) && (devr->start >= busr->start) &&
 448                                 (devr->end <= busr->end))
 449                         return 1;
 450         }
 451         return 0;
 452 }
 453
 454 static void __devinit
 455 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
 456 {
 457         struct pci_bus_region region;
 458         int i;
 459
 460         for (i = start; i < limit; i++) {
 461                 if (!dev->resource[i].flags)
 462                         continue;
 463                 region.start = dev->resource[i].start;
 464                 region.end = dev->resource[i].end;
 465                 pcibios_bus_to_resource(dev, &dev->resource[i], &region);
 466                 if ((is_valid_resource(dev, i)))
 467                         pci_claim_resource(dev, i);
 468         }
 469 }
 470
 471 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 472 {
 473         pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
 474 }
 475 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
 476
 477 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
 478 {
 479         pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
 480 }
 481
 482 /*
 483  *  Called after each bus is probed, but before its children are examined.
 484  */
 485 void __devinit
 486 pcibios_fixup_bus (struct pci_bus *b)
 487 {
 488         struct pci_dev *dev;
 489
 490         if (b->self) {
 491                 pci_read_bridge_bases(b);
 492                 pcibios_fixup_bridge_resources(b->self);
 493         }
 494         list_for_each_entry(dev, &b->devices, bus_list)
 495                 pcibios_fixup_device_resources(dev);
 496         platform_pci_fixup_bus(b);
 497
 498         return;
 499 }
 500
 501 void __devinit
 502 pcibios_update_irq (struct pci_dev *dev, int irq)
 503 {
 504         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 505
 506         /* ??? FIXME -- record old value for shutdown.  */
 507 }
 508
 509 static inline int
 510 pcibios_enable_resources (struct pci_dev *dev, int mask)
 511 {
 512         u16 cmd, old_cmd;
 513         int idx;
 514         struct resource *r;
 515         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 516
 517         if (!dev)
 518                 return -EINVAL;
 519
 520         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 521         old_cmd = cmd;
 522         for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
 523                 /* Only set up the desired resources.  */
 524                 if (!(mask & (1 << idx)))
 525                         continue;
 526
 527                 r = &dev->resource[idx];
 528                 if (!(r->flags & type_mask))
 529                         continue;
 530                 if ((idx == PCI_ROM_RESOURCE) &&
 531                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 532                         continue;
 533                 if (!r->start && r->end) {
 534                         printk(KERN_ERR
 535                                "PCI: Device %s not available because of resource collisions\n",
 536                                pci_name(dev));
 537                         return -EINVAL;
 538                 }
 539                 if (r->flags & IORESOURCE_IO)
 540                         cmd |= PCI_COMMAND_IO;
 541                 if (r->flags & IORESOURCE_MEM)
 542                         cmd |= PCI_COMMAND_MEMORY;
 543         }
 544         if (cmd != old_cmd) {
 545                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 546                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 547         }
 548         return 0;
 549 }
 550
 551 int
 552 pcibios_enable_device (struct pci_dev *dev, int mask)
 553 {
 554         int ret;
 555
 556         ret = pcibios_enable_resources(dev, mask);
 557         if (ret < 0)
 558                 return ret;
 559
 560         if (!dev->msi_enabled)
 561                 return acpi_pci_irq_enable(dev);
 562         return 0;
 563 }
 564
 565 void
 566 pcibios_disable_device (struct pci_dev *dev)
 567 {
 568         BUG_ON(atomic_read(&dev->enable_cnt));
 569         if (!dev->msi_enabled)
 570                 acpi_pci_irq_disable(dev);
 571 }
 572
 573 void
 574 pcibios_align_resource (void *data, struct resource *res,
 575                         resource_size_t size, resource_size_t align)
 576 {
 577 }
 578
 579 /*
 580  * PCI BIOS setup, always defaults to SAL interface
 581  */
 582 char * __init
 583 pcibios_setup (char *str)
 584 {
 585         return str;
 586 }
 587
 588 int
 589 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 590                      enum pci_mmap_state mmap_state, int write_combine)
 591 {
 592         /*
 593          * I/O space cannot be accessed via normal processor loads and
 594          * stores on this platform.
 595          */
 596         if (mmap_state == pci_mmap_io)
 597                 /*
 598                  * XXX we could relax this for I/O spaces for which ACPI
 599                  * indicates that the space is 1-to-1 mapped.  But at the
 600                  * moment, we don't support multiple PCI address spaces and
 601                  * the legacy I/O space is not 1-to-1 mapped, so this is moot.
 602                  */
 603                 return -EINVAL;
 604
 605         /*
 606          * Leave vm_pgoff as-is, the PCI space address is the physical
 607          * address on this platform.
 608          */
 609         if (write_combine && efi_range_is_wc(vma->vm_start,
 610                                              vma->vm_end - vma->vm_start))
 611                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 612         else
 613                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 614
 615         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 616                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 617                 return -EAGAIN;
 618
 619         return 0;
 620 }
 621
 622 /**
 623  * ia64_pci_get_legacy_mem - generic legacy mem routine
 624  * @bus: bus to get legacy memory base address for
 625  *
 626  * Find the base of legacy memory for @bus.  This is typically the first
 627  * megabyte of bus address space for @bus or is simply 0 on platforms whose
 628  * chipsets support legacy I/O and memory routing.  Returns the base address
 629  * or an error pointer if an error occurred.
 630  *
 631  * This is the ia64 generic version of this routine.  Other platforms
 632  * are free to override it with a machine vector.
 633  */
 634 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
 635 {
 636         return (char *)__IA64_UNCACHED_OFFSET;
 637 }
 638
 639 /**
 640  * pci_mmap_legacy_page_range - map legacy memory space to userland
 641  * @bus: bus whose legacy space we're mapping
 642  * @vma: vma passed in by mmap
 643  *
 644  * Map legacy memory space for this device back to userspace using a machine
 645  * vector to get the base address.
 646  */
 647 int
 648 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
 649 {
 650         unsigned long size = vma->vm_end - vma->vm_start;
 651         pgprot_t prot;
 652         char *addr;
 653
 654         /*
 655          * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
 656          * for more details.
 657          */
 658         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 659                 return -EINVAL;
 660         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 661                                     vma->vm_page_prot);
 662         if (pgprot_val(prot) != pgprot_val(pgprot_noncached(vma->vm_page_prot)))
 663                 return -EINVAL;
 664
 665         addr = pci_get_legacy_mem(bus);
 666         if (IS_ERR(addr))
 667                 return PTR_ERR(addr);
 668
 669         vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
 670         vma->vm_page_prot = prot;
 671
 672         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 673                             size, vma->vm_page_prot))
 674                 return -EAGAIN;
 675
 676         return 0;
 677 }
 678
 679 /**
 680  * ia64_pci_legacy_read - read from legacy I/O space
 681  * @bus: bus to read
 682  * @port: legacy port value
 683  * @val: caller allocated storage for returned value
 684  * @size: number of bytes to read
 685  *
 686  * Simply reads @size bytes from @port and puts the result in @val.
 687  *
 688  * Again, this (and the write routine) are generic versions that can be
 689  * overridden by the platform.  This is necessary on platforms that don't
 690  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
 691  */
 692 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 693 {
 694         int ret = size;
 695
 696         switch (size) {
 697         case 1:
 698                 *val = inb(port);
 699                 break;
 700         case 2:
 701                 *val = inw(port);
 702                 break;
 703         case 4:
 704                 *val = inl(port);
 705                 break;
 706         default:
 707                 ret = -EINVAL;
 708                 break;
 709         }
 710
 711         return ret;
 712 }
 713
 714 /**
 715  * ia64_pci_legacy_write - perform a legacy I/O write
 716  * @bus: bus pointer
 717  * @port: port to write
 718  * @val: value to write
 719  * @size: number of bytes to write from @val
 720  *
 721  * Simply writes @size bytes of @val to @port.
 722  */
 723 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 724 {
 725         int ret = size;
 726
 727         switch (size) {
 728         case 1:
 729                 outb(val, port);
 730                 break;
 731         case 2:
 732                 outw(val, port);
 733                 break;
 734         case 4:
 735                 outl(val, port);
 736                 break;
 737         default:
 738                 ret = -EINVAL;
 739                 break;
 740         }
 741
 742         return ret;
 743 }
 744
 745 /* It's defined in drivers/pci/pci.c */
 746 extern u8 pci_cache_line_size;
 747
 748 /**
 749  * set_pci_cacheline_size - determine cacheline size for PCI devices
 750  *
 751  * We want to use the line-size of the outer-most cache.  We assume
 752  * that this line-size is the same for all CPUs.
 753  *
 754  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 755  */
 756 static void __init set_pci_cacheline_size(void)
 757 {
 758         u64 levels, unique_caches;
 759         s64 status;
 760         pal_cache_config_info_t cci;
 761
 762         status = ia64_pal_cache_summary(&levels, &unique_caches);
 763         if (status != 0) {
 764                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
 765                         "(status=%ld)\n", __FUNCTION__, status);
 766                 return;
 767         }
 768
 769         status = ia64_pal_cache_config_info(levels - 1,
 770                                 /* cache_type (data_or_unified)= */ 2, &cci);
 771         if (status != 0) {
 772                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
 773                         "(status=%ld)\n", __FUNCTION__, status);
 774                 return;
 775         }
 776         pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
 777 }
 778
 779 static int __init pcibios_init(void)
 780 {
 781         set_pci_cacheline_size();
 782         return 0;
 783 }
 784
 785 subsys_initcall(pcibios_init);