arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33
  34 #include <asm/of_device.h>
  35 #include <asm/of_platform.h>
  36 #include <asm/system.h>
  37 #include <asm/atomic.h>
  38 #include <asm/time.h>
  39 #include <asm/io.h>
  40 #include <asm/machdep.h>
  41 #include <asm/bootinfo.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/mpc85xx.h>
  44 #include <asm/irq.h>
  45 #include <mm/mmu_decl.h>
  46 #include <asm/prom.h>
  47 #include <asm/udbg.h>
  48 #include <sysdev/fsl_soc.h>
  49 #include <asm/qe.h>
  50 #include <asm/qe_ic.h>
  51 #include <asm/mpic.h>
  52
  53 #include "mpc85xx.h"
  54
  55 #undef DEBUG
  56 #ifdef DEBUG
  57 #define DBG(fmt...) udbg_printf(fmt)
  58 #else
  59 #define DBG(fmt...)
  60 #endif
  61
  62 #ifndef CONFIG_PCI
  63 unsigned long isa_io_base = 0;
  64 unsigned long isa_mem_base = 0;
  65 #endif
  66
  67 /* ************************************************************************
  68  *
  69  * Setup the architecture
  70  *
  71  */
  72 static void __init mpc85xx_mds_setup_arch(void)
  73 {
  74         struct device_node *np;
  75         static u8 *bcsr_regs = NULL;
  76
  77         if (ppc_md.progress)
  78                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
  79
  80         np = of_find_node_by_type(NULL, "cpu");
  81         if (np != NULL) {
  82                 const unsigned int *fp =
  83                     get_property(np, "clock-frequency", NULL);
  84                 if (fp != NULL)
  85                         loops_per_jiffy = *fp / HZ;
  86                 else
  87                         loops_per_jiffy = 50000000 / HZ;
  88                 of_node_put(np);
  89         }
  90
  91         /* Map BCSR area */
  92         np = of_find_node_by_name(NULL, "bcsr");
  93         if (np != NULL) {
  94                 struct resource res;
  95
  96                 of_address_to_resource(np, 0, &res);
  97                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
  98                 of_node_put(np);
  99         }
 100
 101 #ifdef CONFIG_PCI
 102         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
 103                 add_bridge(np);
 104         }
 105         of_node_put(np);
 106 #endif
 107
 108 #ifdef CONFIG_QUICC_ENGINE
 109         if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
 110                 qe_reset();
 111                 of_node_put(np);
 112         }
 113
 114         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
 115                 struct device_node *ucc = NULL;
 116
 117                 par_io_init(np);
 118                 of_node_put(np);
 119
 120                 for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
 121                         par_io_of_config(ucc);
 122
 123                 of_node_put(ucc);
 124         }
 125
 126         if (bcsr_regs) {
 127                 u8 bcsr_phy;
 128
 129                 /* Reset the Ethernet PHY */
 130                 bcsr_phy = in_be8(&bcsr_regs[9]);
 131                 bcsr_phy &= ~0x20;
 132                 out_be8(&bcsr_regs[9], bcsr_phy);
 133
 134                 udelay(1000);
 135
 136                 bcsr_phy = in_be8(&bcsr_regs[9]);
 137                 bcsr_phy |= 0x20;
 138                 out_be8(&bcsr_regs[9], bcsr_phy);
 139
 140                 iounmap(bcsr_regs);
 141         }
 142
 143 #endif  /* CONFIG_QUICC_ENGINE */
 144 }
 145
 146 static struct of_device_id mpc85xx_ids[] = {
 147         { .type = "soc", },
 148         { .compatible = "soc", },
 149         { .type = "qe", },
 150         {},
 151 };
 152
 153 static int __init mpc85xx_publish_devices(void)
 154 {
 155         if (!machine_is(mpc85xx_mds))
 156                 return 0;
 157
 158         /* Publish the QE devices */
 159         of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
 160
 161         return 0;
 162 }
 163 device_initcall(mpc85xx_publish_devices);
 164
 165 static void __init mpc85xx_mds_pic_init(void)
 166 {
 167         struct mpic *mpic;
 168         struct resource r;
 169         struct device_node *np = NULL;
 170
 171         np = of_find_node_by_type(NULL, "open-pic");
 172         if (!np)
 173                 return;
 174
 175         if (of_address_to_resource(np, 0, &r)) {
 176                 printk(KERN_ERR "Failed to map mpic register space\n");
 177                 of_node_put(np);
 178                 return;
 179         }
 180
 181         mpic = mpic_alloc(np, r.start,
 182                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 183                         4, 0, " OpenPIC  ");
 184         BUG_ON(mpic == NULL);
 185         of_node_put(np);
 186
 187         /* Internal Interrupts */
 188         mpic_assign_isu(mpic, 0, r.start + 0x10200);
 189         mpic_assign_isu(mpic, 1, r.start + 0x10280);
 190         mpic_assign_isu(mpic, 2, r.start + 0x10300);
 191         mpic_assign_isu(mpic, 3, r.start + 0x10380);
 192         mpic_assign_isu(mpic, 4, r.start + 0x10400);
 193         mpic_assign_isu(mpic, 5, r.start + 0x10480);
 194         mpic_assign_isu(mpic, 6, r.start + 0x10500);
 195         mpic_assign_isu(mpic, 7, r.start + 0x10580);
 196         mpic_assign_isu(mpic, 8, r.start + 0x10600);
 197         mpic_assign_isu(mpic, 9, r.start + 0x10680);
 198         mpic_assign_isu(mpic, 10, r.start + 0x10700);
 199         mpic_assign_isu(mpic, 11, r.start + 0x10780);
 200
 201         /* External Interrupts */
 202         mpic_assign_isu(mpic, 12, r.start + 0x10000);
 203         mpic_assign_isu(mpic, 13, r.start + 0x10080);
 204         mpic_assign_isu(mpic, 14, r.start + 0x10100);
 205
 206         mpic_init(mpic);
 207
 208 #ifdef CONFIG_QUICC_ENGINE
 209         np = of_find_node_by_type(NULL, "qeic");
 210         if (!np)
 211                 return;
 212
 213         qe_ic_init(np, 0);
 214         of_node_put(np);
 215 #endif                          /* CONFIG_QUICC_ENGINE */
 216 }
 217
 218 static int __init mpc85xx_mds_probe(void)
 219 {
 220         unsigned long root = of_get_flat_dt_root();
 221
 222         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 223 }
 224
 225 define_machine(mpc85xx_mds) {
 226         .name           = "MPC85xx MDS",
 227         .probe          = mpc85xx_mds_probe,
 228         .setup_arch     = mpc85xx_mds_setup_arch,
 229         .init_IRQ       = mpc85xx_mds_pic_init,
 230         .get_irq        = mpic_get_irq,
 231         .restart        = mpc85xx_restart,
 232         .calibrate_decr = generic_calibrate_decr,
 233         .progress       = udbg_progress,
 234 };