arch/powerpc/platforms/86xx/mpc86xx_hpcn.c

   1 /*
   2  * MPC86xx HPCN board specific routines
   3  *
   4  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   5  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   6  *
   7  * Copyright 2006 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21
  22 #include <asm/system.h>
  23 #include <asm/time.h>
  24 #include <asm/machdep.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/mpc86xx.h>
  27 #include <asm/prom.h>
  28 #include <mm/mmu_decl.h>
  29 #include <asm/udbg.h>
  30 #include <asm/i8259.h>
  31
  32 #include <asm/mpic.h>
  33
  34 #include <sysdev/fsl_soc.h>
  35
  36 #include "mpc86xx.h"
  37 #include "mpc8641_hpcn.h"
  38
  39 #undef DEBUG
  40
  41 #ifdef DEBUG
  42 #define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0)
  43 #else
  44 #define DBG(fmt...) do { } while(0)
  45 #endif
  46
  47 #ifndef CONFIG_PCI
  48 unsigned long isa_io_base = 0;
  49 unsigned long isa_mem_base = 0;
  50 unsigned long pci_dram_offset = 0;
  51 #endif
  52
  53
  54 #ifdef CONFIG_PCI
  55 static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
  56 {
  57         unsigned int cascade_irq = i8259_irq();
  58         if (cascade_irq != NO_IRQ)
  59                 generic_handle_irq(cascade_irq);
  60         desc->chip->eoi(irq);
  61 }
  62 #endif  /* CONFIG_PCI */
  63
  64 void __init
  65 mpc86xx_hpcn_init_irq(void)
  66 {
  67         struct mpic *mpic1;
  68         struct device_node *np;
  69         struct resource res;
  70 #ifdef CONFIG_PCI
  71         struct device_node *cascade_node = NULL;
  72         int cascade_irq;
  73 #endif
  74
  75         /* Determine PIC address. */
  76         np = of_find_node_by_type(NULL, "open-pic");
  77         if (np == NULL)
  78                 return;
  79         of_address_to_resource(np, 0, &res);
  80
  81         /* Alloc mpic structure and per isu has 16 INT entries. */
  82         mpic1 = mpic_alloc(np, res.start,
  83                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  84                         16, NR_IRQS - 4,
  85                         " MPIC     ");
  86         BUG_ON(mpic1 == NULL);
  87
  88         mpic_assign_isu(mpic1, 0, res.start + 0x10000);
  89
  90         /* 48 Internal Interrupts */
  91         mpic_assign_isu(mpic1, 1, res.start + 0x10200);
  92         mpic_assign_isu(mpic1, 2, res.start + 0x10400);
  93         mpic_assign_isu(mpic1, 3, res.start + 0x10600);
  94
  95         /* 16 External interrupts
  96          * Moving them from [0 - 15] to [64 - 79]
  97          */
  98         mpic_assign_isu(mpic1, 4, res.start + 0x10000);
  99
 100         mpic_init(mpic1);
 101
 102 #ifdef CONFIG_PCI
 103         /* Initialize i8259 controller */
 104         for_each_node_by_type(np, "interrupt-controller")
 105                 if (device_is_compatible(np, "chrp,iic")) {
 106                         cascade_node = np;
 107                         break;
 108                 }
 109         if (cascade_node == NULL) {
 110                 printk(KERN_DEBUG "mpc86xxhpcn: no ISA interrupt controller\n");
 111                 return;
 112         }
 113
 114         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 115         if (cascade_irq == NO_IRQ) {
 116                 printk(KERN_ERR "mpc86xxhpcn: failed to map cascade interrupt");
 117                 return;
 118         }
 119         DBG("mpc86xxhpcn: cascade mapped to irq %d\n", cascade_irq);
 120
 121         i8259_init(cascade_node, 0);
 122         of_node_put(cascade_node);
 123
 124         set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade);
 125 #endif
 126 }
 127
 128 #ifdef CONFIG_PCI
 129
 130 enum pirq{PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH};
 131 const unsigned char uli1575_irq_route_table[16] = {
 132         0,      /* 0: Reserved */
 133         0x8,    /* 1: 0b1000 */
 134         0,      /* 2: Reserved */
 135         0x2,    /* 3: 0b0010 */
 136         0x4,    /* 4: 0b0100 */
 137         0x5,    /* 5: 0b0101 */
 138         0x7,    /* 6: 0b0111 */
 139         0x6,    /* 7: 0b0110 */
 140         0,      /* 8: Reserved */
 141         0x1,    /* 9: 0b0001 */
 142         0x3,    /* 10: 0b0011 */
 143         0x9,    /* 11: 0b1001 */
 144         0xb,    /* 12: 0b1011 */
 145         0,      /* 13: Reserved */
 146         0xd,    /* 14, 0b1101 */
 147         0xf,    /* 15, 0b1111 */
 148 };
 149
 150 static int __devinit
 151 get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
 152 {
 153         struct of_irq oirq;
 154         u32 laddr[3];
 155         struct device_node *hosenode = hose ? hose->arch_data : NULL;
 156
 157         if (!hosenode) return -EINVAL;
 158
 159         laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
 160         laddr[1] = laddr[2] = 0;
 161         of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
 162         DBG("mpc86xx_hpcn: pci irq addr %x, slot %d, pin %d, irq %d\n",
 163                         laddr[0], slot, pin, oirq.specifier[0]);
 164         return oirq.specifier[0];
 165 }
 166
 167 static void __devinit quirk_uli1575(struct pci_dev *dev)
 168 {
 169         unsigned short temp;
 170         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 171         unsigned char irq2pin[16];
 172         unsigned long pirq_map_word = 0;
 173         u32 irq;
 174         int i;
 175
 176         /*
 177          * ULI1575 interrupts route setup
 178          */
 179         memset(irq2pin, 0, 16); /* Initialize default value 0 */
 180
 181         /*
 182          * PIRQA -> PIRQD mapping read from OF-tree
 183          *
 184          * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
 185          *                PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
 186          */
 187         for (i = 0; i < 4; i++){
 188                 irq = get_pci_irq_from_of(hose, 17, i + 1);
 189                 if (irq > 0 && irq < 16)
 190                         irq2pin[irq] = PIRQA + i;
 191                 else
 192                         printk(KERN_WARNING "ULI1575 device"
 193                             "(slot %d, pin %d) irq %d is invalid.\n",
 194                             17, i, irq);
 195         }
 196
 197         /*
 198          * PIRQE -> PIRQF mapping set manually
 199          *
 200          * IRQ pin   IRQ#
 201          * PIRQE ---- 9
 202          * PIRQF ---- 10
 203          * PIRQG ---- 11
 204          * PIRQH ---- 12
 205          */
 206         for (i = 0; i < 4; i++) irq2pin[i + 9] = PIRQE + i;
 207
 208         /* Set IRQ-PIRQ Mapping to ULI1575 */
 209         for (i = 0; i < 16; i++)
 210                 if (irq2pin[i])
 211                         pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
 212                                 << ((irq2pin[i] - PIRQA) * 4);
 213
 214         /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
 215         DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
 216                         pirq_map_word);
 217         pci_write_config_dword(dev, 0x48, pirq_map_word);
 218
 219 #define ULI1575_SET_DEV_IRQ(slot, pin, reg)                             \
 220         do {                                                            \
 221                 int irq;                                                \
 222                 irq = get_pci_irq_from_of(hose, slot, pin);             \
 223                 if (irq > 0 && irq < 16)                                \
 224                         pci_write_config_byte(dev, reg, irq2pin[irq]);  \
 225                 else                                                    \
 226                         printk(KERN_WARNING "ULI1575 device"            \
 227                             "(slot %d, pin %d) irq %d is invalid.\n",   \
 228                             slot, pin, irq);                            \
 229         } while(0)
 230
 231         /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
 232         ULI1575_SET_DEV_IRQ(28, 1, 0x86);
 233
 234         /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
 235         ULI1575_SET_DEV_IRQ(28, 2, 0x87);
 236
 237         /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
 238         ULI1575_SET_DEV_IRQ(28, 3, 0x88);
 239
 240         /* USB 2.0 controller, slot 28, pin 4 */
 241         irq = get_pci_irq_from_of(hose, 28, 4);
 242         if (irq >= 0 && irq <=15)
 243                 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
 244
 245         /* Audio controller, slot 29, pin 1 */
 246         ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
 247
 248         /* Modem controller, slot 29, pin 2 */
 249         ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
 250
 251         /* HD audio controller, slot 29, pin 3 */
 252         ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
 253
 254         /* SMB interrupt: slot 30, pin 1 */
 255         ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
 256
 257         /* PMU ACPI SCI interrupt: slot 30, pin 2 */
 258         ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
 259
 260         /* Serial ATA interrupt: slot 31, pin 1 */
 261         ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
 262
 263         /* Primary PATA IDE IRQ: 14
 264          * Secondary PATA IDE IRQ: 15
 265          */
 266         pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
 267         pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
 268
 269         /* Set IRQ14 and IRQ15 to legacy IRQs */
 270         pci_read_config_word(dev, 0x46, &temp);
 271         temp |= 0xc000;
 272         pci_write_config_word(dev, 0x46, temp);
 273
 274         /* Set i8259 interrupt trigger
 275          * IRQ 3:  Level
 276          * IRQ 4:  Level
 277          * IRQ 5:  Level
 278          * IRQ 6:  Level
 279          * IRQ 7:  Level
 280          * IRQ 9:  Level
 281          * IRQ 10: Level
 282          * IRQ 11: Level
 283          * IRQ 12: Level
 284          * IRQ 14: Edge
 285          * IRQ 15: Edge
 286          */
 287         outb(0xfa, 0x4d0);
 288         outb(0x1e, 0x4d1);
 289
 290 #undef ULI1575_SET_DEV_IRQ
 291 }
 292
 293 static void __devinit quirk_uli5288(struct pci_dev *dev)
 294 {
 295         unsigned char c;
 296
 297         pci_read_config_byte(dev,0x83,&c);
 298         c |= 0x80;
 299         pci_write_config_byte(dev, 0x83, c);
 300
 301         pci_write_config_byte(dev, 0x09, 0x01);
 302         pci_write_config_byte(dev, 0x0a, 0x06);
 303
 304         pci_read_config_byte(dev,0x83,&c);
 305         c &= 0x7f;
 306         pci_write_config_byte(dev, 0x83, c);
 307
 308         pci_read_config_byte(dev,0x84,&c);
 309         c |= 0x01;
 310         pci_write_config_byte(dev, 0x84, c);
 311 }
 312
 313 static void __devinit quirk_uli5229(struct pci_dev *dev)
 314 {
 315         unsigned short temp;
 316         pci_write_config_word(dev, 0x04, 0x0405);
 317         pci_read_config_word(dev, 0x4a, &temp);
 318         temp |= 0x1000;
 319         pci_write_config_word(dev, 0x4a, temp);
 320 }
 321
 322 static void __devinit early_uli5249(struct pci_dev *dev)
 323 {
 324         unsigned char temp;
 325         pci_write_config_word(dev, 0x04, 0x0007);
 326         pci_read_config_byte(dev, 0x7c, &temp);
 327         pci_write_config_byte(dev, 0x7c, 0x80);
 328         pci_write_config_byte(dev, 0x09, 0x01);
 329         pci_write_config_byte(dev, 0x7c, temp);
 330         dev->class |= 0x1;
 331 }
 332
 333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
 334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
 335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 336 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
 337 #endif /* CONFIG_PCI */
 338
 339
 340 static void __init
 341 mpc86xx_hpcn_setup_arch(void)
 342 {
 343         struct device_node *np;
 344
 345         if (ppc_md.progress)
 346                 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
 347
 348         np = of_find_node_by_type(NULL, "cpu");
 349         if (np != 0) {
 350                 const unsigned int *fp;
 351
 352                 fp = get_property(np, "clock-frequency", NULL);
 353                 if (fp != 0)
 354                         loops_per_jiffy = *fp / HZ;
 355                 else
 356                         loops_per_jiffy = 50000000 / HZ;
 357                 of_node_put(np);
 358         }
 359
 360 #ifdef CONFIG_PCI
 361         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 362                 add_bridge(np);
 363
 364         ppc_md.pci_exclude_device = mpc86xx_exclude_device;
 365 #endif
 366
 367         printk("MPC86xx HPCN board from Freescale Semiconductor\n");
 368
 369 #ifdef CONFIG_SMP
 370         mpc86xx_smp_init();
 371 #endif
 372 }
 373
 374
 375 void
 376 mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
 377 {
 378         struct device_node *root;
 379         uint memsize = total_memory;
 380         const char *model = "";
 381         uint svid = mfspr(SPRN_SVR);
 382
 383         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 384
 385         root = of_find_node_by_path("/");
 386         if (root)
 387                 model = get_property(root, "model", NULL);
 388         seq_printf(m, "Machine\t\t: %s\n", model);
 389         of_node_put(root);
 390
 391         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 392         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 393 }
 394
 395
 396 /*
 397  * Called very early, device-tree isn't unflattened
 398  */
 399 static int __init mpc86xx_hpcn_probe(void)
 400 {
 401         unsigned long root = of_get_flat_dt_root();
 402
 403         if (of_flat_dt_is_compatible(root, "mpc86xx"))
 404                 return 1;       /* Looks good */
 405
 406         return 0;
 407 }
 408
 409
 410 void
 411 mpc86xx_restart(char *cmd)
 412 {
 413         void __iomem *rstcr;
 414
 415         rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
 416
 417         local_irq_disable();
 418
 419         /* Assert reset request to Reset Control Register */
 420         out_be32(rstcr, 0x2);
 421
 422         /* not reached */
 423 }
 424
 425
 426 long __init
 427 mpc86xx_time_init(void)
 428 {
 429         unsigned int temp;
 430
 431         /* Set the time base to zero */
 432         mtspr(SPRN_TBWL, 0);
 433         mtspr(SPRN_TBWU, 0);
 434
 435         temp = mfspr(SPRN_HID0);
 436         temp |= HID0_TBEN;
 437         mtspr(SPRN_HID0, temp);
 438         asm volatile("isync");
 439
 440         return 0;
 441 }
 442
 443
 444 define_machine(mpc86xx_hpcn) {
 445         .name                   = "MPC86xx HPCN",
 446         .probe                  = mpc86xx_hpcn_probe,
 447         .setup_arch             = mpc86xx_hpcn_setup_arch,
 448         .init_IRQ               = mpc86xx_hpcn_init_irq,
 449         .show_cpuinfo           = mpc86xx_hpcn_show_cpuinfo,
 450         .get_irq                = mpic_get_irq,
 451         .restart                = mpc86xx_restart,
 452         .time_init              = mpc86xx_time_init,
 453         .calibrate_decr         = generic_calibrate_decr,
 454         .progress               = udbg_progress,
 455 };