arch/powerpc/platforms/cell/spu_base.c

   1 /*
   2  * Low-level SPU handling
   3  *
   4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *
   6  * Author: Arnd Bergmann <arndb@de.ibm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #undef DEBUG
  24
  25 #include <linux/interrupt.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/ptrace.h>
  29 #include <linux/slab.h>
  30 #include <linux/wait.h>
  31 #include <linux/mm.h>
  32 #include <linux/io.h>
  33 #include <linux/mutex.h>
  34 #include <asm/spu.h>
  35 #include <asm/spu_priv1.h>
  36 #include <asm/xmon.h>
  37
  38 const struct spu_management_ops *spu_management_ops;
  39 const struct spu_priv1_ops *spu_priv1_ops;
  40
  41 static struct list_head spu_list[MAX_NUMNODES];
  42 static LIST_HEAD(spu_full_list);
  43 static DEFINE_MUTEX(spu_mutex);
  44 static spinlock_t spu_list_lock = SPIN_LOCK_UNLOCKED;
  45
  46 EXPORT_SYMBOL_GPL(spu_priv1_ops);
  47
  48 void spu_invalidate_slbs(struct spu *spu)
  49 {
  50         struct spu_priv2 __iomem *priv2 = spu->priv2;
  51
  52         if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
  53                 out_be64(&priv2->slb_invalidate_all_W, 0UL);
  54 }
  55 EXPORT_SYMBOL_GPL(spu_invalidate_slbs);
  56
  57 /* This is called by the MM core when a segment size is changed, to
  58  * request a flush of all the SPEs using a given mm
  59  */
  60 void spu_flush_all_slbs(struct mm_struct *mm)
  61 {
  62         struct spu *spu;
  63         unsigned long flags;
  64
  65         spin_lock_irqsave(&spu_list_lock, flags);
  66         list_for_each_entry(spu, &spu_full_list, full_list) {
  67                 if (spu->mm == mm)
  68                         spu_invalidate_slbs(spu);
  69         }
  70         spin_unlock_irqrestore(&spu_list_lock, flags);
  71 }
  72
  73 /* The hack below stinks... try to do something better one of
  74  * these days... Does it even work properly with NR_CPUS == 1 ?
  75  */
  76 static inline void mm_needs_global_tlbie(struct mm_struct *mm)
  77 {
  78         int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1;
  79
  80         /* Global TLBIE broadcast required with SPEs. */
  81         __cpus_setall(&mm->cpu_vm_mask, nr);
  82 }
  83
  84 void spu_associate_mm(struct spu *spu, struct mm_struct *mm)
  85 {
  86         unsigned long flags;
  87
  88         spin_lock_irqsave(&spu_list_lock, flags);
  89         spu->mm = mm;
  90         spin_unlock_irqrestore(&spu_list_lock, flags);
  91         if (mm)
  92                 mm_needs_global_tlbie(mm);
  93 }
  94 EXPORT_SYMBOL_GPL(spu_associate_mm);
  95
  96 static int __spu_trap_invalid_dma(struct spu *spu)
  97 {
  98         pr_debug("%s\n", __FUNCTION__);
  99         spu->dma_callback(spu, SPE_EVENT_INVALID_DMA);
 100         return 0;
 101 }
 102
 103 static int __spu_trap_dma_align(struct spu *spu)
 104 {
 105         pr_debug("%s\n", __FUNCTION__);
 106         spu->dma_callback(spu, SPE_EVENT_DMA_ALIGNMENT);
 107         return 0;
 108 }
 109
 110 static int __spu_trap_error(struct spu *spu)
 111 {
 112         pr_debug("%s\n", __FUNCTION__);
 113         spu->dma_callback(spu, SPE_EVENT_SPE_ERROR);
 114         return 0;
 115 }
 116
 117 static void spu_restart_dma(struct spu *spu)
 118 {
 119         struct spu_priv2 __iomem *priv2 = spu->priv2;
 120
 121         if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
 122                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
 123 }
 124
 125 static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
 126 {
 127         struct spu_priv2 __iomem *priv2 = spu->priv2;
 128         struct mm_struct *mm = spu->mm;
 129         u64 esid, vsid, llp;
 130         int psize;
 131
 132         pr_debug("%s\n", __FUNCTION__);
 133
 134         if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
 135                 /* SLBs are pre-loaded for context switch, so
 136                  * we should never get here!
 137                  */
 138                 printk("%s: invalid access during switch!\n", __func__);
 139                 return 1;
 140         }
 141         esid = (ea & ESID_MASK) | SLB_ESID_V;
 142
 143         switch(REGION_ID(ea)) {
 144         case USER_REGION_ID:
 145 #ifdef CONFIG_HUGETLB_PAGE
 146                 if (in_hugepage_area(mm->context, ea))
 147                         psize = mmu_huge_psize;
 148                 else
 149 #endif
 150                         psize = mm->context.user_psize;
 151                 vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) |
 152                                 SLB_VSID_USER;
 153                 break;
 154         case VMALLOC_REGION_ID:
 155                 if (ea < VMALLOC_END)
 156                         psize = mmu_vmalloc_psize;
 157                 else
 158                         psize = mmu_io_psize;
 159                 vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
 160                         SLB_VSID_KERNEL;
 161                 break;
 162         case KERNEL_REGION_ID:
 163                 psize = mmu_linear_psize;
 164                 vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
 165                         SLB_VSID_KERNEL;
 166                 break;
 167         default:
 168                 /* Future: support kernel segments so that drivers
 169                  * can use SPUs.
 170                  */
 171                 pr_debug("invalid region access at %016lx\n", ea);
 172                 return 1;
 173         }
 174         llp = mmu_psize_defs[psize].sllp;
 175
 176         out_be64(&priv2->slb_index_W, spu->slb_replace);
 177         out_be64(&priv2->slb_vsid_RW, vsid | llp);
 178         out_be64(&priv2->slb_esid_RW, esid);
 179
 180         spu->slb_replace++;
 181         if (spu->slb_replace >= 8)
 182                 spu->slb_replace = 0;
 183
 184         spu_restart_dma(spu);
 185
 186         return 0;
 187 }
 188
 189 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
 190 static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
 191 {
 192         pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);
 193
 194         /* Handle kernel space hash faults immediately.
 195            User hash faults need to be deferred to process context. */
 196         if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
 197             && REGION_ID(ea) != USER_REGION_ID
 198             && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
 199                 spu_restart_dma(spu);
 200                 return 0;
 201         }
 202
 203         if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
 204                 printk("%s: invalid access during switch!\n", __func__);
 205                 return 1;
 206         }
 207
 208         spu->dar = ea;
 209         spu->dsisr = dsisr;
 210         mb();
 211         spu->stop_callback(spu);
 212         return 0;
 213 }
 214
 215 static irqreturn_t
 216 spu_irq_class_0(int irq, void *data)
 217 {
 218         struct spu *spu;
 219
 220         spu = data;
 221         spu->class_0_pending = 1;
 222         spu->stop_callback(spu);
 223
 224         return IRQ_HANDLED;
 225 }
 226
 227 int
 228 spu_irq_class_0_bottom(struct spu *spu)
 229 {
 230         unsigned long stat, mask;
 231         unsigned long flags;
 232
 233         spu->class_0_pending = 0;
 234
 235         spin_lock_irqsave(&spu->register_lock, flags);
 236         mask = spu_int_mask_get(spu, 0);
 237         stat = spu_int_stat_get(spu, 0);
 238
 239         stat &= mask;
 240
 241         if (stat & 1) /* invalid DMA alignment */
 242                 __spu_trap_dma_align(spu);
 243
 244         if (stat & 2) /* invalid MFC DMA */
 245                 __spu_trap_invalid_dma(spu);
 246
 247         if (stat & 4) /* error on SPU */
 248                 __spu_trap_error(spu);
 249
 250         spu_int_stat_clear(spu, 0, stat);
 251         spin_unlock_irqrestore(&spu->register_lock, flags);
 252
 253         return (stat & 0x7) ? -EIO : 0;
 254 }
 255 EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);
 256
 257 static irqreturn_t
 258 spu_irq_class_1(int irq, void *data)
 259 {
 260         struct spu *spu;
 261         unsigned long stat, mask, dar, dsisr;
 262
 263         spu = data;
 264
 265         /* atomically read & clear class1 status. */
 266         spin_lock(&spu->register_lock);
 267         mask  = spu_int_mask_get(spu, 1);
 268         stat  = spu_int_stat_get(spu, 1) & mask;
 269         dar   = spu_mfc_dar_get(spu);
 270         dsisr = spu_mfc_dsisr_get(spu);
 271         if (stat & 2) /* mapping fault */
 272                 spu_mfc_dsisr_set(spu, 0ul);
 273         spu_int_stat_clear(spu, 1, stat);
 274         spin_unlock(&spu->register_lock);
 275         pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
 276                         dar, dsisr);
 277
 278         if (stat & 1) /* segment fault */
 279                 __spu_trap_data_seg(spu, dar);
 280
 281         if (stat & 2) { /* mapping fault */
 282                 __spu_trap_data_map(spu, dar, dsisr);
 283         }
 284
 285         if (stat & 4) /* ls compare & suspend on get */
 286                 ;
 287
 288         if (stat & 8) /* ls compare & suspend on put */
 289                 ;
 290
 291         return stat ? IRQ_HANDLED : IRQ_NONE;
 292 }
 293 EXPORT_SYMBOL_GPL(spu_irq_class_1_bottom);
 294
 295 static irqreturn_t
 296 spu_irq_class_2(int irq, void *data)
 297 {
 298         struct spu *spu;
 299         unsigned long stat;
 300         unsigned long mask;
 301
 302         spu = data;
 303         spin_lock(&spu->register_lock);
 304         stat = spu_int_stat_get(spu, 2);
 305         mask = spu_int_mask_get(spu, 2);
 306         /* ignore interrupts we're not waiting for */
 307         stat &= mask;
 308         /*
 309          * mailbox interrupts (0x1 and 0x10) are level triggered.
 310          * mask them now before acknowledging.
 311          */
 312         if (stat & 0x11)
 313                 spu_int_mask_and(spu, 2, ~(stat & 0x11));
 314         /* acknowledge all interrupts before the callbacks */
 315         spu_int_stat_clear(spu, 2, stat);
 316         spin_unlock(&spu->register_lock);
 317
 318         pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
 319
 320         if (stat & 1)  /* PPC core mailbox */
 321                 spu->ibox_callback(spu);
 322
 323         if (stat & 2) /* SPU stop-and-signal */
 324                 spu->stop_callback(spu);
 325
 326         if (stat & 4) /* SPU halted */
 327                 spu->stop_callback(spu);
 328
 329         if (stat & 8) /* DMA tag group complete */
 330                 spu->mfc_callback(spu);
 331
 332         if (stat & 0x10) /* SPU mailbox threshold */
 333                 spu->wbox_callback(spu);
 334
 335         return stat ? IRQ_HANDLED : IRQ_NONE;
 336 }
 337
 338 static int spu_request_irqs(struct spu *spu)
 339 {
 340         int ret = 0;
 341
 342         if (spu->irqs[0] != NO_IRQ) {
 343                 snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",
 344                          spu->number);
 345                 ret = request_irq(spu->irqs[0], spu_irq_class_0,
 346                                   IRQF_DISABLED,
 347                                   spu->irq_c0, spu);
 348                 if (ret)
 349                         goto bail0;
 350         }
 351         if (spu->irqs[1] != NO_IRQ) {
 352                 snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",
 353                          spu->number);
 354                 ret = request_irq(spu->irqs[1], spu_irq_class_1,
 355                                   IRQF_DISABLED,
 356                                   spu->irq_c1, spu);
 357                 if (ret)
 358                         goto bail1;
 359         }
 360         if (spu->irqs[2] != NO_IRQ) {
 361                 snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",
 362                          spu->number);
 363                 ret = request_irq(spu->irqs[2], spu_irq_class_2,
 364                                   IRQF_DISABLED,
 365                                   spu->irq_c2, spu);
 366                 if (ret)
 367                         goto bail2;
 368         }
 369         return 0;
 370
 371 bail2:
 372         if (spu->irqs[1] != NO_IRQ)
 373                 free_irq(spu->irqs[1], spu);
 374 bail1:
 375         if (spu->irqs[0] != NO_IRQ)
 376                 free_irq(spu->irqs[0], spu);
 377 bail0:
 378         return ret;
 379 }
 380
 381 static void spu_free_irqs(struct spu *spu)
 382 {
 383         if (spu->irqs[0] != NO_IRQ)
 384                 free_irq(spu->irqs[0], spu);
 385         if (spu->irqs[1] != NO_IRQ)
 386                 free_irq(spu->irqs[1], spu);
 387         if (spu->irqs[2] != NO_IRQ)
 388                 free_irq(spu->irqs[2], spu);
 389 }
 390
 391 static void spu_init_channels(struct spu *spu)
 392 {
 393         static const struct {
 394                  unsigned channel;
 395                  unsigned count;
 396         } zero_list[] = {
 397                 { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
 398                 { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
 399         }, count_list[] = {
 400                 { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
 401                 { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
 402                 { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
 403         };
 404         struct spu_priv2 __iomem *priv2;
 405         int i;
 406
 407         priv2 = spu->priv2;
 408
 409         /* initialize all channel data to zero */
 410         for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
 411                 int count;
 412
 413                 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
 414                 for (count = 0; count < zero_list[i].count; count++)
 415                         out_be64(&priv2->spu_chnldata_RW, 0);
 416         }
 417
 418         /* initialize channel counts to meaningful values */
 419         for (i = 0; i < ARRAY_SIZE(count_list); i++) {
 420                 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
 421                 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
 422         }
 423 }
 424
 425 struct spu *spu_alloc_node(int node)
 426 {
 427         struct spu *spu = NULL;
 428
 429         mutex_lock(&spu_mutex);
 430         if (!list_empty(&spu_list[node])) {
 431                 spu = list_entry(spu_list[node].next, struct spu, list);
 432                 list_del_init(&spu->list);
 433                 pr_debug("Got SPU %d %d\n", spu->number, spu->node);
 434                 spu_init_channels(spu);
 435         }
 436         mutex_unlock(&spu_mutex);
 437
 438         return spu;
 439 }
 440 EXPORT_SYMBOL_GPL(spu_alloc_node);
 441
 442 struct spu *spu_alloc(void)
 443 {
 444         struct spu *spu = NULL;
 445         int node;
 446
 447         for (node = 0; node < MAX_NUMNODES; node++) {
 448                 spu = spu_alloc_node(node);
 449                 if (spu)
 450                         break;
 451         }
 452
 453         return spu;
 454 }
 455
 456 void spu_free(struct spu *spu)
 457 {
 458         mutex_lock(&spu_mutex);
 459         list_add_tail(&spu->list, &spu_list[spu->node]);
 460         mutex_unlock(&spu_mutex);
 461 }
 462 EXPORT_SYMBOL_GPL(spu_free);
 463
 464 static int spu_handle_mm_fault(struct spu *spu)
 465 {
 466         struct mm_struct *mm = spu->mm;
 467         struct vm_area_struct *vma;
 468         u64 ea, dsisr, is_write;
 469         int ret;
 470
 471         ea = spu->dar;
 472         dsisr = spu->dsisr;
 473 #if 0
 474         if (!IS_VALID_EA(ea)) {
 475                 return -EFAULT;
 476         }
 477 #endif /* XXX */
 478         if (mm == NULL) {
 479                 return -EFAULT;
 480         }
 481         if (mm->pgd == NULL) {
 482                 return -EFAULT;
 483         }
 484
 485         down_read(&mm->mmap_sem);
 486         vma = find_vma(mm, ea);
 487         if (!vma)
 488                 goto bad_area;
 489         if (vma->vm_start <= ea)
 490                 goto good_area;
 491         if (!(vma->vm_flags & VM_GROWSDOWN))
 492                 goto bad_area;
 493 #if 0
 494         if (expand_stack(vma, ea))
 495                 goto bad_area;
 496 #endif /* XXX */
 497 good_area:
 498         is_write = dsisr & MFC_DSISR_ACCESS_PUT;
 499         if (is_write) {
 500                 if (!(vma->vm_flags & VM_WRITE))
 501                         goto bad_area;
 502         } else {
 503                 if (dsisr & MFC_DSISR_ACCESS_DENIED)
 504                         goto bad_area;
 505                 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
 506                         goto bad_area;
 507         }
 508         ret = 0;
 509         switch (handle_mm_fault(mm, vma, ea, is_write)) {
 510         case VM_FAULT_MINOR:
 511                 current->min_flt++;
 512                 break;
 513         case VM_FAULT_MAJOR:
 514                 current->maj_flt++;
 515                 break;
 516         case VM_FAULT_SIGBUS:
 517                 ret = -EFAULT;
 518                 goto bad_area;
 519         case VM_FAULT_OOM:
 520                 ret = -ENOMEM;
 521                 goto bad_area;
 522         default:
 523                 BUG();
 524         }
 525         up_read(&mm->mmap_sem);
 526         return ret;
 527
 528 bad_area:
 529         up_read(&mm->mmap_sem);
 530         return -EFAULT;
 531 }
 532
 533 int spu_irq_class_1_bottom(struct spu *spu)
 534 {
 535         u64 ea, dsisr, access, error = 0UL;
 536         int ret = 0;
 537
 538         ea = spu->dar;
 539         dsisr = spu->dsisr;
 540         if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)) {
 541                 u64 flags;
 542
 543                 access = (_PAGE_PRESENT | _PAGE_USER);
 544                 access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
 545                 local_irq_save(flags);
 546                 if (hash_page(ea, access, 0x300) != 0)
 547                         error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
 548                 local_irq_restore(flags);
 549         }
 550         if (error & CLASS1_ENABLE_STORAGE_FAULT_INTR) {
 551                 if ((ret = spu_handle_mm_fault(spu)) != 0)
 552                         error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
 553                 else
 554                         error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
 555         }
 556         spu->dar = 0UL;
 557         spu->dsisr = 0UL;
 558         if (!error) {
 559                 spu_restart_dma(spu);
 560         } else {
 561                 spu->dma_callback(spu, SPE_EVENT_SPE_DATA_STORAGE);
 562         }
 563         return ret;
 564 }
 565
 566 struct sysdev_class spu_sysdev_class = {
 567         set_kset_name("spu")
 568 };
 569
 570 int spu_add_sysdev_attr(struct sysdev_attribute *attr)
 571 {
 572         struct spu *spu;
 573         mutex_lock(&spu_mutex);
 574
 575         list_for_each_entry(spu, &spu_full_list, full_list)
 576                 sysdev_create_file(&spu->sysdev, attr);
 577
 578         mutex_unlock(&spu_mutex);
 579         return 0;
 580 }
 581 EXPORT_SYMBOL_GPL(spu_add_sysdev_attr);
 582
 583 int spu_add_sysdev_attr_group(struct attribute_group *attrs)
 584 {
 585         struct spu *spu;
 586         mutex_lock(&spu_mutex);
 587
 588         list_for_each_entry(spu, &spu_full_list, full_list)
 589                 sysfs_create_group(&spu->sysdev.kobj, attrs);
 590
 591         mutex_unlock(&spu_mutex);
 592         return 0;
 593 }
 594 EXPORT_SYMBOL_GPL(spu_add_sysdev_attr_group);
 595
 596
 597 void spu_remove_sysdev_attr(struct sysdev_attribute *attr)
 598 {
 599         struct spu *spu;
 600         mutex_lock(&spu_mutex);
 601
 602         list_for_each_entry(spu, &spu_full_list, full_list)
 603                 sysdev_remove_file(&spu->sysdev, attr);
 604
 605         mutex_unlock(&spu_mutex);
 606 }
 607 EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr);
 608
 609 void spu_remove_sysdev_attr_group(struct attribute_group *attrs)
 610 {
 611         struct spu *spu;
 612         mutex_lock(&spu_mutex);
 613
 614         list_for_each_entry(spu, &spu_full_list, full_list)
 615                 sysfs_remove_group(&spu->sysdev.kobj, attrs);
 616
 617         mutex_unlock(&spu_mutex);
 618 }
 619 EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr_group);
 620
 621 static int spu_create_sysdev(struct spu *spu)
 622 {
 623         int ret;
 624
 625         spu->sysdev.id = spu->number;
 626         spu->sysdev.cls = &spu_sysdev_class;
 627         ret = sysdev_register(&spu->sysdev);
 628         if (ret) {
 629                 printk(KERN_ERR "Can't register SPU %d with sysfs\n",
 630                                 spu->number);
 631                 return ret;
 632         }
 633
 634         sysfs_add_device_to_node(&spu->sysdev, spu->node);
 635
 636         return 0;
 637 }
 638
 639 static void spu_destroy_sysdev(struct spu *spu)
 640 {
 641         sysfs_remove_device_from_node(&spu->sysdev, spu->node);
 642         sysdev_unregister(&spu->sysdev);
 643 }
 644
 645 static int __init create_spu(void *data)
 646 {
 647         struct spu *spu;
 648         int ret;
 649         static int number;
 650         unsigned long flags;
 651
 652         ret = -ENOMEM;
 653         spu = kzalloc(sizeof (*spu), GFP_KERNEL);
 654         if (!spu)
 655                 goto out;
 656
 657         spin_lock_init(&spu->register_lock);
 658         mutex_lock(&spu_mutex);
 659         spu->number = number++;
 660         mutex_unlock(&spu_mutex);
 661
 662         ret = spu_create_spu(spu, data);
 663
 664         if (ret)
 665                 goto out_free;
 666
 667         spu_mfc_sdr_setup(spu);
 668         spu_mfc_sr1_set(spu, 0x33);
 669         ret = spu_request_irqs(spu);
 670         if (ret)
 671                 goto out_destroy;
 672
 673         ret = spu_create_sysdev(spu);
 674         if (ret)
 675                 goto out_free_irqs;
 676
 677         mutex_lock(&spu_mutex);
 678         spin_lock_irqsave(&spu_list_lock, flags);
 679         list_add(&spu->list, &spu_list[spu->node]);
 680         list_add(&spu->full_list, &spu_full_list);
 681         spin_unlock_irqrestore(&spu_list_lock, flags);
 682         mutex_unlock(&spu_mutex);
 683
 684         goto out;
 685
 686 out_free_irqs:
 687         spu_free_irqs(spu);
 688 out_destroy:
 689         spu_destroy_spu(spu);
 690 out_free:
 691         kfree(spu);
 692 out:
 693         return ret;
 694 }
 695
 696 static void destroy_spu(struct spu *spu)
 697 {
 698         list_del_init(&spu->list);
 699         list_del_init(&spu->full_list);
 700
 701         spu_destroy_sysdev(spu);
 702         spu_free_irqs(spu);
 703         spu_destroy_spu(spu);
 704         kfree(spu);
 705 }
 706
 707 static void cleanup_spu_base(void)
 708 {
 709         struct spu *spu, *tmp;
 710         int node;
 711
 712         mutex_lock(&spu_mutex);
 713         for (node = 0; node < MAX_NUMNODES; node++) {
 714                 list_for_each_entry_safe(spu, tmp, &spu_list[node], list)
 715                         destroy_spu(spu);
 716         }
 717         mutex_unlock(&spu_mutex);
 718         sysdev_class_unregister(&spu_sysdev_class);
 719 }
 720 module_exit(cleanup_spu_base);
 721
 722 static int __init init_spu_base(void)
 723 {
 724         int i, ret;
 725
 726         if (!spu_management_ops)
 727                 return 0;
 728
 729         /* create sysdev class for spus */
 730         ret = sysdev_class_register(&spu_sysdev_class);
 731         if (ret)
 732                 return ret;
 733
 734         for (i = 0; i < MAX_NUMNODES; i++)
 735                 INIT_LIST_HEAD(&spu_list[i]);
 736
 737         ret = spu_enumerate_spus(create_spu);
 738
 739         if (ret) {
 740                 printk(KERN_WARNING "%s: Error initializing spus\n",
 741                         __FUNCTION__);
 742                 cleanup_spu_base();
 743                 return ret;
 744         }
 745
 746         xmon_register_spus(&spu_full_list);
 747
 748         return ret;
 749 }
 750 module_init(init_spu_base);
 751
 752 MODULE_LICENSE("GPL");
 753 MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");