arch/sparc64/kernel/irq.c

   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/sched.h>
  11 #include <linux/ptrace.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/signal.h>
  15 #include <linux/mm.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/slab.h>
  18 #include <linux/random.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/irq.h>
  25 #include <linux/msi.h>
  26
  27 #include <asm/ptrace.h>
  28 #include <asm/processor.h>
  29 #include <asm/atomic.h>
  30 #include <asm/system.h>
  31 #include <asm/irq.h>
  32 #include <asm/io.h>
  33 #include <asm/sbus.h>
  34 #include <asm/iommu.h>
  35 #include <asm/upa.h>
  36 #include <asm/oplib.h>
  37 #include <asm/prom.h>
  38 #include <asm/timer.h>
  39 #include <asm/smp.h>
  40 #include <asm/starfire.h>
  41 #include <asm/uaccess.h>
  42 #include <asm/cache.h>
  43 #include <asm/cpudata.h>
  44 #include <asm/auxio.h>
  45 #include <asm/head.h>
  46
  47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  48  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  49  * delivered.  We must translate this into a non-vector IRQ so we can
  50  * set the softint on this cpu.
  51  *
  52  * To make processing these packets efficient and race free we use
  53  * an array of irq buckets below.  The interrupt vector handler in
  54  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  55  * The IVEC handler does not need to act atomically, the PIL dispatch
  56  * code uses CAS to get an atomic snapshot of the list and clear it
  57  * at the same time.
  58  *
  59  * If you make changes to ino_bucket, please update hand coded assembler
  60  * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
  61  */
  62 struct ino_bucket {
  63         /* Next handler in per-CPU IRQ worklist.  We know that
  64          * bucket pointers have the high 32-bits clear, so to
  65          * save space we only store the bits we need.
  66          */
  67 /*0x00*/unsigned int irq_chain;
  68
  69         /* Virtual interrupt number assigned to this INO.  */
  70 /*0x04*/unsigned int virt_irq;
  71 };
  72
  73 #define NUM_IVECS       (IMAP_INR + 1)
  74 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  75
  76 #define __irq_ino(irq) \
  77         (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
  78 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
  79 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
  80
  81 /* This has to be in the main kernel image, it cannot be
  82  * turned into per-cpu data.  The reason is that the main
  83  * kernel image is locked into the TLB and this structure
  84  * is accessed from the vectored interrupt trap handler.  If
  85  * access to this structure takes a TLB miss it could cause
  86  * the 5-level sparc v9 trap stack to overflow.
  87  */
  88 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
  89
  90 static unsigned int virt_to_real_irq_table[NR_IRQS];
  91
  92 static unsigned char virt_irq_alloc(unsigned int real_irq)
  93 {
  94         unsigned char ent;
  95
  96         BUILD_BUG_ON(NR_IRQS >= 256);
  97
  98         for (ent = 1; ent < NR_IRQS; ent++) {
  99                 if (!virt_to_real_irq_table[ent])
 100                         break;
 101         }
 102         if (ent >= NR_IRQS) {
 103                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 104                 return 0;
 105         }
 106
 107         virt_to_real_irq_table[ent] = real_irq;
 108
 109         return ent;
 110 }
 111
 112 #ifdef CONFIG_PCI_MSI
 113 static void virt_irq_free(unsigned int virt_irq)
 114 {
 115         unsigned int real_irq;
 116
 117         if (virt_irq >= NR_IRQS)
 118                 return;
 119
 120         real_irq = virt_to_real_irq_table[virt_irq];
 121         virt_to_real_irq_table[virt_irq] = 0;
 122
 123         __bucket(real_irq)->virt_irq = 0;
 124 }
 125 #endif
 126
 127 static unsigned int virt_to_real_irq(unsigned char virt_irq)
 128 {
 129         return virt_to_real_irq_table[virt_irq];
 130 }
 131
 132 /*
 133  * /proc/interrupts printing:
 134  */
 135
 136 int show_interrupts(struct seq_file *p, void *v)
 137 {
 138         int i = *(loff_t *) v, j;
 139         struct irqaction * action;
 140         unsigned long flags;
 141
 142         if (i == 0) {
 143                 seq_printf(p, "           ");
 144                 for_each_online_cpu(j)
 145                         seq_printf(p, "CPU%d       ",j);
 146                 seq_putc(p, '\n');
 147         }
 148
 149         if (i < NR_IRQS) {
 150                 spin_lock_irqsave(&irq_desc[i].lock, flags);
 151                 action = irq_desc[i].action;
 152                 if (!action)
 153                         goto skip;
 154                 seq_printf(p, "%3d: ",i);
 155 #ifndef CONFIG_SMP
 156                 seq_printf(p, "%10u ", kstat_irqs(i));
 157 #else
 158                 for_each_online_cpu(j)
 159                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
 160 #endif
 161                 seq_printf(p, " %9s", irq_desc[i].chip->typename);
 162                 seq_printf(p, "  %s", action->name);
 163
 164                 for (action=action->next; action; action = action->next)
 165                         seq_printf(p, ", %s", action->name);
 166
 167                 seq_putc(p, '\n');
 168 skip:
 169                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 170         }
 171         return 0;
 172 }
 173
 174 extern unsigned long real_hard_smp_processor_id(void);
 175
 176 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 177 {
 178         unsigned int tid;
 179
 180         if (this_is_starfire) {
 181                 tid = starfire_translate(imap, cpuid);
 182                 tid <<= IMAP_TID_SHIFT;
 183                 tid &= IMAP_TID_UPA;
 184         } else {
 185                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 186                         unsigned long ver;
 187
 188                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 189                         if ((ver >> 32UL) == __JALAPENO_ID ||
 190                             (ver >> 32UL) == __SERRANO_ID) {
 191                                 tid = cpuid << IMAP_TID_SHIFT;
 192                                 tid &= IMAP_TID_JBUS;
 193                         } else {
 194                                 unsigned int a = cpuid & 0x1f;
 195                                 unsigned int n = (cpuid >> 5) & 0x1f;
 196
 197                                 tid = ((a << IMAP_AID_SHIFT) |
 198                                        (n << IMAP_NID_SHIFT));
 199                                 tid &= (IMAP_AID_SAFARI |
 200                                         IMAP_NID_SAFARI);;
 201                         }
 202                 } else {
 203                         tid = cpuid << IMAP_TID_SHIFT;
 204                         tid &= IMAP_TID_UPA;
 205                 }
 206         }
 207
 208         return tid;
 209 }
 210
 211 struct irq_handler_data {
 212         unsigned long   iclr;
 213         unsigned long   imap;
 214
 215         void            (*pre_handler)(unsigned int, void *, void *);
 216         void            *pre_handler_arg1;
 217         void            *pre_handler_arg2;
 218 };
 219
 220 static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
 221 {
 222         unsigned int real_irq = virt_to_real_irq(virt_irq);
 223         struct ino_bucket *bucket = NULL;
 224
 225         if (likely(real_irq))
 226                 bucket = __bucket(real_irq);
 227
 228         return bucket;
 229 }
 230
 231 #ifdef CONFIG_SMP
 232 static int irq_choose_cpu(unsigned int virt_irq)
 233 {
 234         cpumask_t mask = irq_desc[virt_irq].affinity;
 235         int cpuid;
 236
 237         if (cpus_equal(mask, CPU_MASK_ALL)) {
 238                 static int irq_rover;
 239                 static DEFINE_SPINLOCK(irq_rover_lock);
 240                 unsigned long flags;
 241
 242                 /* Round-robin distribution... */
 243         do_round_robin:
 244                 spin_lock_irqsave(&irq_rover_lock, flags);
 245
 246                 while (!cpu_online(irq_rover)) {
 247                         if (++irq_rover >= NR_CPUS)
 248                                 irq_rover = 0;
 249                 }
 250                 cpuid = irq_rover;
 251                 do {
 252                         if (++irq_rover >= NR_CPUS)
 253                                 irq_rover = 0;
 254                 } while (!cpu_online(irq_rover));
 255
 256                 spin_unlock_irqrestore(&irq_rover_lock, flags);
 257         } else {
 258                 cpumask_t tmp;
 259
 260                 cpus_and(tmp, cpu_online_map, mask);
 261
 262                 if (cpus_empty(tmp))
 263                         goto do_round_robin;
 264
 265                 cpuid = first_cpu(tmp);
 266         }
 267
 268         return cpuid;
 269 }
 270 #else
 271 static int irq_choose_cpu(unsigned int virt_irq)
 272 {
 273         return real_hard_smp_processor_id();
 274 }
 275 #endif
 276
 277 static void sun4u_irq_enable(unsigned int virt_irq)
 278 {
 279         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 280
 281         if (likely(data)) {
 282                 unsigned long cpuid, imap;
 283                 unsigned int tid;
 284
 285                 cpuid = irq_choose_cpu(virt_irq);
 286                 imap = data->imap;
 287
 288                 tid = sun4u_compute_tid(imap, cpuid);
 289
 290                 upa_writel(tid | IMAP_VALID, imap);
 291         }
 292 }
 293
 294 static void sun4u_irq_disable(unsigned int virt_irq)
 295 {
 296         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 297
 298         if (likely(data)) {
 299                 unsigned long imap = data->imap;
 300                 u32 tmp = upa_readl(imap);
 301
 302                 tmp &= ~IMAP_VALID;
 303                 upa_writel(tmp, imap);
 304         }
 305 }
 306
 307 static void sun4u_irq_end(unsigned int virt_irq)
 308 {
 309         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 310
 311         if (likely(data))
 312                 upa_writel(ICLR_IDLE, data->iclr);
 313 }
 314
 315 static void sun4v_irq_enable(unsigned int virt_irq)
 316 {
 317         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
 318         unsigned int ino = bucket - &ivector_table[0];
 319
 320         if (likely(bucket)) {
 321                 unsigned long cpuid;
 322                 int err;
 323
 324                 cpuid = irq_choose_cpu(virt_irq);
 325
 326                 err = sun4v_intr_settarget(ino, cpuid);
 327                 if (err != HV_EOK)
 328                         printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
 329                                ino, cpuid, err);
 330                 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 331                 if (err != HV_EOK)
 332                         printk("sun4v_intr_setenabled(%x): err(%d)\n",
 333                                ino, err);
 334         }
 335 }
 336
 337 static void sun4v_irq_disable(unsigned int virt_irq)
 338 {
 339         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
 340         unsigned int ino = bucket - &ivector_table[0];
 341
 342         if (likely(bucket)) {
 343                 int err;
 344
 345                 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 346                 if (err != HV_EOK)
 347                         printk("sun4v_intr_setenabled(%x): "
 348                                "err(%d)\n", ino, err);
 349         }
 350 }
 351
 352 #ifdef CONFIG_PCI_MSI
 353 static void sun4v_msi_enable(unsigned int virt_irq)
 354 {
 355         sun4v_irq_enable(virt_irq);
 356         unmask_msi_irq(virt_irq);
 357 }
 358
 359 static void sun4v_msi_disable(unsigned int virt_irq)
 360 {
 361         mask_msi_irq(virt_irq);
 362         sun4v_irq_disable(virt_irq);
 363 }
 364 #endif
 365
 366 static void sun4v_irq_end(unsigned int virt_irq)
 367 {
 368         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
 369         unsigned int ino = bucket - &ivector_table[0];
 370
 371         if (likely(bucket)) {
 372                 int err;
 373
 374                 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 375                 if (err != HV_EOK)
 376                         printk("sun4v_intr_setstate(%x): "
 377                                "err(%d)\n", ino, err);
 378         }
 379 }
 380
 381 static void run_pre_handler(unsigned int virt_irq)
 382 {
 383         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
 384         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 385
 386         if (likely(data->pre_handler)) {
 387                 data->pre_handler(__irq_ino(__irq(bucket)),
 388                                   data->pre_handler_arg1,
 389                                   data->pre_handler_arg2);
 390         }
 391 }
 392
 393 static struct irq_chip sun4u_irq = {
 394         .typename       = "sun4u",
 395         .enable         = sun4u_irq_enable,
 396         .disable        = sun4u_irq_disable,
 397         .end            = sun4u_irq_end,
 398 };
 399
 400 static struct irq_chip sun4u_irq_ack = {
 401         .typename       = "sun4u+ack",
 402         .enable         = sun4u_irq_enable,
 403         .disable        = sun4u_irq_disable,
 404         .ack            = run_pre_handler,
 405         .end            = sun4u_irq_end,
 406 };
 407
 408 static struct irq_chip sun4v_irq = {
 409         .typename       = "sun4v",
 410         .enable         = sun4v_irq_enable,
 411         .disable        = sun4v_irq_disable,
 412         .end            = sun4v_irq_end,
 413 };
 414
 415 static struct irq_chip sun4v_irq_ack = {
 416         .typename       = "sun4v+ack",
 417         .enable         = sun4v_irq_enable,
 418         .disable        = sun4v_irq_disable,
 419         .ack            = run_pre_handler,
 420         .end            = sun4v_irq_end,
 421 };
 422
 423 #ifdef CONFIG_PCI_MSI
 424 static struct irq_chip sun4v_msi = {
 425         .typename       = "sun4v+msi",
 426         .mask           = mask_msi_irq,
 427         .unmask         = unmask_msi_irq,
 428         .enable         = sun4v_msi_enable,
 429         .disable        = sun4v_msi_disable,
 430         .ack            = run_pre_handler,
 431         .end            = sun4v_irq_end,
 432 };
 433 #endif
 434
 435 void irq_install_pre_handler(int virt_irq,
 436                              void (*func)(unsigned int, void *, void *),
 437                              void *arg1, void *arg2)
 438 {
 439         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 440         struct irq_chip *chip;
 441
 442         data->pre_handler = func;
 443         data->pre_handler_arg1 = arg1;
 444         data->pre_handler_arg2 = arg2;
 445
 446         chip = get_irq_chip(virt_irq);
 447         if (chip == &sun4u_irq_ack ||
 448             chip == &sun4v_irq_ack
 449 #ifdef CONFIG_PCI_MSI
 450             || chip == &sun4v_msi
 451 #endif
 452             )
 453                 return;
 454
 455         chip = (chip == &sun4u_irq ?
 456                 &sun4u_irq_ack : &sun4v_irq_ack);
 457         set_irq_chip(virt_irq, chip);
 458 }
 459
 460 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 461 {
 462         struct ino_bucket *bucket;
 463         struct irq_handler_data *data;
 464         int ino;
 465
 466         BUG_ON(tlb_type == hypervisor);
 467
 468         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 469         bucket = &ivector_table[ino];
 470         if (!bucket->virt_irq) {
 471                 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
 472                 set_irq_chip(bucket->virt_irq, &sun4u_irq);
 473         }
 474
 475         data = get_irq_chip_data(bucket->virt_irq);
 476         if (unlikely(data))
 477                 goto out;
 478
 479         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 480         if (unlikely(!data)) {
 481                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 482                 prom_halt();
 483         }
 484         set_irq_chip_data(bucket->virt_irq, data);
 485
 486         data->imap  = imap;
 487         data->iclr  = iclr;
 488
 489 out:
 490         return bucket->virt_irq;
 491 }
 492
 493 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 494 {
 495         struct ino_bucket *bucket;
 496         struct irq_handler_data *data;
 497         unsigned long sysino;
 498
 499         BUG_ON(tlb_type != hypervisor);
 500
 501         sysino = sun4v_devino_to_sysino(devhandle, devino);
 502         bucket = &ivector_table[sysino];
 503         if (!bucket->virt_irq) {
 504                 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
 505                 set_irq_chip(bucket->virt_irq, &sun4v_irq);
 506         }
 507
 508         data = get_irq_chip_data(bucket->virt_irq);
 509         if (unlikely(data))
 510                 goto out;
 511
 512         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 513         if (unlikely(!data)) {
 514                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 515                 prom_halt();
 516         }
 517         set_irq_chip_data(bucket->virt_irq, data);
 518
 519         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 520          * is done by hypervisor calls on sun4v platforms, not by direct
 521          * register accesses.
 522          */
 523         data->imap = ~0UL;
 524         data->iclr = ~0UL;
 525
 526 out:
 527         return bucket->virt_irq;
 528 }
 529
 530 #ifdef CONFIG_PCI_MSI
 531 unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
 532                              unsigned int msi_start, unsigned int msi_end)
 533 {
 534         struct ino_bucket *bucket;
 535         struct irq_handler_data *data;
 536         unsigned long sysino;
 537         unsigned int devino;
 538
 539         BUG_ON(tlb_type != hypervisor);
 540
 541         /* Find a free devino in the given range.  */
 542         for (devino = msi_start; devino < msi_end; devino++) {
 543                 sysino = sun4v_devino_to_sysino(devhandle, devino);
 544                 bucket = &ivector_table[sysino];
 545                 if (!bucket->virt_irq)
 546                         break;
 547         }
 548         if (devino >= msi_end)
 549                 return 0;
 550
 551         sysino = sun4v_devino_to_sysino(devhandle, devino);
 552         bucket = &ivector_table[sysino];
 553         bucket->virt_irq = virt_irq_alloc(__irq(bucket));
 554         *virt_irq_p = bucket->virt_irq;
 555         set_irq_chip(bucket->virt_irq, &sun4v_msi);
 556
 557         data = get_irq_chip_data(bucket->virt_irq);
 558         if (unlikely(data))
 559                 return devino;
 560
 561         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 562         if (unlikely(!data)) {
 563                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 564                 prom_halt();
 565         }
 566         set_irq_chip_data(bucket->virt_irq, data);
 567
 568         data->imap = ~0UL;
 569         data->iclr = ~0UL;
 570
 571         return devino;
 572 }
 573
 574 void sun4v_destroy_msi(unsigned int virt_irq)
 575 {
 576         virt_irq_free(virt_irq);
 577 }
 578 #endif
 579
 580 void ack_bad_irq(unsigned int virt_irq)
 581 {
 582         struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
 583         unsigned int ino = 0xdeadbeef;
 584
 585         if (bucket)
 586                 ino = bucket - &ivector_table[0];
 587
 588         printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
 589                ino, virt_irq);
 590 }
 591
 592 #ifndef CONFIG_SMP
 593 extern irqreturn_t timer_interrupt(int, void *);
 594
 595 void timer_irq(int irq, struct pt_regs *regs)
 596 {
 597         unsigned long clr_mask = 1 << irq;
 598         unsigned long tick_mask = tick_ops->softint_mask;
 599         struct pt_regs *old_regs;
 600
 601         if (get_softint() & tick_mask) {
 602                 irq = 0;
 603                 clr_mask = tick_mask;
 604         }
 605         clear_softint(clr_mask);
 606
 607         old_regs = set_irq_regs(regs);
 608         irq_enter();
 609
 610         kstat_this_cpu.irqs[0]++;
 611         timer_interrupt(irq, NULL);
 612
 613         irq_exit();
 614         set_irq_regs(old_regs);
 615 }
 616 #endif
 617
 618 void handler_irq(int irq, struct pt_regs *regs)
 619 {
 620         struct ino_bucket *bucket;
 621         struct pt_regs *old_regs;
 622
 623         clear_softint(1 << irq);
 624
 625         old_regs = set_irq_regs(regs);
 626         irq_enter();
 627
 628         /* Sliiiick... */
 629         bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
 630         while (bucket) {
 631                 struct ino_bucket *next = __bucket(bucket->irq_chain);
 632
 633                 bucket->irq_chain = 0;
 634                 __do_IRQ(bucket->virt_irq);
 635
 636                 bucket = next;
 637         }
 638
 639         irq_exit();
 640         set_irq_regs(old_regs);
 641 }
 642
 643 struct sun5_timer {
 644         u64     count0;
 645         u64     limit0;
 646         u64     count1;
 647         u64     limit1;
 648 };
 649
 650 static struct sun5_timer *prom_timers;
 651 static u64 prom_limit0, prom_limit1;
 652
 653 static void map_prom_timers(void)
 654 {
 655         struct device_node *dp;
 656         unsigned int *addr;
 657
 658         /* PROM timer node hangs out in the top level of device siblings... */
 659         dp = of_find_node_by_path("/");
 660         dp = dp->child;
 661         while (dp) {
 662                 if (!strcmp(dp->name, "counter-timer"))
 663                         break;
 664                 dp = dp->sibling;
 665         }
 666
 667         /* Assume if node is not present, PROM uses different tick mechanism
 668          * which we should not care about.
 669          */
 670         if (!dp) {
 671                 prom_timers = (struct sun5_timer *) 0;
 672                 return;
 673         }
 674
 675         /* If PROM is really using this, it must be mapped by him. */
 676         addr = of_get_property(dp, "address", NULL);
 677         if (!addr) {
 678                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 679                 prom_timers = (struct sun5_timer *) 0;
 680                 return;
 681         }
 682         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 683 }
 684
 685 static void kill_prom_timer(void)
 686 {
 687         if (!prom_timers)
 688                 return;
 689
 690         /* Save them away for later. */
 691         prom_limit0 = prom_timers->limit0;
 692         prom_limit1 = prom_timers->limit1;
 693
 694         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 695          * We turn both off here just to be paranoid.
 696          */
 697         prom_timers->limit0 = 0;
 698         prom_timers->limit1 = 0;
 699
 700         /* Wheee, eat the interrupt packet too... */
 701         __asm__ __volatile__(
 702 "       mov     0x40, %%g2\n"
 703 "       ldxa    [%%g0] %0, %%g1\n"
 704 "       ldxa    [%%g2] %1, %%g1\n"
 705 "       stxa    %%g0, [%%g0] %0\n"
 706 "       membar  #Sync\n"
 707         : /* no outputs */
 708         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 709         : "g1", "g2");
 710 }
 711
 712 void init_irqwork_curcpu(void)
 713 {
 714         int cpu = hard_smp_processor_id();
 715
 716         trap_block[cpu].irq_worklist = 0;
 717 }
 718
 719 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
 720 {
 721         unsigned long num_entries = 128;
 722         unsigned long status;
 723
 724         status = sun4v_cpu_qconf(type, paddr, num_entries);
 725         if (status != HV_EOK) {
 726                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 727                             "err %lu\n", type, paddr, num_entries, status);
 728                 prom_halt();
 729         }
 730 }
 731
 732 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
 733 {
 734         struct trap_per_cpu *tb = &trap_block[this_cpu];
 735
 736         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 737         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 738         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 739         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 740 }
 741
 742 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
 743 {
 744         void *page;
 745
 746         if (use_bootmem)
 747                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 748         else
 749                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 750
 751         if (!page) {
 752                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 753                 prom_halt();
 754         }
 755
 756         *pa_ptr = __pa(page);
 757 }
 758
 759 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
 760 {
 761         void *page;
 762
 763         if (use_bootmem)
 764                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 765         else
 766                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 767
 768         if (!page) {
 769                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 770                 prom_halt();
 771         }
 772
 773         *pa_ptr = __pa(page);
 774 }
 775
 776 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
 777 {
 778 #ifdef CONFIG_SMP
 779         void *page;
 780
 781         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 782
 783         if (use_bootmem)
 784                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 785         else
 786                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 787
 788         if (!page) {
 789                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 790                 prom_halt();
 791         }
 792
 793         tb->cpu_mondo_block_pa = __pa(page);
 794         tb->cpu_list_pa = __pa(page + 64);
 795 #endif
 796 }
 797
 798 /* Allocate and register the mondo and error queues for this cpu.  */
 799 void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
 800 {
 801         struct trap_per_cpu *tb = &trap_block[cpu];
 802
 803         if (alloc) {
 804                 alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
 805                 alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
 806                 alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
 807                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
 808                 alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
 809                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
 810
 811                 init_cpu_send_mondo_info(tb, use_bootmem);
 812         }
 813
 814         if (load) {
 815                 if (cpu != hard_smp_processor_id()) {
 816                         prom_printf("SUN4V: init mondo on cpu %d not %d\n",
 817                                     cpu, hard_smp_processor_id());
 818                         prom_halt();
 819                 }
 820                 sun4v_register_mondo_queues(cpu);
 821         }
 822 }
 823
 824 static struct irqaction timer_irq_action = {
 825         .name = "timer",
 826 };
 827
 828 /* Only invoked on boot processor. */
 829 void __init init_IRQ(void)
 830 {
 831         map_prom_timers();
 832         kill_prom_timer();
 833         memset(&ivector_table[0], 0, sizeof(ivector_table));
 834
 835         if (tlb_type == hypervisor)
 836                 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
 837
 838         /* We need to clear any IRQ's pending in the soft interrupt
 839          * registers, a spurious one could be left around from the
 840          * PROM timer which we just disabled.
 841          */
 842         clear_softint(get_softint());
 843
 844         /* Now that ivector table is initialized, it is safe
 845          * to receive IRQ vector traps.  We will normally take
 846          * one or two right now, in case some device PROM used
 847          * to boot us wants to speak to us.  We just ignore them.
 848          */
 849         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
 850                              "or        %%g1, %0, %%g1\n\t"
 851                              "wrpr      %%g1, 0x0, %%pstate"
 852                              : /* No outputs */
 853                              : "i" (PSTATE_IE)
 854                              : "g1");
 855
 856         irq_desc[0].action = &timer_irq_action;
 857 }