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Linux 2.6.21
[linux/fpc-iii.git] / arch / sparc64 / mm / init.c
blobf146071a4b2a383934f24c5a590c2433d0e3ab09
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26
27 #include <asm/head.h>
28 #include <asm/system.h>
29 #include <asm/page.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
38 #include <asm/dma.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
43 #include <asm/tsb.h>
44 #include <asm/hypervisor.h>
45 #include <asm/prom.h>
46
47 extern void device_scan(void);
48
49 #define MAX_PHYS_ADDRESS (1UL << 42UL)
50 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
51 #define KPTE_BITMAP_BYTES \
52 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
53
54 unsigned long kern_linear_pte_xor[2] __read_mostly;
55
56 /* A bitmap, one bit for every 256MB of physical memory. If the bit
57 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
58 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59 */
60 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
61
62 #ifndef CONFIG_DEBUG_PAGEALLOC
63 /* A special kernel TSB for 4MB and 256MB linear mappings. */
64 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
65 #endif
66
67 #define MAX_BANKS 32
68
69 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
70 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
71 static int pavail_ents __initdata;
72 static int pavail_rescan_ents __initdata;
73
74 static int cmp_p64(const void *a, const void *b)
75 {
76 const struct linux_prom64_registers *x = a, *y = b;
77
78 if (x->phys_addr > y->phys_addr)
79 return 1;
80 if (x->phys_addr < y->phys_addr)
81 return -1;
82 return 0;
83 }
84
85 static void __init read_obp_memory(const char *property,
86 struct linux_prom64_registers *regs,
87 int *num_ents)
88 {
89 int node = prom_finddevice("/memory");
90 int prop_size = prom_getproplen(node, property);
91 int ents, ret, i;
92
93 ents = prop_size / sizeof(struct linux_prom64_registers);
94 if (ents > MAX_BANKS) {
95 prom_printf("The machine has more %s property entries than "
96 "this kernel can support (%d).\n",
97 property, MAX_BANKS);
98 prom_halt();
99 }
100
101 ret = prom_getproperty(node, property, (char *) regs, prop_size);
102 if (ret == -1) {
103 prom_printf("Couldn't get %s property from /memory.\n");
104 prom_halt();
105 }
106
107 /* Sanitize what we got from the firmware, by page aligning
108 * everything.
109 */
110 for (i = 0; i < ents; i++) {
111 unsigned long base, size;
112
113 base = regs[i].phys_addr;
114 size = regs[i].reg_size;
115
116 size &= PAGE_MASK;
117 if (base & ~PAGE_MASK) {
118 unsigned long new_base = PAGE_ALIGN(base);
119
120 size -= new_base - base;
121 if ((long) size < 0L)
122 size = 0UL;
123 base = new_base;
124 }
125 regs[i].phys_addr = base;
126 regs[i].reg_size = size;
127 }
128
129 for (i = 0; i < ents; i++) {
130 if (regs[i].reg_size == 0UL) {
131 int j;
132
133 for (j = i; j < ents - 1; j++) {
134 regs[j].phys_addr =
135 regs[j+1].phys_addr;
136 regs[j].reg_size =
137 regs[j+1].reg_size;
138 }
139
140 ents--;
141 i--;
142 }
143 }
144
145 *num_ents = ents;
146
147 sort(regs, ents, sizeof(struct linux_prom64_registers),
148 cmp_p64, NULL);
149 }
150
151 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
152
153 /* Kernel physical address base and size in bytes. */
154 unsigned long kern_base __read_mostly;
155 unsigned long kern_size __read_mostly;
156
157 /* get_new_mmu_context() uses "cache + 1". */
158 DEFINE_SPINLOCK(ctx_alloc_lock);
159 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
160 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
161 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
162
163 /* References to special section boundaries */
164 extern char _start[], _end[];
165
166 /* Initial ramdisk setup */
167 extern unsigned long sparc_ramdisk_image64;
168 extern unsigned int sparc_ramdisk_image;
169 extern unsigned int sparc_ramdisk_size;
170
171 struct page *mem_map_zero __read_mostly;
172
173 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
174
175 unsigned long sparc64_kern_pri_context __read_mostly;
176 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
177 unsigned long sparc64_kern_sec_context __read_mostly;
178
179 int bigkernel = 0;
180
181 struct kmem_cache *pgtable_cache __read_mostly;
182
183 static void zero_ctor(void *addr, struct kmem_cache *cache, unsigned long flags)
184 {
185 clear_page(addr);
186 }
187
188 extern void tsb_cache_init(void);
189
190 void pgtable_cache_init(void)
191 {
192 pgtable_cache = kmem_cache_create("pgtable_cache",
193 PAGE_SIZE, PAGE_SIZE,
194 SLAB_HWCACHE_ALIGN |
195 SLAB_MUST_HWCACHE_ALIGN,
196 zero_ctor,
197 NULL);
198 if (!pgtable_cache) {
199 prom_printf("Could not create pgtable_cache\n");
200 prom_halt();
201 }
202 tsb_cache_init();
203 }
204
205 #ifdef CONFIG_DEBUG_DCFLUSH
206 atomic_t dcpage_flushes = ATOMIC_INIT(0);
207 #ifdef CONFIG_SMP
208 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
209 #endif
210 #endif
211
212 inline void flush_dcache_page_impl(struct page *page)
213 {
214 BUG_ON(tlb_type == hypervisor);
215 #ifdef CONFIG_DEBUG_DCFLUSH
216 atomic_inc(&dcpage_flushes);
217 #endif
218
219 #ifdef DCACHE_ALIASING_POSSIBLE
220 __flush_dcache_page(page_address(page),
221 ((tlb_type == spitfire) &&
222 page_mapping(page) != NULL));
223 #else
224 if (page_mapping(page) != NULL &&
225 tlb_type == spitfire)
226 __flush_icache_page(__pa(page_address(page)));
227 #endif
228 }
229
230 #define PG_dcache_dirty PG_arch_1
231 #define PG_dcache_cpu_shift 24UL
232 #define PG_dcache_cpu_mask (256UL - 1UL)
233
234 #if NR_CPUS > 256
235 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
236 #endif
237
238 #define dcache_dirty_cpu(page) \
239 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
240
241 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
242 {
243 unsigned long mask = this_cpu;
244 unsigned long non_cpu_bits;
245
246 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
247 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
248
249 __asm__ __volatile__("1:\n\t"
250 "ldx [%2], %%g7\n\t"
251 "and %%g7, %1, %%g1\n\t"
252 "or %%g1, %0, %%g1\n\t"
253 "casx [%2], %%g7, %%g1\n\t"
254 "cmp %%g7, %%g1\n\t"
255 "membar #StoreLoad | #StoreStore\n\t"
256 "bne,pn %%xcc, 1b\n\t"
257 " nop"
258 : /* no outputs */
259 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
260 : "g1", "g7");
261 }
262
263 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
264 {
265 unsigned long mask = (1UL << PG_dcache_dirty);
266
267 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
268 "1:\n\t"
269 "ldx [%2], %%g7\n\t"
270 "srlx %%g7, %4, %%g1\n\t"
271 "and %%g1, %3, %%g1\n\t"
272 "cmp %%g1, %0\n\t"
273 "bne,pn %%icc, 2f\n\t"
274 " andn %%g7, %1, %%g1\n\t"
275 "casx [%2], %%g7, %%g1\n\t"
276 "cmp %%g7, %%g1\n\t"
277 "membar #StoreLoad | #StoreStore\n\t"
278 "bne,pn %%xcc, 1b\n\t"
279 " nop\n"
280 "2:"
281 : /* no outputs */
282 : "r" (cpu), "r" (mask), "r" (&page->flags),
283 "i" (PG_dcache_cpu_mask),
284 "i" (PG_dcache_cpu_shift)
285 : "g1", "g7");
286 }
287
288 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
289 {
290 unsigned long tsb_addr = (unsigned long) ent;
291
292 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
293 tsb_addr = __pa(tsb_addr);
294
295 __tsb_insert(tsb_addr, tag, pte);
296 }
297
298 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
299 unsigned long _PAGE_SZBITS __read_mostly;
300
301 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
302 {
303 struct mm_struct *mm;
304 struct tsb *tsb;
305 unsigned long tag, flags;
306 unsigned long tsb_index, tsb_hash_shift;
307
308 if (tlb_type != hypervisor) {
309 unsigned long pfn = pte_pfn(pte);
310 unsigned long pg_flags;
311 struct page *page;
312
313 if (pfn_valid(pfn) &&
314 (page = pfn_to_page(pfn), page_mapping(page)) &&
315 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
316 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
317 PG_dcache_cpu_mask);
318 int this_cpu = get_cpu();
319
320 /* This is just to optimize away some function calls
321 * in the SMP case.
322 */
323 if (cpu == this_cpu)
324 flush_dcache_page_impl(page);
325 else
326 smp_flush_dcache_page_impl(page, cpu);
327
328 clear_dcache_dirty_cpu(page, cpu);
329
330 put_cpu();
331 }
332 }
333
334 mm = vma->vm_mm;
335
336 tsb_index = MM_TSB_BASE;
337 tsb_hash_shift = PAGE_SHIFT;
338
339 spin_lock_irqsave(&mm->context.lock, flags);
340
341 #ifdef CONFIG_HUGETLB_PAGE
342 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
343 if ((tlb_type == hypervisor &&
344 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
345 (tlb_type != hypervisor &&
346 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
347 tsb_index = MM_TSB_HUGE;
348 tsb_hash_shift = HPAGE_SHIFT;
349 }
350 }
351 #endif
352
353 tsb = mm->context.tsb_block[tsb_index].tsb;
354 tsb += ((address >> tsb_hash_shift) &
355 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
356 tag = (address >> 22UL);
357 tsb_insert(tsb, tag, pte_val(pte));
358
359 spin_unlock_irqrestore(&mm->context.lock, flags);
360 }
361
362 void flush_dcache_page(struct page *page)
363 {
364 struct address_space *mapping;
365 int this_cpu;
366
367 if (tlb_type == hypervisor)
368 return;
369
370 /* Do not bother with the expensive D-cache flush if it
371 * is merely the zero page. The 'bigcore' testcase in GDB
372 * causes this case to run millions of times.
373 */
374 if (page == ZERO_PAGE(0))
375 return;
376
377 this_cpu = get_cpu();
378
379 mapping = page_mapping(page);
380 if (mapping && !mapping_mapped(mapping)) {
381 int dirty = test_bit(PG_dcache_dirty, &page->flags);
382 if (dirty) {
383 int dirty_cpu = dcache_dirty_cpu(page);
384
385 if (dirty_cpu == this_cpu)
386 goto out;
387 smp_flush_dcache_page_impl(page, dirty_cpu);
388 }
389 set_dcache_dirty(page, this_cpu);
390 } else {
391 /* We could delay the flush for the !page_mapping
392 * case too. But that case is for exec env/arg
393 * pages and those are %99 certainly going to get
394 * faulted into the tlb (and thus flushed) anyways.
395 */
396 flush_dcache_page_impl(page);
397 }
398
399 out:
400 put_cpu();
401 }
402
403 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
404 {
405 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
406 if (tlb_type == spitfire) {
407 unsigned long kaddr;
408
409 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
410 __flush_icache_page(__get_phys(kaddr));
411 }
412 }
413
414 void show_mem(void)
415 {
416 printk("Mem-info:\n");
417 show_free_areas();
418 printk("Free swap: %6ldkB\n",
419 nr_swap_pages << (PAGE_SHIFT-10));
420 printk("%ld pages of RAM\n", num_physpages);
421 printk("%lu free pages\n", nr_free_pages());
422 }
423
424 void mmu_info(struct seq_file *m)
425 {
426 if (tlb_type == cheetah)
427 seq_printf(m, "MMU Type\t: Cheetah\n");
428 else if (tlb_type == cheetah_plus)
429 seq_printf(m, "MMU Type\t: Cheetah+\n");
430 else if (tlb_type == spitfire)
431 seq_printf(m, "MMU Type\t: Spitfire\n");
432 else if (tlb_type == hypervisor)
433 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
434 else
435 seq_printf(m, "MMU Type\t: ???\n");
436
437 #ifdef CONFIG_DEBUG_DCFLUSH
438 seq_printf(m, "DCPageFlushes\t: %d\n",
439 atomic_read(&dcpage_flushes));
440 #ifdef CONFIG_SMP
441 seq_printf(m, "DCPageFlushesXC\t: %d\n",
442 atomic_read(&dcpage_flushes_xcall));
443 #endif /* CONFIG_SMP */
444 #endif /* CONFIG_DEBUG_DCFLUSH */
445 }
446
447 struct linux_prom_translation {
448 unsigned long virt;
449 unsigned long size;
450 unsigned long data;
451 };
452
453 /* Exported for kernel TLB miss handling in ktlb.S */
454 struct linux_prom_translation prom_trans[512] __read_mostly;
455 unsigned int prom_trans_ents __read_mostly;
456
457 /* Exported for SMP bootup purposes. */
458 unsigned long kern_locked_tte_data;
459
460 /* The obp translations are saved based on 8k pagesize, since obp can
461 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
462 * HI_OBP_ADDRESS range are handled in ktlb.S.
463 */
464 static inline int in_obp_range(unsigned long vaddr)
465 {
466 return (vaddr >= LOW_OBP_ADDRESS &&
467 vaddr < HI_OBP_ADDRESS);
468 }
469
470 static int cmp_ptrans(const void *a, const void *b)
471 {
472 const struct linux_prom_translation *x = a, *y = b;
473
474 if (x->virt > y->virt)
475 return 1;
476 if (x->virt < y->virt)
477 return -1;
478 return 0;
479 }
480
481 /* Read OBP translations property into 'prom_trans[]'. */
482 static void __init read_obp_translations(void)
483 {
484 int n, node, ents, first, last, i;
485
486 node = prom_finddevice("/virtual-memory");
487 n = prom_getproplen(node, "translations");
488 if (unlikely(n == 0 || n == -1)) {
489 prom_printf("prom_mappings: Couldn't get size.\n");
490 prom_halt();
491 }
492 if (unlikely(n > sizeof(prom_trans))) {
493 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
494 prom_halt();
495 }
496
497 if ((n = prom_getproperty(node, "translations",
498 (char *)&prom_trans[0],
499 sizeof(prom_trans))) == -1) {
500 prom_printf("prom_mappings: Couldn't get property.\n");
501 prom_halt();
502 }
503
504 n = n / sizeof(struct linux_prom_translation);
505
506 ents = n;
507
508 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
509 cmp_ptrans, NULL);
510
511 /* Now kick out all the non-OBP entries. */
512 for (i = 0; i < ents; i++) {
513 if (in_obp_range(prom_trans[i].virt))
514 break;
515 }
516 first = i;
517 for (; i < ents; i++) {
518 if (!in_obp_range(prom_trans[i].virt))
519 break;
520 }
521 last = i;
522
523 for (i = 0; i < (last - first); i++) {
524 struct linux_prom_translation *src = &prom_trans[i + first];
525 struct linux_prom_translation *dest = &prom_trans[i];
526
527 *dest = *src;
528 }
529 for (; i < ents; i++) {
530 struct linux_prom_translation *dest = &prom_trans[i];
531 dest->virt = dest->size = dest->data = 0x0UL;
532 }
533
534 prom_trans_ents = last - first;
535
536 if (tlb_type == spitfire) {
537 /* Clear diag TTE bits. */
538 for (i = 0; i < prom_trans_ents; i++)
539 prom_trans[i].data &= ~0x0003fe0000000000UL;
540 }
541 }
542
543 static void __init hypervisor_tlb_lock(unsigned long vaddr,
544 unsigned long pte,
545 unsigned long mmu)
546 {
547 register unsigned long func asm("%o5");
548 register unsigned long arg0 asm("%o0");
549 register unsigned long arg1 asm("%o1");
550 register unsigned long arg2 asm("%o2");
551 register unsigned long arg3 asm("%o3");
552
553 func = HV_FAST_MMU_MAP_PERM_ADDR;
554 arg0 = vaddr;
555 arg1 = 0;
556 arg2 = pte;
557 arg3 = mmu;
558 __asm__ __volatile__("ta 0x80"
559 : "=&r" (func), "=&r" (arg0),
560 "=&r" (arg1), "=&r" (arg2),
561 "=&r" (arg3)
562 : "0" (func), "1" (arg0), "2" (arg1),
563 "3" (arg2), "4" (arg3));
564 if (arg0 != 0) {
565 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
566 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
567 prom_halt();
568 }
569 }
570
571 static unsigned long kern_large_tte(unsigned long paddr);
572
573 static void __init remap_kernel(void)
574 {
575 unsigned long phys_page, tte_vaddr, tte_data;
576 int tlb_ent = sparc64_highest_locked_tlbent();
577
578 tte_vaddr = (unsigned long) KERNBASE;
579 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
580 tte_data = kern_large_tte(phys_page);
581
582 kern_locked_tte_data = tte_data;
583
584 /* Now lock us into the TLBs via Hypervisor or OBP. */
585 if (tlb_type == hypervisor) {
586 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
587 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
588 if (bigkernel) {
589 tte_vaddr += 0x400000;
590 tte_data += 0x400000;
591 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
592 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
593 }
594 } else {
595 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
596 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
597 if (bigkernel) {
598 tlb_ent -= 1;
599 prom_dtlb_load(tlb_ent,
600 tte_data + 0x400000,
601 tte_vaddr + 0x400000);
602 prom_itlb_load(tlb_ent,
603 tte_data + 0x400000,
604 tte_vaddr + 0x400000);
605 }
606 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
607 }
608 if (tlb_type == cheetah_plus) {
609 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
610 CTX_CHEETAH_PLUS_NUC);
611 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
612 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
613 }
614 }
615
616
617 static void __init inherit_prom_mappings(void)
618 {
619 read_obp_translations();
620
621 /* Now fixup OBP's idea about where we really are mapped. */
622 prom_printf("Remapping the kernel... ");
623 remap_kernel();
624 prom_printf("done.\n");
625 }
626
627 void prom_world(int enter)
628 {
629 if (!enter)
630 set_fs((mm_segment_t) { get_thread_current_ds() });
631
632 __asm__ __volatile__("flushw");
633 }
634
635 #ifdef DCACHE_ALIASING_POSSIBLE
636 void __flush_dcache_range(unsigned long start, unsigned long end)
637 {
638 unsigned long va;
639
640 if (tlb_type == spitfire) {
641 int n = 0;
642
643 for (va = start; va < end; va += 32) {
644 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
645 if (++n >= 512)
646 break;
647 }
648 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
649 start = __pa(start);
650 end = __pa(end);
651 for (va = start; va < end; va += 32)
652 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
653 "membar #Sync"
654 : /* no outputs */
655 : "r" (va),
656 "i" (ASI_DCACHE_INVALIDATE));
657 }
658 }
659 #endif /* DCACHE_ALIASING_POSSIBLE */
660
661 /* Caller does TLB context flushing on local CPU if necessary.
662 * The caller also ensures that CTX_VALID(mm->context) is false.
663 *
664 * We must be careful about boundary cases so that we never
665 * let the user have CTX 0 (nucleus) or we ever use a CTX
666 * version of zero (and thus NO_CONTEXT would not be caught
667 * by version mis-match tests in mmu_context.h).
668 *
669 * Always invoked with interrupts disabled.
670 */
671 void get_new_mmu_context(struct mm_struct *mm)
672 {
673 unsigned long ctx, new_ctx;
674 unsigned long orig_pgsz_bits;
675 unsigned long flags;
676 int new_version;
677
678 spin_lock_irqsave(&ctx_alloc_lock, flags);
679 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
680 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
681 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
682 new_version = 0;
683 if (new_ctx >= (1 << CTX_NR_BITS)) {
684 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
685 if (new_ctx >= ctx) {
686 int i;
687 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
688 CTX_FIRST_VERSION;
689 if (new_ctx == 1)
690 new_ctx = CTX_FIRST_VERSION;
691
692 /* Don't call memset, for 16 entries that's just
693 * plain silly...
694 */
695 mmu_context_bmap[0] = 3;
696 mmu_context_bmap[1] = 0;
697 mmu_context_bmap[2] = 0;
698 mmu_context_bmap[3] = 0;
699 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
700 mmu_context_bmap[i + 0] = 0;
701 mmu_context_bmap[i + 1] = 0;
702 mmu_context_bmap[i + 2] = 0;
703 mmu_context_bmap[i + 3] = 0;
704 }
705 new_version = 1;
706 goto out;
707 }
708 }
709 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
710 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
711 out:
712 tlb_context_cache = new_ctx;
713 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
714 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
715
716 if (unlikely(new_version))
717 smp_new_mmu_context_version();
718 }
719
720 void sparc_ultra_dump_itlb(void)
721 {
722 int slot;
723
724 if (tlb_type == spitfire) {
725 printk ("Contents of itlb: ");
726 for (slot = 0; slot < 14; slot++) printk (" ");
727 printk ("%2x:%016lx,%016lx\n",
728 0,
729 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
730 for (slot = 1; slot < 64; slot+=3) {
731 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
732 slot,
733 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
734 slot+1,
735 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
736 slot+2,
737 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
738 }
739 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
740 printk ("Contents of itlb0:\n");
741 for (slot = 0; slot < 16; slot+=2) {
742 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
743 slot,
744 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
745 slot+1,
746 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
747 }
748 printk ("Contents of itlb2:\n");
749 for (slot = 0; slot < 128; slot+=2) {
750 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
751 slot,
752 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
753 slot+1,
754 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
755 }
756 }
757 }
758
759 void sparc_ultra_dump_dtlb(void)
760 {
761 int slot;
762
763 if (tlb_type == spitfire) {
764 printk ("Contents of dtlb: ");
765 for (slot = 0; slot < 14; slot++) printk (" ");
766 printk ("%2x:%016lx,%016lx\n", 0,
767 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
768 for (slot = 1; slot < 64; slot+=3) {
769 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
770 slot,
771 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
772 slot+1,
773 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
774 slot+2,
775 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
776 }
777 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
778 printk ("Contents of dtlb0:\n");
779 for (slot = 0; slot < 16; slot+=2) {
780 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
781 slot,
782 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
783 slot+1,
784 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
785 }
786 printk ("Contents of dtlb2:\n");
787 for (slot = 0; slot < 512; slot+=2) {
788 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
789 slot,
790 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
791 slot+1,
792 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
793 }
794 if (tlb_type == cheetah_plus) {
795 printk ("Contents of dtlb3:\n");
796 for (slot = 0; slot < 512; slot+=2) {
797 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
798 slot,
799 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
800 slot+1,
801 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
802 }
803 }
804 }
805 }
806
807 extern unsigned long cmdline_memory_size;
808
809 /* Find a free area for the bootmem map, avoiding the kernel image
810 * and the initial ramdisk.
811 */
812 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
813 unsigned long end_pfn)
814 {
815 unsigned long avoid_start, avoid_end, bootmap_size;
816 int i;
817
818 bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
819 bootmap_size = ALIGN(bootmap_size, sizeof(long));
820
821 avoid_start = avoid_end = 0;
822 #ifdef CONFIG_BLK_DEV_INITRD
823 avoid_start = initrd_start;
824 avoid_end = PAGE_ALIGN(initrd_end);
825 #endif
826
827 #ifdef CONFIG_DEBUG_BOOTMEM
828 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
829 kern_base, PAGE_ALIGN(kern_base + kern_size),
830 avoid_start, avoid_end);
831 #endif
832 for (i = 0; i < pavail_ents; i++) {
833 unsigned long start, end;
834
835 start = pavail[i].phys_addr;
836 end = start + pavail[i].reg_size;
837
838 while (start < end) {
839 if (start >= kern_base &&
840 start < PAGE_ALIGN(kern_base + kern_size)) {
841 start = PAGE_ALIGN(kern_base + kern_size);
842 continue;
843 }
844 if (start >= avoid_start && start < avoid_end) {
845 start = avoid_end;
846 continue;
847 }
848
849 if ((end - start) < bootmap_size)
850 break;
851
852 if (start < kern_base &&
853 (start + bootmap_size) > kern_base) {
854 start = PAGE_ALIGN(kern_base + kern_size);
855 continue;
856 }
857
858 if (start < avoid_start &&
859 (start + bootmap_size) > avoid_start) {
860 start = avoid_end;
861 continue;
862 }
863
864 /* OK, it doesn't overlap anything, use it. */
865 #ifdef CONFIG_DEBUG_BOOTMEM
866 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
867 start >> PAGE_SHIFT, start);
868 #endif
869 return start >> PAGE_SHIFT;
870 }
871 }
872
873 prom_printf("Cannot find free area for bootmap, aborting.\n");
874 prom_halt();
875 }
876
877 static void __init trim_pavail(unsigned long *cur_size_p,
878 unsigned long *end_of_phys_p)
879 {
880 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
881 unsigned long avoid_start, avoid_end;
882 int i;
883
884 to_trim = PAGE_ALIGN(to_trim);
885
886 avoid_start = avoid_end = 0;
887 #ifdef CONFIG_BLK_DEV_INITRD
888 avoid_start = initrd_start;
889 avoid_end = PAGE_ALIGN(initrd_end);
890 #endif
891
892 /* Trim some pavail[] entries in order to satisfy the
893 * requested "mem=xxx" kernel command line specification.
894 *
895 * We must not trim off the kernel image area nor the
896 * initial ramdisk range (if any). Also, we must not trim
897 * any pavail[] entry down to zero in order to preserve
898 * the invariant that all pavail[] entries have a non-zero
899 * size which is assumed by all of the code in here.
900 */
901 for (i = 0; i < pavail_ents; i++) {
902 unsigned long start, end, kern_end;
903 unsigned long trim_low, trim_high, n;
904
905 kern_end = PAGE_ALIGN(kern_base + kern_size);
906
907 trim_low = start = pavail[i].phys_addr;
908 trim_high = end = start + pavail[i].reg_size;
909
910 if (kern_base >= start &&
911 kern_base < end) {
912 trim_low = kern_base;
913 if (kern_end >= end)
914 continue;
915 }
916 if (kern_end >= start &&
917 kern_end < end) {
918 trim_high = kern_end;
919 }
920 if (avoid_start &&
921 avoid_start >= start &&
922 avoid_start < end) {
923 if (trim_low > avoid_start)
924 trim_low = avoid_start;
925 if (avoid_end >= end)
926 continue;
927 }
928 if (avoid_end &&
929 avoid_end >= start &&
930 avoid_end < end) {
931 if (trim_high < avoid_end)
932 trim_high = avoid_end;
933 }
934
935 if (trim_high <= trim_low)
936 continue;
937
938 if (trim_low == start && trim_high == end) {
939 /* Whole chunk is available for trimming.
940 * Trim all except one page, in order to keep
941 * entry non-empty.
942 */
943 n = (end - start) - PAGE_SIZE;
944 if (n > to_trim)
945 n = to_trim;
946
947 if (n) {
948 pavail[i].phys_addr += n;
949 pavail[i].reg_size -= n;
950 to_trim -= n;
951 }
952 } else {
953 n = (trim_low - start);
954 if (n > to_trim)
955 n = to_trim;
956
957 if (n) {
958 pavail[i].phys_addr += n;
959 pavail[i].reg_size -= n;
960 to_trim -= n;
961 }
962 if (to_trim) {
963 n = end - trim_high;
964 if (n > to_trim)
965 n = to_trim;
966 if (n) {
967 pavail[i].reg_size -= n;
968 to_trim -= n;
969 }
970 }
971 }
972
973 if (!to_trim)
974 break;
975 }
976
977 /* Recalculate. */
978 *cur_size_p = 0UL;
979 for (i = 0; i < pavail_ents; i++) {
980 *end_of_phys_p = pavail[i].phys_addr +
981 pavail[i].reg_size;
982 *cur_size_p += pavail[i].reg_size;
983 }
984 }
985
986 static unsigned long __init bootmem_init(unsigned long *pages_avail,
987 unsigned long phys_base)
988 {
989 unsigned long bootmap_size, end_pfn;
990 unsigned long end_of_phys_memory = 0UL;
991 unsigned long bootmap_pfn, bytes_avail, size;
992 int i;
993
994 #ifdef CONFIG_DEBUG_BOOTMEM
995 prom_printf("bootmem_init: Scan pavail, ");
996 #endif
997
998 bytes_avail = 0UL;
999 for (i = 0; i < pavail_ents; i++) {
1000 end_of_phys_memory = pavail[i].phys_addr +
1001 pavail[i].reg_size;
1002 bytes_avail += pavail[i].reg_size;
1003 }
1004
1005 /* Determine the location of the initial ramdisk before trying
1006 * to honor the "mem=xxx" command line argument. We must know
1007 * where the kernel image and the ramdisk image are so that we
1008 * do not trim those two areas from the physical memory map.
1009 */
1010
1011 #ifdef CONFIG_BLK_DEV_INITRD
1012 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1013 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1014 unsigned long ramdisk_image = sparc_ramdisk_image ?
1015 sparc_ramdisk_image : sparc_ramdisk_image64;
1016 ramdisk_image -= KERNBASE;
1017 initrd_start = ramdisk_image + phys_base;
1018 initrd_end = initrd_start + sparc_ramdisk_size;
1019 if (initrd_end > end_of_phys_memory) {
1020 printk(KERN_CRIT "initrd extends beyond end of memory "
1021 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1022 initrd_end, end_of_phys_memory);
1023 initrd_start = 0;
1024 initrd_end = 0;
1025 }
1026 }
1027 #endif
1028
1029 if (cmdline_memory_size &&
1030 bytes_avail > cmdline_memory_size)
1031 trim_pavail(&bytes_avail,
1032 &end_of_phys_memory);
1033
1034 *pages_avail = bytes_avail >> PAGE_SHIFT;
1035
1036 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1037
1038 /* Initialize the boot-time allocator. */
1039 max_pfn = max_low_pfn = end_pfn;
1040 min_low_pfn = (phys_base >> PAGE_SHIFT);
1041
1042 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1043
1044 #ifdef CONFIG_DEBUG_BOOTMEM
1045 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1046 min_low_pfn, bootmap_pfn, max_low_pfn);
1047 #endif
1048 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
1049 min_low_pfn, end_pfn);
1050
1051 /* Now register the available physical memory with the
1052 * allocator.
1053 */
1054 for (i = 0; i < pavail_ents; i++) {
1055 #ifdef CONFIG_DEBUG_BOOTMEM
1056 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1057 i, pavail[i].phys_addr, pavail[i].reg_size);
1058 #endif
1059 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1060 }
1061
1062 #ifdef CONFIG_BLK_DEV_INITRD
1063 if (initrd_start) {
1064 size = initrd_end - initrd_start;
1065
1066 /* Resert the initrd image area. */
1067 #ifdef CONFIG_DEBUG_BOOTMEM
1068 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1069 initrd_start, initrd_end);
1070 #endif
1071 reserve_bootmem(initrd_start, size);
1072 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1073
1074 initrd_start += PAGE_OFFSET;
1075 initrd_end += PAGE_OFFSET;
1076 }
1077 #endif
1078 /* Reserve the kernel text/data/bss. */
1079 #ifdef CONFIG_DEBUG_BOOTMEM
1080 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1081 #endif
1082 reserve_bootmem(kern_base, kern_size);
1083 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1084
1085 /* Reserve the bootmem map. We do not account for it
1086 * in pages_avail because we will release that memory
1087 * in free_all_bootmem.
1088 */
1089 size = bootmap_size;
1090 #ifdef CONFIG_DEBUG_BOOTMEM
1091 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1092 (bootmap_pfn << PAGE_SHIFT), size);
1093 #endif
1094 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1095 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1096
1097 for (i = 0; i < pavail_ents; i++) {
1098 unsigned long start_pfn, end_pfn;
1099
1100 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1101 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1102 #ifdef CONFIG_DEBUG_BOOTMEM
1103 prom_printf("memory_present(0, %lx, %lx)\n",
1104 start_pfn, end_pfn);
1105 #endif
1106 memory_present(0, start_pfn, end_pfn);
1107 }
1108
1109 sparse_init();
1110
1111 return end_pfn;
1112 }
1113
1114 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1115 static int pall_ents __initdata;
1116
1117 #ifdef CONFIG_DEBUG_PAGEALLOC
1118 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1119 {
1120 unsigned long vstart = PAGE_OFFSET + pstart;
1121 unsigned long vend = PAGE_OFFSET + pend;
1122 unsigned long alloc_bytes = 0UL;
1123
1124 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1125 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1126 vstart, vend);
1127 prom_halt();
1128 }
1129
1130 while (vstart < vend) {
1131 unsigned long this_end, paddr = __pa(vstart);
1132 pgd_t *pgd = pgd_offset_k(vstart);
1133 pud_t *pud;
1134 pmd_t *pmd;
1135 pte_t *pte;
1136
1137 pud = pud_offset(pgd, vstart);
1138 if (pud_none(*pud)) {
1139 pmd_t *new;
1140
1141 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1142 alloc_bytes += PAGE_SIZE;
1143 pud_populate(&init_mm, pud, new);
1144 }
1145
1146 pmd = pmd_offset(pud, vstart);
1147 if (!pmd_present(*pmd)) {
1148 pte_t *new;
1149
1150 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1151 alloc_bytes += PAGE_SIZE;
1152 pmd_populate_kernel(&init_mm, pmd, new);
1153 }
1154
1155 pte = pte_offset_kernel(pmd, vstart);
1156 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1157 if (this_end > vend)
1158 this_end = vend;
1159
1160 while (vstart < this_end) {
1161 pte_val(*pte) = (paddr | pgprot_val(prot));
1162
1163 vstart += PAGE_SIZE;
1164 paddr += PAGE_SIZE;
1165 pte++;
1166 }
1167 }
1168
1169 return alloc_bytes;
1170 }
1171
1172 extern unsigned int kvmap_linear_patch[1];
1173 #endif /* CONFIG_DEBUG_PAGEALLOC */
1174
1175 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1176 {
1177 const unsigned long shift_256MB = 28;
1178 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1179 const unsigned long size_256MB = (1UL << shift_256MB);
1180
1181 while (start < end) {
1182 long remains;
1183
1184 remains = end - start;
1185 if (remains < size_256MB)
1186 break;
1187
1188 if (start & mask_256MB) {
1189 start = (start + size_256MB) & ~mask_256MB;
1190 continue;
1191 }
1192
1193 while (remains >= size_256MB) {
1194 unsigned long index = start >> shift_256MB;
1195
1196 __set_bit(index, kpte_linear_bitmap);
1197
1198 start += size_256MB;
1199 remains -= size_256MB;
1200 }
1201 }
1202 }
1203
1204 static void __init kernel_physical_mapping_init(void)
1205 {
1206 unsigned long i;
1207 #ifdef CONFIG_DEBUG_PAGEALLOC
1208 unsigned long mem_alloced = 0UL;
1209 #endif
1210
1211 read_obp_memory("reg", &pall[0], &pall_ents);
1212
1213 for (i = 0; i < pall_ents; i++) {
1214 unsigned long phys_start, phys_end;
1215
1216 phys_start = pall[i].phys_addr;
1217 phys_end = phys_start + pall[i].reg_size;
1218
1219 mark_kpte_bitmap(phys_start, phys_end);
1220
1221 #ifdef CONFIG_DEBUG_PAGEALLOC
1222 mem_alloced += kernel_map_range(phys_start, phys_end,
1223 PAGE_KERNEL);
1224 #endif
1225 }
1226
1227 #ifdef CONFIG_DEBUG_PAGEALLOC
1228 printk("Allocated %ld bytes for kernel page tables.\n",
1229 mem_alloced);
1230
1231 kvmap_linear_patch[0] = 0x01000000; /* nop */
1232 flushi(&kvmap_linear_patch[0]);
1233
1234 __flush_tlb_all();
1235 #endif
1236 }
1237
1238 #ifdef CONFIG_DEBUG_PAGEALLOC
1239 void kernel_map_pages(struct page *page, int numpages, int enable)
1240 {
1241 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1242 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1243
1244 kernel_map_range(phys_start, phys_end,
1245 (enable ? PAGE_KERNEL : __pgprot(0)));
1246
1247 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1248 PAGE_OFFSET + phys_end);
1249
1250 /* we should perform an IPI and flush all tlbs,
1251 * but that can deadlock->flush only current cpu.
1252 */
1253 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1254 PAGE_OFFSET + phys_end);
1255 }
1256 #endif
1257
1258 unsigned long __init find_ecache_flush_span(unsigned long size)
1259 {
1260 int i;
1261
1262 for (i = 0; i < pavail_ents; i++) {
1263 if (pavail[i].reg_size >= size)
1264 return pavail[i].phys_addr;
1265 }
1266
1267 return ~0UL;
1268 }
1269
1270 static void __init tsb_phys_patch(void)
1271 {
1272 struct tsb_ldquad_phys_patch_entry *pquad;
1273 struct tsb_phys_patch_entry *p;
1274
1275 pquad = &__tsb_ldquad_phys_patch;
1276 while (pquad < &__tsb_ldquad_phys_patch_end) {
1277 unsigned long addr = pquad->addr;
1278
1279 if (tlb_type == hypervisor)
1280 *(unsigned int *) addr = pquad->sun4v_insn;
1281 else
1282 *(unsigned int *) addr = pquad->sun4u_insn;
1283 wmb();
1284 __asm__ __volatile__("flush %0"
1285 : /* no outputs */
1286 : "r" (addr));
1287
1288 pquad++;
1289 }
1290
1291 p = &__tsb_phys_patch;
1292 while (p < &__tsb_phys_patch_end) {
1293 unsigned long addr = p->addr;
1294
1295 *(unsigned int *) addr = p->insn;
1296 wmb();
1297 __asm__ __volatile__("flush %0"
1298 : /* no outputs */
1299 : "r" (addr));
1300
1301 p++;
1302 }
1303 }
1304
1305 /* Don't mark as init, we give this to the Hypervisor. */
1306 #ifndef CONFIG_DEBUG_PAGEALLOC
1307 #define NUM_KTSB_DESCR 2
1308 #else
1309 #define NUM_KTSB_DESCR 1
1310 #endif
1311 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1312 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1313
1314 static void __init sun4v_ktsb_init(void)
1315 {
1316 unsigned long ktsb_pa;
1317
1318 /* First KTSB for PAGE_SIZE mappings. */
1319 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1320
1321 switch (PAGE_SIZE) {
1322 case 8 * 1024:
1323 default:
1324 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1325 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1326 break;
1327
1328 case 64 * 1024:
1329 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1330 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1331 break;
1332
1333 case 512 * 1024:
1334 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1335 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1336 break;
1337
1338 case 4 * 1024 * 1024:
1339 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1340 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1341 break;
1342 };
1343
1344 ktsb_descr[0].assoc = 1;
1345 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1346 ktsb_descr[0].ctx_idx = 0;
1347 ktsb_descr[0].tsb_base = ktsb_pa;
1348 ktsb_descr[0].resv = 0;
1349
1350 #ifndef CONFIG_DEBUG_PAGEALLOC
1351 /* Second KTSB for 4MB/256MB mappings. */
1352 ktsb_pa = (kern_base +
1353 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1354
1355 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1356 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1357 HV_PGSZ_MASK_256MB);
1358 ktsb_descr[1].assoc = 1;
1359 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1360 ktsb_descr[1].ctx_idx = 0;
1361 ktsb_descr[1].tsb_base = ktsb_pa;
1362 ktsb_descr[1].resv = 0;
1363 #endif
1364 }
1365
1366 void __cpuinit sun4v_ktsb_register(void)
1367 {
1368 register unsigned long func asm("%o5");
1369 register unsigned long arg0 asm("%o0");
1370 register unsigned long arg1 asm("%o1");
1371 unsigned long pa;
1372
1373 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1374
1375 func = HV_FAST_MMU_TSB_CTX0;
1376 arg0 = NUM_KTSB_DESCR;
1377 arg1 = pa;
1378 __asm__ __volatile__("ta %6"
1379 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1380 : "0" (func), "1" (arg0), "2" (arg1),
1381 "i" (HV_FAST_TRAP));
1382 }
1383
1384 /* paging_init() sets up the page tables */
1385
1386 extern void cheetah_ecache_flush_init(void);
1387 extern void sun4v_patch_tlb_handlers(void);
1388
1389 static unsigned long last_valid_pfn;
1390 pgd_t swapper_pg_dir[2048];
1391
1392 static void sun4u_pgprot_init(void);
1393 static void sun4v_pgprot_init(void);
1394
1395 void __init paging_init(void)
1396 {
1397 unsigned long end_pfn, pages_avail, shift, phys_base;
1398 unsigned long real_end, i;
1399
1400 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1401 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1402
1403 /* Invalidate both kernel TSBs. */
1404 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1405 #ifndef CONFIG_DEBUG_PAGEALLOC
1406 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1407 #endif
1408
1409 if (tlb_type == hypervisor)
1410 sun4v_pgprot_init();
1411 else
1412 sun4u_pgprot_init();
1413
1414 if (tlb_type == cheetah_plus ||
1415 tlb_type == hypervisor)
1416 tsb_phys_patch();
1417
1418 if (tlb_type == hypervisor) {
1419 sun4v_patch_tlb_handlers();
1420 sun4v_ktsb_init();
1421 }
1422
1423 /* Find available physical memory... */
1424 read_obp_memory("available", &pavail[0], &pavail_ents);
1425
1426 phys_base = 0xffffffffffffffffUL;
1427 for (i = 0; i < pavail_ents; i++)
1428 phys_base = min(phys_base, pavail[i].phys_addr);
1429
1430 set_bit(0, mmu_context_bmap);
1431
1432 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1433
1434 real_end = (unsigned long)_end;
1435 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1436 bigkernel = 1;
1437 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1438 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1439 prom_halt();
1440 }
1441
1442 /* Set kernel pgd to upper alias so physical page computations
1443 * work.
1444 */
1445 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1446
1447 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1448
1449 /* Now can init the kernel/bad page tables. */
1450 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1451 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1452
1453 inherit_prom_mappings();
1454
1455 /* Ok, we can use our TLB miss and window trap handlers safely. */
1456 setup_tba();
1457
1458 __flush_tlb_all();
1459
1460 if (tlb_type == hypervisor)
1461 sun4v_ktsb_register();
1462
1463 /* Setup bootmem... */
1464 pages_avail = 0;
1465 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1466
1467 max_mapnr = last_valid_pfn;
1468
1469 kernel_physical_mapping_init();
1470
1471 prom_build_devicetree();
1472
1473 {
1474 unsigned long zones_size[MAX_NR_ZONES];
1475 unsigned long zholes_size[MAX_NR_ZONES];
1476 int znum;
1477
1478 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1479 zones_size[znum] = zholes_size[znum] = 0;
1480
1481 zones_size[ZONE_NORMAL] = end_pfn;
1482 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1483
1484 free_area_init_node(0, &contig_page_data, zones_size,
1485 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1486 zholes_size);
1487 }
1488
1489 device_scan();
1490 }
1491
1492 static void __init taint_real_pages(void)
1493 {
1494 int i;
1495
1496 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1497
1498 /* Find changes discovered in the physmem available rescan and
1499 * reserve the lost portions in the bootmem maps.
1500 */
1501 for (i = 0; i < pavail_ents; i++) {
1502 unsigned long old_start, old_end;
1503
1504 old_start = pavail[i].phys_addr;
1505 old_end = old_start +
1506 pavail[i].reg_size;
1507 while (old_start < old_end) {
1508 int n;
1509
1510 for (n = 0; n < pavail_rescan_ents; n++) {
1511 unsigned long new_start, new_end;
1512
1513 new_start = pavail_rescan[n].phys_addr;
1514 new_end = new_start +
1515 pavail_rescan[n].reg_size;
1516
1517 if (new_start <= old_start &&
1518 new_end >= (old_start + PAGE_SIZE)) {
1519 set_bit(old_start >> 22,
1520 sparc64_valid_addr_bitmap);
1521 goto do_next_page;
1522 }
1523 }
1524 reserve_bootmem(old_start, PAGE_SIZE);
1525
1526 do_next_page:
1527 old_start += PAGE_SIZE;
1528 }
1529 }
1530 }
1531
1532 int __init page_in_phys_avail(unsigned long paddr)
1533 {
1534 int i;
1535
1536 paddr &= PAGE_MASK;
1537
1538 for (i = 0; i < pavail_rescan_ents; i++) {
1539 unsigned long start, end;
1540
1541 start = pavail_rescan[i].phys_addr;
1542 end = start + pavail_rescan[i].reg_size;
1543
1544 if (paddr >= start && paddr < end)
1545 return 1;
1546 }
1547 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1548 return 1;
1549 #ifdef CONFIG_BLK_DEV_INITRD
1550 if (paddr >= __pa(initrd_start) &&
1551 paddr < __pa(PAGE_ALIGN(initrd_end)))
1552 return 1;
1553 #endif
1554
1555 return 0;
1556 }
1557
1558 void __init mem_init(void)
1559 {
1560 unsigned long codepages, datapages, initpages;
1561 unsigned long addr, last;
1562 int i;
1563
1564 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1565 i += 1;
1566 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1567 if (sparc64_valid_addr_bitmap == NULL) {
1568 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1569 prom_halt();
1570 }
1571 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1572
1573 addr = PAGE_OFFSET + kern_base;
1574 last = PAGE_ALIGN(kern_size) + addr;
1575 while (addr < last) {
1576 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1577 addr += PAGE_SIZE;
1578 }
1579
1580 taint_real_pages();
1581
1582 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1583
1584 #ifdef CONFIG_DEBUG_BOOTMEM
1585 prom_printf("mem_init: Calling free_all_bootmem().\n");
1586 #endif
1587 totalram_pages = num_physpages = free_all_bootmem() - 1;
1588
1589 /*
1590 * Set up the zero page, mark it reserved, so that page count
1591 * is not manipulated when freeing the page from user ptes.
1592 */
1593 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1594 if (mem_map_zero == NULL) {
1595 prom_printf("paging_init: Cannot alloc zero page.\n");
1596 prom_halt();
1597 }
1598 SetPageReserved(mem_map_zero);
1599
1600 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1601 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1602 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1603 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1604 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1605 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1606
1607 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1608 nr_free_pages() << (PAGE_SHIFT-10),
1609 codepages << (PAGE_SHIFT-10),
1610 datapages << (PAGE_SHIFT-10),
1611 initpages << (PAGE_SHIFT-10),
1612 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1613
1614 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1615 cheetah_ecache_flush_init();
1616 }
1617
1618 void free_initmem(void)
1619 {
1620 unsigned long addr, initend;
1621
1622 /*
1623 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1624 */
1625 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1626 initend = (unsigned long)(__init_end) & PAGE_MASK;
1627 for (; addr < initend; addr += PAGE_SIZE) {
1628 unsigned long page;
1629 struct page *p;
1630
1631 page = (addr +
1632 ((unsigned long) __va(kern_base)) -
1633 ((unsigned long) KERNBASE));
1634 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1635 p = virt_to_page(page);
1636
1637 ClearPageReserved(p);
1638 init_page_count(p);
1639 __free_page(p);
1640 num_physpages++;
1641 totalram_pages++;
1642 }
1643 }
1644
1645 #ifdef CONFIG_BLK_DEV_INITRD
1646 void free_initrd_mem(unsigned long start, unsigned long end)
1647 {
1648 if (start < end)
1649 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1650 for (; start < end; start += PAGE_SIZE) {
1651 struct page *p = virt_to_page(start);
1652
1653 ClearPageReserved(p);
1654 init_page_count(p);
1655 __free_page(p);
1656 num_physpages++;
1657 totalram_pages++;
1658 }
1659 }
1660 #endif
1661
1662 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1663 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1664 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1665 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1666 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1667 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1668
1669 pgprot_t PAGE_KERNEL __read_mostly;
1670 EXPORT_SYMBOL(PAGE_KERNEL);
1671
1672 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1673 pgprot_t PAGE_COPY __read_mostly;
1674
1675 pgprot_t PAGE_SHARED __read_mostly;
1676 EXPORT_SYMBOL(PAGE_SHARED);
1677
1678 pgprot_t PAGE_EXEC __read_mostly;
1679 unsigned long pg_iobits __read_mostly;
1680
1681 unsigned long _PAGE_IE __read_mostly;
1682 EXPORT_SYMBOL(_PAGE_IE);
1683
1684 unsigned long _PAGE_E __read_mostly;
1685 EXPORT_SYMBOL(_PAGE_E);
1686
1687 unsigned long _PAGE_CACHE __read_mostly;
1688 EXPORT_SYMBOL(_PAGE_CACHE);
1689
1690 static void prot_init_common(unsigned long page_none,
1691 unsigned long page_shared,
1692 unsigned long page_copy,
1693 unsigned long page_readonly,
1694 unsigned long page_exec_bit)
1695 {
1696 PAGE_COPY = __pgprot(page_copy);
1697 PAGE_SHARED = __pgprot(page_shared);
1698
1699 protection_map[0x0] = __pgprot(page_none);
1700 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1701 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1702 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1703 protection_map[0x4] = __pgprot(page_readonly);
1704 protection_map[0x5] = __pgprot(page_readonly);
1705 protection_map[0x6] = __pgprot(page_copy);
1706 protection_map[0x7] = __pgprot(page_copy);
1707 protection_map[0x8] = __pgprot(page_none);
1708 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1709 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1710 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1711 protection_map[0xc] = __pgprot(page_readonly);
1712 protection_map[0xd] = __pgprot(page_readonly);
1713 protection_map[0xe] = __pgprot(page_shared);
1714 protection_map[0xf] = __pgprot(page_shared);
1715 }
1716
1717 static void __init sun4u_pgprot_init(void)
1718 {
1719 unsigned long page_none, page_shared, page_copy, page_readonly;
1720 unsigned long page_exec_bit;
1721
1722 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1723 _PAGE_CACHE_4U | _PAGE_P_4U |
1724 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1725 _PAGE_EXEC_4U);
1726 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1727 _PAGE_CACHE_4U | _PAGE_P_4U |
1728 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1729 _PAGE_EXEC_4U | _PAGE_L_4U);
1730 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1731
1732 _PAGE_IE = _PAGE_IE_4U;
1733 _PAGE_E = _PAGE_E_4U;
1734 _PAGE_CACHE = _PAGE_CACHE_4U;
1735
1736 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1737 __ACCESS_BITS_4U | _PAGE_E_4U);
1738
1739 #ifdef CONFIG_DEBUG_PAGEALLOC
1740 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1741 0xfffff80000000000;
1742 #else
1743 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1744 0xfffff80000000000;
1745 #endif
1746 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1747 _PAGE_P_4U | _PAGE_W_4U);
1748
1749 /* XXX Should use 256MB on Panther. XXX */
1750 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1751
1752 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1753 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1754 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1755 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1756
1757
1758 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1759 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1760 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1761 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1762 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1763 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1764 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1765
1766 page_exec_bit = _PAGE_EXEC_4U;
1767
1768 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1769 page_exec_bit);
1770 }
1771
1772 static void __init sun4v_pgprot_init(void)
1773 {
1774 unsigned long page_none, page_shared, page_copy, page_readonly;
1775 unsigned long page_exec_bit;
1776
1777 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1778 _PAGE_CACHE_4V | _PAGE_P_4V |
1779 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1780 _PAGE_EXEC_4V);
1781 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1782 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1783
1784 _PAGE_IE = _PAGE_IE_4V;
1785 _PAGE_E = _PAGE_E_4V;
1786 _PAGE_CACHE = _PAGE_CACHE_4V;
1787
1788 #ifdef CONFIG_DEBUG_PAGEALLOC
1789 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1790 0xfffff80000000000;
1791 #else
1792 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1793 0xfffff80000000000;
1794 #endif
1795 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1796 _PAGE_P_4V | _PAGE_W_4V);
1797
1798 #ifdef CONFIG_DEBUG_PAGEALLOC
1799 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1800 0xfffff80000000000;
1801 #else
1802 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1803 0xfffff80000000000;
1804 #endif
1805 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1806 _PAGE_P_4V | _PAGE_W_4V);
1807
1808 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1809 __ACCESS_BITS_4V | _PAGE_E_4V);
1810
1811 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1812 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1813 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1814 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1815 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1816
1817 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1818 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1819 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1820 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1821 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1822 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1823 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1824
1825 page_exec_bit = _PAGE_EXEC_4V;
1826
1827 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1828 page_exec_bit);
1829 }
1830
1831 unsigned long pte_sz_bits(unsigned long sz)
1832 {
1833 if (tlb_type == hypervisor) {
1834 switch (sz) {
1835 case 8 * 1024:
1836 default:
1837 return _PAGE_SZ8K_4V;
1838 case 64 * 1024:
1839 return _PAGE_SZ64K_4V;
1840 case 512 * 1024:
1841 return _PAGE_SZ512K_4V;
1842 case 4 * 1024 * 1024:
1843 return _PAGE_SZ4MB_4V;
1844 };
1845 } else {
1846 switch (sz) {
1847 case 8 * 1024:
1848 default:
1849 return _PAGE_SZ8K_4U;
1850 case 64 * 1024:
1851 return _PAGE_SZ64K_4U;
1852 case 512 * 1024:
1853 return _PAGE_SZ512K_4U;
1854 case 4 * 1024 * 1024:
1855 return _PAGE_SZ4MB_4U;
1856 };
1857 }
1858 }
1859
1860 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1861 {
1862 pte_t pte;
1863
1864 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1865 pte_val(pte) |= (((unsigned long)space) << 32);
1866 pte_val(pte) |= pte_sz_bits(page_size);
1867
1868 return pte;
1869 }
1870
1871 static unsigned long kern_large_tte(unsigned long paddr)
1872 {
1873 unsigned long val;
1874
1875 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1876 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1877 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1878 if (tlb_type == hypervisor)
1879 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1880 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1881 _PAGE_EXEC_4V | _PAGE_W_4V);
1882
1883 return val | paddr;
1884 }
1885
1886 /*
1887 * Translate PROM's mapping we capture at boot time into physical address.
1888 * The second parameter is only set from prom_callback() invocations.
1889 */
1890 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1891 {
1892 unsigned long mask;
1893 int i;
1894
1895 mask = _PAGE_PADDR_4U;
1896 if (tlb_type == hypervisor)
1897 mask = _PAGE_PADDR_4V;
1898
1899 for (i = 0; i < prom_trans_ents; i++) {
1900 struct linux_prom_translation *p = &prom_trans[i];
1901
1902 if (promva >= p->virt &&
1903 promva < (p->virt + p->size)) {
1904 unsigned long base = p->data & mask;
1905
1906 if (error)
1907 *error = 0;
1908 return base + (promva & (8192 - 1));
1909 }
1910 }
1911 if (error)
1912 *error = 1;
1913 return 0UL;
1914 }
1915
1916 /* XXX We should kill off this ugly thing at so me point. XXX */
1917 unsigned long sun4u_get_pte(unsigned long addr)
1918 {
1919 pgd_t *pgdp;
1920 pud_t *pudp;
1921 pmd_t *pmdp;
1922 pte_t *ptep;
1923 unsigned long mask = _PAGE_PADDR_4U;
1924
1925 if (tlb_type == hypervisor)
1926 mask = _PAGE_PADDR_4V;
1927
1928 if (addr >= PAGE_OFFSET)
1929 return addr & mask;
1930
1931 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1932 return prom_virt_to_phys(addr, NULL);
1933
1934 pgdp = pgd_offset_k(addr);
1935 pudp = pud_offset(pgdp, addr);
1936 pmdp = pmd_offset(pudp, addr);
1937 ptep = pte_offset_kernel(pmdp, addr);
1938
1939 return pte_val(*ptep) & mask;
1940 }
1941
1942 /* If not locked, zap it. */
1943 void __flush_tlb_all(void)
1944 {
1945 unsigned long pstate;
1946 int i;
1947
1948 __asm__ __volatile__("flushw\n\t"
1949 "rdpr %%pstate, %0\n\t"
1950 "wrpr %0, %1, %%pstate"
1951 : "=r" (pstate)
1952 : "i" (PSTATE_IE));
1953 if (tlb_type == spitfire) {
1954 for (i = 0; i < 64; i++) {
1955 /* Spitfire Errata #32 workaround */
1956 /* NOTE: Always runs on spitfire, so no
1957 * cheetah+ page size encodings.
1958 */
1959 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1960 "flush %%g6"
1961 : /* No outputs */
1962 : "r" (0),
1963 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1964
1965 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1966 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1967 "membar #Sync"
1968 : /* no outputs */
1969 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1970 spitfire_put_dtlb_data(i, 0x0UL);
1971 }
1972
1973 /* Spitfire Errata #32 workaround */
1974 /* NOTE: Always runs on spitfire, so no
1975 * cheetah+ page size encodings.
1976 */
1977 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1978 "flush %%g6"
1979 : /* No outputs */
1980 : "r" (0),
1981 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1982
1983 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1984 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1985 "membar #Sync"
1986 : /* no outputs */
1987 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1988 spitfire_put_itlb_data(i, 0x0UL);
1989 }
1990 }
1991 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1992 cheetah_flush_dtlb_all();
1993 cheetah_flush_itlb_all();
1994 }
1995 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1996 : : "r" (pstate));
1997 }
1998
1999 #ifdef CONFIG_MEMORY_HOTPLUG
2000
2001 void online_page(struct page *page)
2002 {
2003 ClearPageReserved(page);
2004 init_page_count(page);
2005 __free_page(page);
2006 totalram_pages++;
2007 num_physpages++;
2008 }
2009
2010 int remove_memory(u64 start, u64 size)
2011 {
2012 return -EINVAL;
2013 }
2014
2015 #endif /* CONFIG_MEMORY_HOTPLUG */
Linux with added FPC-III support