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Linux 2.6.21
[linux/fpc-iii.git] / drivers / ata / sata_qstor.c
blob8786b45f291b8d62af9ddb6fd3bc585d7c659201
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/device.h>
38 #include <scsi/scsi_host.h>
39 #include <linux/libata.h>
40
41 #define DRV_NAME "sata_qstor"
42 #define DRV_VERSION "0.07"
43
44 enum {
45 QS_MMIO_BAR = 4,
46
47 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100 };
101
102 enum {
103 QS_DMA_BOUNDARY = ~0UL
104 };
105
106 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
107
108 struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112 };
113
114 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
115 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
117 static irqreturn_t qs_intr (int irq, void *dev_instance);
118 static int qs_port_start(struct ata_port *ap);
119 static void qs_host_stop(struct ata_host *host);
120 static void qs_phy_reset(struct ata_port *ap);
121 static void qs_qc_prep(struct ata_queued_cmd *qc);
122 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
123 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
124 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
125 static u8 qs_bmdma_status(struct ata_port *ap);
126 static void qs_irq_clear(struct ata_port *ap);
127 static void qs_eng_timeout(struct ata_port *ap);
128
129 static struct scsi_host_template qs_ata_sht = {
130 .module = THIS_MODULE,
131 .name = DRV_NAME,
132 .ioctl = ata_scsi_ioctl,
133 .queuecommand = ata_scsi_queuecmd,
134 .can_queue = ATA_DEF_QUEUE,
135 .this_id = ATA_SHT_THIS_ID,
136 .sg_tablesize = QS_MAX_PRD,
137 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
138 .emulated = ATA_SHT_EMULATED,
139 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
140 .use_clustering = ENABLE_CLUSTERING,
141 .proc_name = DRV_NAME,
142 .dma_boundary = QS_DMA_BOUNDARY,
143 .slave_configure = ata_scsi_slave_config,
144 .slave_destroy = ata_scsi_slave_destroy,
145 .bios_param = ata_std_bios_param,
146 };
147
148 static const struct ata_port_operations qs_ata_ops = {
149 .port_disable = ata_port_disable,
150 .tf_load = ata_tf_load,
151 .tf_read = ata_tf_read,
152 .check_status = ata_check_status,
153 .check_atapi_dma = qs_check_atapi_dma,
154 .exec_command = ata_exec_command,
155 .dev_select = ata_std_dev_select,
156 .phy_reset = qs_phy_reset,
157 .qc_prep = qs_qc_prep,
158 .qc_issue = qs_qc_issue,
159 .data_xfer = ata_data_xfer,
160 .eng_timeout = qs_eng_timeout,
161 .irq_handler = qs_intr,
162 .irq_clear = qs_irq_clear,
163 .irq_on = ata_irq_on,
164 .irq_ack = ata_irq_ack,
165 .scr_read = qs_scr_read,
166 .scr_write = qs_scr_write,
167 .port_start = qs_port_start,
168 .host_stop = qs_host_stop,
169 .bmdma_stop = qs_bmdma_stop,
170 .bmdma_status = qs_bmdma_status,
171 };
172
173 static const struct ata_port_info qs_port_info[] = {
174 /* board_2068_idx */
175 {
176 .sht = &qs_ata_sht,
177 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
178 ATA_FLAG_SATA_RESET |
179 //FIXME ATA_FLAG_SRST |
180 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
181 .pio_mask = 0x10, /* pio4 */
182 .udma_mask = 0x7f, /* udma0-6 */
183 .port_ops = &qs_ata_ops,
184 },
185 };
186
187 static const struct pci_device_id qs_ata_pci_tbl[] = {
188 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
189
190 { } /* terminate list */
191 };
192
193 static struct pci_driver qs_ata_pci_driver = {
194 .name = DRV_NAME,
195 .id_table = qs_ata_pci_tbl,
196 .probe = qs_ata_init_one,
197 .remove = ata_pci_remove_one,
198 };
199
200 static void __iomem *qs_mmio_base(struct ata_host *host)
201 {
202 return host->iomap[QS_MMIO_BAR];
203 }
204
205 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
206 {
207 return 1; /* ATAPI DMA not supported */
208 }
209
210 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
211 {
212 /* nothing */
213 }
214
215 static u8 qs_bmdma_status(struct ata_port *ap)
216 {
217 return 0;
218 }
219
220 static void qs_irq_clear(struct ata_port *ap)
221 {
222 /* nothing */
223 }
224
225 static inline void qs_enter_reg_mode(struct ata_port *ap)
226 {
227 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
228
229 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
230 readb(chan + QS_CCT_CTR0); /* flush */
231 }
232
233 static inline void qs_reset_channel_logic(struct ata_port *ap)
234 {
235 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
236
237 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
238 readb(chan + QS_CCT_CTR0); /* flush */
239 qs_enter_reg_mode(ap);
240 }
241
242 static void qs_phy_reset(struct ata_port *ap)
243 {
244 struct qs_port_priv *pp = ap->private_data;
245
246 pp->state = qs_state_idle;
247 qs_reset_channel_logic(ap);
248 sata_phy_reset(ap);
249 }
250
251 static void qs_eng_timeout(struct ata_port *ap)
252 {
253 struct qs_port_priv *pp = ap->private_data;
254
255 if (pp->state != qs_state_idle) /* healthy paranoia */
256 pp->state = qs_state_mmio;
257 qs_reset_channel_logic(ap);
258 ata_eng_timeout(ap);
259 }
260
261 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
262 {
263 if (sc_reg > SCR_CONTROL)
264 return ~0U;
265 return readl(ap->ioaddr.scr_addr + (sc_reg * 8));
266 }
267
268 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
269 {
270 if (sc_reg > SCR_CONTROL)
271 return;
272 writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
273 }
274
275 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
276 {
277 struct scatterlist *sg;
278 struct ata_port *ap = qc->ap;
279 struct qs_port_priv *pp = ap->private_data;
280 unsigned int nelem;
281 u8 *prd = pp->pkt + QS_CPB_BYTES;
282
283 WARN_ON(qc->__sg == NULL);
284 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
285
286 nelem = 0;
287 ata_for_each_sg(sg, qc) {
288 u64 addr;
289 u32 len;
290
291 addr = sg_dma_address(sg);
292 *(__le64 *)prd = cpu_to_le64(addr);
293 prd += sizeof(u64);
294
295 len = sg_dma_len(sg);
296 *(__le32 *)prd = cpu_to_le32(len);
297 prd += sizeof(u64);
298
299 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
300 (unsigned long long)addr, len);
301 nelem++;
302 }
303
304 return nelem;
305 }
306
307 static void qs_qc_prep(struct ata_queued_cmd *qc)
308 {
309 struct qs_port_priv *pp = qc->ap->private_data;
310 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
311 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
312 u64 addr;
313 unsigned int nelem;
314
315 VPRINTK("ENTER\n");
316
317 qs_enter_reg_mode(qc->ap);
318 if (qc->tf.protocol != ATA_PROT_DMA) {
319 ata_qc_prep(qc);
320 return;
321 }
322
323 nelem = qs_fill_sg(qc);
324
325 if ((qc->tf.flags & ATA_TFLAG_WRITE))
326 hflags |= QS_HF_DIRO;
327 if ((qc->tf.flags & ATA_TFLAG_LBA48))
328 dflags |= QS_DF_ELBA;
329
330 /* host control block (HCB) */
331 buf[ 0] = QS_HCB_HDR;
332 buf[ 1] = hflags;
333 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
334 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
335 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
336 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
337
338 /* device control block (DCB) */
339 buf[24] = QS_DCB_HDR;
340 buf[28] = dflags;
341
342 /* frame information structure (FIS) */
343 ata_tf_to_fis(&qc->tf, &buf[32], 0);
344 }
345
346 static inline void qs_packet_start(struct ata_queued_cmd *qc)
347 {
348 struct ata_port *ap = qc->ap;
349 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
350
351 VPRINTK("ENTER, ap %p\n", ap);
352
353 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
354 wmb(); /* flush PRDs and pkt to memory */
355 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
356 readl(chan + QS_CCT_CFF); /* flush */
357 }
358
359 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
360 {
361 struct qs_port_priv *pp = qc->ap->private_data;
362
363 switch (qc->tf.protocol) {
364 case ATA_PROT_DMA:
365
366 pp->state = qs_state_pkt;
367 qs_packet_start(qc);
368 return 0;
369
370 case ATA_PROT_ATAPI_DMA:
371 BUG();
372 break;
373
374 default:
375 break;
376 }
377
378 pp->state = qs_state_mmio;
379 return ata_qc_issue_prot(qc);
380 }
381
382 static inline unsigned int qs_intr_pkt(struct ata_host *host)
383 {
384 unsigned int handled = 0;
385 u8 sFFE;
386 u8 __iomem *mmio_base = qs_mmio_base(host);
387
388 do {
389 u32 sff0 = readl(mmio_base + QS_HST_SFF);
390 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
391 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
392 sFFE = sff1 >> 31; /* empty flag */
393
394 if (sEVLD) {
395 u8 sDST = sff0 >> 16; /* dev status */
396 u8 sHST = sff1 & 0x3f; /* host status */
397 unsigned int port_no = (sff1 >> 8) & 0x03;
398 struct ata_port *ap = host->ports[port_no];
399
400 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
401 sff1, sff0, port_no, sHST, sDST);
402 handled = 1;
403 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
404 struct ata_queued_cmd *qc;
405 struct qs_port_priv *pp = ap->private_data;
406 if (!pp || pp->state != qs_state_pkt)
407 continue;
408 qc = ata_qc_from_tag(ap, ap->active_tag);
409 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
410 switch (sHST) {
411 case 0: /* successful CPB */
412 case 3: /* device error */
413 pp->state = qs_state_idle;
414 qs_enter_reg_mode(qc->ap);
415 qc->err_mask |= ac_err_mask(sDST);
416 ata_qc_complete(qc);
417 break;
418 default:
419 break;
420 }
421 }
422 }
423 }
424 } while (!sFFE);
425 return handled;
426 }
427
428 static inline unsigned int qs_intr_mmio(struct ata_host *host)
429 {
430 unsigned int handled = 0, port_no;
431
432 for (port_no = 0; port_no < host->n_ports; ++port_no) {
433 struct ata_port *ap;
434 ap = host->ports[port_no];
435 if (ap &&
436 !(ap->flags & ATA_FLAG_DISABLED)) {
437 struct ata_queued_cmd *qc;
438 struct qs_port_priv *pp = ap->private_data;
439 if (!pp || pp->state != qs_state_mmio)
440 continue;
441 qc = ata_qc_from_tag(ap, ap->active_tag);
442 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
443
444 /* check main status, clearing INTRQ */
445 u8 status = ata_check_status(ap);
446 if ((status & ATA_BUSY))
447 continue;
448 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
449 ap->print_id, qc->tf.protocol, status);
450
451 /* complete taskfile transaction */
452 pp->state = qs_state_idle;
453 qc->err_mask |= ac_err_mask(status);
454 ata_qc_complete(qc);
455 handled = 1;
456 }
457 }
458 }
459 return handled;
460 }
461
462 static irqreturn_t qs_intr(int irq, void *dev_instance)
463 {
464 struct ata_host *host = dev_instance;
465 unsigned int handled = 0;
466
467 VPRINTK("ENTER\n");
468
469 spin_lock(&host->lock);
470 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
471 spin_unlock(&host->lock);
472
473 VPRINTK("EXIT\n");
474
475 return IRQ_RETVAL(handled);
476 }
477
478 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
479 {
480 port->cmd_addr =
481 port->data_addr = base + 0x400;
482 port->error_addr =
483 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
484 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
485 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
486 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
487 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
488 port->device_addr = base + 0x430;
489 port->status_addr =
490 port->command_addr = base + 0x438;
491 port->altstatus_addr =
492 port->ctl_addr = base + 0x440;
493 port->scr_addr = base + 0xc00;
494 }
495
496 static int qs_port_start(struct ata_port *ap)
497 {
498 struct device *dev = ap->host->dev;
499 struct qs_port_priv *pp;
500 void __iomem *mmio_base = qs_mmio_base(ap->host);
501 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
502 u64 addr;
503 int rc;
504
505 rc = ata_port_start(ap);
506 if (rc)
507 return rc;
508 qs_enter_reg_mode(ap);
509 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
510 if (!pp)
511 return -ENOMEM;
512 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
513 GFP_KERNEL);
514 if (!pp->pkt)
515 return -ENOMEM;
516 memset(pp->pkt, 0, QS_PKT_BYTES);
517 ap->private_data = pp;
518
519 addr = (u64)pp->pkt_dma;
520 writel((u32) addr, chan + QS_CCF_CPBA);
521 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
522 return 0;
523 }
524
525 static void qs_host_stop(struct ata_host *host)
526 {
527 void __iomem *mmio_base = qs_mmio_base(host);
528
529 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
530 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
531 }
532
533 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
534 {
535 void __iomem *mmio_base = pe->iomap[QS_MMIO_BAR];
536 unsigned int port_no;
537
538 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
539 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
540
541 /* reset each channel in turn */
542 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
543 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
544 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
545 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
546 readb(chan + QS_CCT_CTR0); /* flush */
547 }
548 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
549
550 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
551 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
552 /* set FIFO depths to same settings as Windows driver */
553 writew(32, chan + QS_CFC_HUFT);
554 writew(32, chan + QS_CFC_HDFT);
555 writew(10, chan + QS_CFC_DUFT);
556 writew( 8, chan + QS_CFC_DDFT);
557 /* set CPB size in bytes, as a power of two */
558 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
559 }
560 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
561 }
562
563 /*
564 * The QStor understands 64-bit buses, and uses 64-bit fields
565 * for DMA pointers regardless of bus width. We just have to
566 * make sure our DMA masks are set appropriately for whatever
567 * bridge lies between us and the QStor, and then the DMA mapping
568 * code will ensure we only ever "see" appropriate buffer addresses.
569 * If we're 32-bit limited somewhere, then our 64-bit fields will
570 * just end up with zeros in the upper 32-bits, without any special
571 * logic required outside of this routine (below).
572 */
573 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
574 {
575 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
576 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
577
578 if (have_64bit_bus &&
579 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
580 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
581 if (rc) {
582 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
583 if (rc) {
584 dev_printk(KERN_ERR, &pdev->dev,
585 "64-bit DMA enable failed\n");
586 return rc;
587 }
588 }
589 } else {
590 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
591 if (rc) {
592 dev_printk(KERN_ERR, &pdev->dev,
593 "32-bit DMA enable failed\n");
594 return rc;
595 }
596 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
597 if (rc) {
598 dev_printk(KERN_ERR, &pdev->dev,
599 "32-bit consistent DMA enable failed\n");
600 return rc;
601 }
602 }
603 return 0;
604 }
605
606 static int qs_ata_init_one(struct pci_dev *pdev,
607 const struct pci_device_id *ent)
608 {
609 static int printed_version;
610 struct ata_probe_ent *probe_ent;
611 void __iomem * const *iomap;
612 unsigned int board_idx = (unsigned int) ent->driver_data;
613 int rc, port_no;
614
615 if (!printed_version++)
616 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
617
618 rc = pcim_enable_device(pdev);
619 if (rc)
620 return rc;
621
622 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
623 return -ENODEV;
624
625 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
626 if (rc)
627 return rc;
628 iomap = pcim_iomap_table(pdev);
629
630 rc = qs_set_dma_masks(pdev, iomap[QS_MMIO_BAR]);
631 if (rc)
632 return rc;
633
634 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
635 if (probe_ent == NULL)
636 return -ENOMEM;
637
638 probe_ent->dev = pci_dev_to_dev(pdev);
639 INIT_LIST_HEAD(&probe_ent->node);
640
641 probe_ent->sht = qs_port_info[board_idx].sht;
642 probe_ent->port_flags = qs_port_info[board_idx].flags;
643 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
644 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
645 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
646 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
647
648 probe_ent->irq = pdev->irq;
649 probe_ent->irq_flags = IRQF_SHARED;
650 probe_ent->iomap = iomap;
651 probe_ent->n_ports = QS_PORTS;
652
653 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
654 void __iomem *chan =
655 probe_ent->iomap[QS_MMIO_BAR] + (port_no * 0x4000);
656 qs_ata_setup_port(&probe_ent->port[port_no], chan);
657 }
658
659 pci_set_master(pdev);
660
661 /* initialize adapter */
662 qs_host_init(board_idx, probe_ent);
663
664 if (ata_device_add(probe_ent) != QS_PORTS)
665 return -EIO;
666
667 devm_kfree(&pdev->dev, probe_ent);
668 return 0;
669 }
670
671 static int __init qs_ata_init(void)
672 {
673 return pci_register_driver(&qs_ata_pci_driver);
674 }
675
676 static void __exit qs_ata_exit(void)
677 {
678 pci_unregister_driver(&qs_ata_pci_driver);
679 }
680
681 MODULE_AUTHOR("Mark Lord");
682 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
683 MODULE_LICENSE("GPL");
684 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
685 MODULE_VERSION(DRV_VERSION);
686
687 module_init(qs_ata_init);
688 module_exit(qs_ata_exit);
Linux with added FPC-III support