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Linux 2.6.21
[linux/fpc-iii.git] / drivers / ata / sata_sis.c
bloba787f0d4a5baeea3d9da9f2c63dd025e9f078d92
1 /*
2 * sata_sis.c - Silicon Integrated Systems SATA
3 *
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 Uwe Koziolek
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
43 #include "sis.h"
44
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "0.7"
47
48 enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
51
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
59
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
64 };
65
66 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
67 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
68 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
69
70 static const struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */
76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */
77
78 { } /* terminate list */
79 };
80
81 static struct pci_driver sis_pci_driver = {
82 .name = DRV_NAME,
83 .id_table = sis_pci_tbl,
84 .probe = sis_init_one,
85 .remove = ata_pci_remove_one,
86 };
87
88 static struct scsi_host_template sis_sht = {
89 .module = THIS_MODULE,
90 .name = DRV_NAME,
91 .ioctl = ata_scsi_ioctl,
92 .queuecommand = ata_scsi_queuecmd,
93 .can_queue = ATA_DEF_QUEUE,
94 .this_id = ATA_SHT_THIS_ID,
95 .sg_tablesize = ATA_MAX_PRD,
96 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
97 .emulated = ATA_SHT_EMULATED,
98 .use_clustering = ATA_SHT_USE_CLUSTERING,
99 .proc_name = DRV_NAME,
100 .dma_boundary = ATA_DMA_BOUNDARY,
101 .slave_configure = ata_scsi_slave_config,
102 .slave_destroy = ata_scsi_slave_destroy,
103 .bios_param = ata_std_bios_param,
104 };
105
106 static const struct ata_port_operations sis_ops = {
107 .port_disable = ata_port_disable,
108 .tf_load = ata_tf_load,
109 .tf_read = ata_tf_read,
110 .check_status = ata_check_status,
111 .exec_command = ata_exec_command,
112 .dev_select = ata_std_dev_select,
113 .bmdma_setup = ata_bmdma_setup,
114 .bmdma_start = ata_bmdma_start,
115 .bmdma_stop = ata_bmdma_stop,
116 .bmdma_status = ata_bmdma_status,
117 .qc_prep = ata_qc_prep,
118 .qc_issue = ata_qc_issue_prot,
119 .data_xfer = ata_data_xfer,
120 .freeze = ata_bmdma_freeze,
121 .thaw = ata_bmdma_thaw,
122 .error_handler = ata_bmdma_error_handler,
123 .post_internal_cmd = ata_bmdma_post_internal_cmd,
124 .irq_handler = ata_interrupt,
125 .irq_clear = ata_bmdma_irq_clear,
126 .irq_on = ata_irq_on,
127 .irq_ack = ata_irq_ack,
128 .scr_read = sis_scr_read,
129 .scr_write = sis_scr_write,
130 .port_start = ata_port_start,
131 };
132
133 static struct ata_port_info sis_port_info = {
134 .sht = &sis_sht,
135 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
136 .pio_mask = 0x1f,
137 .mwdma_mask = 0x7,
138 .udma_mask = 0x7f,
139 .port_ops = &sis_ops,
140 };
141
142 MODULE_AUTHOR("Uwe Koziolek");
143 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
144 MODULE_LICENSE("GPL");
145 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
146 MODULE_VERSION(DRV_VERSION);
147
148 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
149 {
150 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
151 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
152 u8 pmr;
153
154 if (ap->port_no) {
155 switch (pdev->device) {
156 case 0x0180:
157 case 0x0181:
158 pci_read_config_byte(pdev, SIS_PMR, &pmr);
159 if ((pmr & SIS_PMR_COMBINED) == 0)
160 addr += SIS180_SATA1_OFS;
161 break;
162
163 case 0x0182:
164 case 0x0183:
165 case 0x1182:
166 case 0x1183:
167 addr += SIS182_SATA1_OFS;
168 break;
169 }
170 }
171 return addr;
172 }
173
174 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
175 {
176 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
177 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
178 u32 val, val2 = 0;
179 u8 pmr;
180
181 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
182 return 0xffffffff;
183
184 pci_read_config_byte(pdev, SIS_PMR, &pmr);
185
186 pci_read_config_dword(pdev, cfg_addr, &val);
187
188 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
189 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
190 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
191
192 return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
193 }
194
195 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
196 {
197 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
198 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
199 u8 pmr;
200
201 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
202 return;
203
204 pci_read_config_byte(pdev, SIS_PMR, &pmr);
205
206 pci_write_config_dword(pdev, cfg_addr, val);
207
208 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
209 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
210 pci_write_config_dword(pdev, cfg_addr+0x10, val);
211 }
212
213 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
214 {
215 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
216 u32 val, val2 = 0;
217 u8 pmr;
218
219 if (sc_reg > SCR_CONTROL)
220 return 0xffffffffU;
221
222 if (ap->flags & SIS_FLAG_CFGSCR)
223 return sis_scr_cfg_read(ap, sc_reg);
224
225 pci_read_config_byte(pdev, SIS_PMR, &pmr);
226
227 val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
228
229 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
230 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
231 val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
232
233 return (val | val2) & 0xfffffffb;
234 }
235
236 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
237 {
238 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
239 u8 pmr;
240
241 if (sc_reg > SCR_CONTROL)
242 return;
243
244 pci_read_config_byte(pdev, SIS_PMR, &pmr);
245
246 if (ap->flags & SIS_FLAG_CFGSCR)
247 sis_scr_cfg_write(ap, sc_reg, val);
248 else {
249 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
250 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
251 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
252 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
253 }
254 }
255
256 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
257 {
258 static int printed_version;
259 struct ata_probe_ent *probe_ent = NULL;
260 int rc;
261 u32 genctl, val;
262 struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
263 u8 pmr;
264 u8 port2_start = 0x20;
265
266 if (!printed_version++)
267 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
268
269 rc = pcim_enable_device(pdev);
270 if (rc)
271 return rc;
272
273 rc = pci_request_regions(pdev, DRV_NAME);
274 if (rc) {
275 pcim_pin_device(pdev);
276 return rc;
277 }
278
279 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
280 if (rc)
281 return rc;
282 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
283 if (rc)
284 return rc;
285
286 /* check and see if the SCRs are in IO space or PCI cfg space */
287 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
288 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
289 pi.flags |= SIS_FLAG_CFGSCR;
290
291 /* if hardware thinks SCRs are in IO space, but there are
292 * no IO resources assigned, change to PCI cfg space.
293 */
294 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
295 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
296 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
297 genctl &= ~GENCTL_IOMAPPED_SCR;
298 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
299 pi.flags |= SIS_FLAG_CFGSCR;
300 }
301
302 pci_read_config_byte(pdev, SIS_PMR, &pmr);
303 switch (ent->device) {
304 case 0x0180:
305 case 0x0181:
306
307 /* The PATA-handling is provided by pata_sis */
308 switch (pmr & 0x30) {
309 case 0x10:
310 ppi[1] = &sis_info133;
311 break;
312
313 case 0x30:
314 ppi[0] = &sis_info133;
315 break;
316 }
317 if ((pmr & SIS_PMR_COMBINED) == 0) {
318 dev_printk(KERN_INFO, &pdev->dev,
319 "Detected SiS 180/181/964 chipset in SATA mode\n");
320 port2_start = 64;
321 } else {
322 dev_printk(KERN_INFO, &pdev->dev,
323 "Detected SiS 180/181 chipset in combined mode\n");
324 port2_start=0;
325 pi.flags |= ATA_FLAG_SLAVE_POSS;
326 }
327 break;
328
329 case 0x0182:
330 case 0x0183:
331 pci_read_config_dword ( pdev, 0x6C, &val);
332 if (val & (1L << 31)) {
333 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
334 pi.flags |= ATA_FLAG_SLAVE_POSS;
335 } else {
336 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
337 }
338 break;
339
340 case 0x1182:
341 case 0x1183:
342 pci_read_config_dword(pdev, 0x64, &val);
343 if (val & 0x10000000) {
344 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
345 } else {
346 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
347 pi.flags |= ATA_FLAG_SLAVE_POSS;
348 }
349 break;
350 }
351
352 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
353 if (!probe_ent)
354 return -ENOMEM;
355
356 if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
357 void __iomem *mmio;
358
359 mmio = pcim_iomap(pdev, SIS_SCR_PCI_BAR, 0);
360 if (!mmio)
361 return -ENOMEM;
362
363 probe_ent->port[0].scr_addr = mmio;
364 probe_ent->port[1].scr_addr = mmio + port2_start;
365 }
366
367 pci_set_master(pdev);
368 pci_intx(pdev, 1);
369
370 if (!ata_device_add(probe_ent))
371 return -EIO;
372
373 devm_kfree(&pdev->dev, probe_ent);
374 return 0;
375
376 }
377
378 static int __init sis_init(void)
379 {
380 return pci_register_driver(&sis_pci_driver);
381 }
382
383 static void __exit sis_exit(void)
384 {
385 pci_unregister_driver(&sis_pci_driver);
386 }
387
388 module_init(sis_init);
389 module_exit(sis_exit);
Linux with added FPC-III support