drivers/ide/pci/siimage.c

   1 /*
   2  * linux/drivers/ide/pci/siimage.c              Version 1.11    Jan 27, 2007
   3  *
   4  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   6  * Copyright (C) 2007           MontaVista Software, Inc.
   7  *
   8  *  May be copied or modified under the terms of the GNU General Public License
   9  *
  10  *  Documentation for CMD680:
  11  *  http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
  12  *
  13  *  Documentation for SiI 3112:
  14  *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  15  *
  16  *  Errata and other documentation only available under NDA.
  17  *
  18  *
  19  *  FAQ Items:
  20  *      If you are using Marvell SATA-IDE adapters with Maxtor drives
  21  *      ensure the system is set up for ATA100/UDMA5 not UDMA6.
  22  *
  23  *      If you are using WD drives with SATA bridges you must set the
  24  *      drive to "Single". "Master" will hang
  25  *
  26  *      If you have strange problems with nVidia chipset systems please
  27  *      see the SI support documentation and update your system BIOS
  28  *      if neccessary
  29  *
  30  *  The Dell DRAC4 has some interesting features including effectively hot
  31  *  unplugging/replugging the virtual CD interface when the DRAC is reset.
  32  *  This often causes drivers/ide/siimage to panic but is ok with the rather
  33  *  smarter code in libata.
  34  */
  35
  36 #include <linux/types.h>
  37 #include <linux/module.h>
  38 #include <linux/pci.h>
  39 #include <linux/delay.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/ide.h>
  42 #include <linux/init.h>
  43
  44 #include <asm/io.h>
  45
  46 /**
  47  *      pdev_is_sata            -       check if device is SATA
  48  *      @pdev:  PCI device to check
  49  *
  50  *      Returns true if this is a SATA controller
  51  */
  52
  53 static int pdev_is_sata(struct pci_dev *pdev)
  54 {
  55         switch(pdev->device)
  56         {
  57                 case PCI_DEVICE_ID_SII_3112:
  58                 case PCI_DEVICE_ID_SII_1210SA:
  59                         return 1;
  60                 case PCI_DEVICE_ID_SII_680:
  61                         return 0;
  62         }
  63         BUG();
  64         return 0;
  65 }
  66
  67 /**
  68  *      is_sata                 -       check if hwif is SATA
  69  *      @hwif:  interface to check
  70  *
  71  *      Returns true if this is a SATA controller
  72  */
  73
  74 static inline int is_sata(ide_hwif_t *hwif)
  75 {
  76         return pdev_is_sata(hwif->pci_dev);
  77 }
  78
  79 /**
  80  *      siimage_selreg          -       return register base
  81  *      @hwif: interface
  82  *      @r: config offset
  83  *
  84  *      Turn a config register offset into the right address in either
  85  *      PCI space or MMIO space to access the control register in question
  86  *      Thankfully this is a configuration operation so isnt performance
  87  *      criticial.
  88  */
  89
  90 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  91 {
  92         unsigned long base = (unsigned long)hwif->hwif_data;
  93         base += 0xA0 + r;
  94         if(hwif->mmio)
  95                 base += (hwif->channel << 6);
  96         else
  97                 base += (hwif->channel << 4);
  98         return base;
  99 }
 100
 101 /**
 102  *      siimage_seldev          -       return register base
 103  *      @hwif: interface
 104  *      @r: config offset
 105  *
 106  *      Turn a config register offset into the right address in either
 107  *      PCI space or MMIO space to access the control register in question
 108  *      including accounting for the unit shift.
 109  */
 110
 111 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 112 {
 113         ide_hwif_t *hwif        = HWIF(drive);
 114         unsigned long base = (unsigned long)hwif->hwif_data;
 115         base += 0xA0 + r;
 116         if(hwif->mmio)
 117                 base += (hwif->channel << 6);
 118         else
 119                 base += (hwif->channel << 4);
 120         base |= drive->select.b.unit << drive->select.b.unit;
 121         return base;
 122 }
 123
 124 /**
 125  *      siimage_ratemask        -       Compute available modes
 126  *      @drive: IDE drive
 127  *
 128  *      Compute the available speeds for the devices on the interface.
 129  *      For the CMD680 this depends on the clocking mode (scsc), for the
 130  *      SI3312 SATA controller life is a bit simpler. Enforce UDMA33
 131  *      as a limit if there is no 80pin cable present.
 132  */
 133
 134 static byte siimage_ratemask (ide_drive_t *drive)
 135 {
 136         ide_hwif_t *hwif        = HWIF(drive);
 137         u8 mode = 0, scsc = 0;
 138         unsigned long base = (unsigned long) hwif->hwif_data;
 139
 140         if (hwif->mmio)
 141                 scsc = hwif->INB(base + 0x4A);
 142         else
 143                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 144
 145         if(is_sata(hwif))
 146         {
 147                 if(strstr(drive->id->model, "Maxtor"))
 148                         return 3;
 149                 return 4;
 150         }
 151
 152         if ((scsc & 0x30) == 0x10)      /* 133 */
 153                 mode = 4;
 154         else if ((scsc & 0x30) == 0x20) /* 2xPCI */
 155                 mode = 4;
 156         else if ((scsc & 0x30) == 0x00) /* 100 */
 157                 mode = 3;
 158         else    /* Disabled ? */
 159                 BUG();
 160
 161         if (!eighty_ninty_three(drive))
 162                 mode = min(mode, (u8)1);
 163         return mode;
 164 }
 165
 166 /**
 167  *      siimage_taskfile_timing -       turn timing data to a mode
 168  *      @hwif: interface to query
 169  *
 170  *      Read the timing data for the interface and return the
 171  *      mode that is being used.
 172  */
 173
 174 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
 175 {
 176         u16 timing      = 0x328a;
 177         unsigned long addr = siimage_selreg(hwif, 2);
 178
 179         if (hwif->mmio)
 180                 timing = hwif->INW(addr);
 181         else
 182                 pci_read_config_word(hwif->pci_dev, addr, &timing);
 183
 184         switch (timing) {
 185                 case 0x10c1:    return 4;
 186                 case 0x10c3:    return 3;
 187                 case 0x1104:
 188                 case 0x1281:    return 2;
 189                 case 0x2283:    return 1;
 190                 case 0x328a:
 191                 default:        return 0;
 192         }
 193 }
 194
 195 /**
 196  *      simmage_tuneproc        -       tune a drive
 197  *      @drive: drive to tune
 198  *      @mode_wanted: the target operating mode
 199  *
 200  *      Load the timing settings for this device mode into the
 201  *      controller. If we are in PIO mode 3 or 4 turn on IORDY
 202  *      monitoring (bit 9). The TF timing is bits 31:16
 203  */
 204
 205 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
 206 {
 207         ide_hwif_t *hwif        = HWIF(drive);
 208         u32 speedt              = 0;
 209         u16 speedp              = 0;
 210         unsigned long addr      = siimage_seldev(drive, 0x04);
 211         unsigned long tfaddr    = siimage_selreg(hwif, 0x02);
 212
 213         /* cheat for now and use the docs */
 214         switch (mode_wanted) {
 215         case 4:
 216                 speedp = 0x10c1;
 217                 speedt = 0x10c1;
 218                 break;
 219         case 3:
 220                 speedp = 0x10c3;
 221                 speedt = 0x10c3;
 222                 break;
 223         case 2:
 224                 speedp = 0x1104;
 225                 speedt = 0x1281;
 226                 break;
 227         case 1:
 228                 speedp = 0x2283;
 229                 speedt = 0x2283;
 230                 break;
 231         case 0:
 232         default:
 233                 speedp = 0x328a;
 234                 speedt = 0x328a;
 235                 break;
 236         }
 237
 238         if (hwif->mmio) {
 239                 hwif->OUTW(speedp, addr);
 240                 hwif->OUTW(speedt, tfaddr);
 241                 /* Now set up IORDY */
 242                 if(mode_wanted == 3 || mode_wanted == 4)
 243                         hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
 244                 else
 245                         hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
 246         } else {
 247                 pci_write_config_word(hwif->pci_dev, addr, speedp);
 248                 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
 249                 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
 250                 speedp &= ~0x200;
 251                 /* Set IORDY for mode 3 or 4 */
 252                 if(mode_wanted == 3 || mode_wanted == 4)
 253                         speedp |= 0x200;
 254                 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
 255         }
 256 }
 257
 258 /**
 259  *      config_siimage_chipset_for_pio  -       set drive timings
 260  *      @drive: drive to tune
 261  *      @speed we want
 262  *
 263  *      Compute the best pio mode we can for a given device. Also honour
 264  *      the timings for the driver when dealing with mixed devices. Some
 265  *      of this is ugly but its all wrapped up here
 266  *
 267  *      The SI680 can also do VDMA - we need to start using that
 268  *
 269  *      FIXME: we use the BIOS channel timings to avoid driving the task
 270  *      files too fast at the disk. We need to compute the master/slave
 271  *      drive PIO mode properly so that we can up the speed on a hotplug
 272  *      system.
 273  */
 274
 275 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 276 {
 277         u8 channel_timings      = siimage_taskfile_timing(HWIF(drive));
 278         u8 speed = 0, set_pio   = ide_get_best_pio_mode(drive, 4, 5, NULL);
 279
 280         /* WARNING PIO timing mess is going to happen b/w devices, argh */
 281         if ((channel_timings != set_pio) && (set_pio > channel_timings))
 282                 set_pio = channel_timings;
 283
 284         siimage_tuneproc(drive, set_pio);
 285         speed = XFER_PIO_0 + set_pio;
 286         if (set_speed)
 287                 (void) ide_config_drive_speed(drive, speed);
 288 }
 289
 290 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 291 {
 292         config_siimage_chipset_for_pio(drive, set_speed);
 293 }
 294
 295 /**
 296  *      siimage_tune_chipset    -       set controller timings
 297  *      @drive: Drive to set up
 298  *      @xferspeed: speed we want to achieve
 299  *
 300  *      Tune the SII chipset for the desired mode. If we can't achieve
 301  *      the desired mode then tune for a lower one, but ultimately
 302  *      make the thing work.
 303  */
 304
 305 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
 306 {
 307         u8 ultra6[]             = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
 308         u8 ultra5[]             = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
 309         u16 dma[]               = { 0x2208, 0x10C2, 0x10C1 };
 310
 311         ide_hwif_t *hwif        = HWIF(drive);
 312         u16 ultra = 0, multi    = 0;
 313         u8 mode = 0, unit       = drive->select.b.unit;
 314         u8 speed                = ide_rate_filter(siimage_ratemask(drive), xferspeed);
 315         unsigned long base      = (unsigned long)hwif->hwif_data;
 316         u8 scsc = 0, addr_mask  = ((hwif->channel) ?
 317                                     ((hwif->mmio) ? 0xF4 : 0x84) :
 318                                     ((hwif->mmio) ? 0xB4 : 0x80));
 319
 320         unsigned long ma        = siimage_seldev(drive, 0x08);
 321         unsigned long ua        = siimage_seldev(drive, 0x0C);
 322
 323         if (hwif->mmio) {
 324                 scsc = hwif->INB(base + 0x4A);
 325                 mode = hwif->INB(base + addr_mask);
 326                 multi = hwif->INW(ma);
 327                 ultra = hwif->INW(ua);
 328         } else {
 329                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 330                 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
 331                 pci_read_config_word(hwif->pci_dev, ma, &multi);
 332                 pci_read_config_word(hwif->pci_dev, ua, &ultra);
 333         }
 334
 335         mode &= ~((unit) ? 0x30 : 0x03);
 336         ultra &= ~0x3F;
 337         scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
 338
 339         scsc = is_sata(hwif) ? 1 : scsc;
 340
 341         switch(speed) {
 342                 case XFER_PIO_4:
 343                 case XFER_PIO_3:
 344                 case XFER_PIO_2:
 345                 case XFER_PIO_1:
 346                 case XFER_PIO_0:
 347                         siimage_tuneproc(drive, (speed - XFER_PIO_0));
 348                         mode |= ((unit) ? 0x10 : 0x01);
 349                         break;
 350                 case XFER_MW_DMA_2:
 351                 case XFER_MW_DMA_1:
 352                 case XFER_MW_DMA_0:
 353                         multi = dma[speed - XFER_MW_DMA_0];
 354                         mode |= ((unit) ? 0x20 : 0x02);
 355                         config_siimage_chipset_for_pio(drive, 0);
 356                         break;
 357                 case XFER_UDMA_6:
 358                 case XFER_UDMA_5:
 359                 case XFER_UDMA_4:
 360                 case XFER_UDMA_3:
 361                 case XFER_UDMA_2:
 362                 case XFER_UDMA_1:
 363                 case XFER_UDMA_0:
 364                         multi = dma[2];
 365                         ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
 366                                            (ultra5[speed - XFER_UDMA_0]));
 367                         mode |= ((unit) ? 0x30 : 0x03);
 368                         config_siimage_chipset_for_pio(drive, 0);
 369                         break;
 370                 default:
 371                         return 1;
 372         }
 373
 374         if (hwif->mmio) {
 375                 hwif->OUTB(mode, base + addr_mask);
 376                 hwif->OUTW(multi, ma);
 377                 hwif->OUTW(ultra, ua);
 378         } else {
 379                 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
 380                 pci_write_config_word(hwif->pci_dev, ma, multi);
 381                 pci_write_config_word(hwif->pci_dev, ua, ultra);
 382         }
 383         return (ide_config_drive_speed(drive, speed));
 384 }
 385
 386 /**
 387  *      config_chipset_for_dma  -       configure for DMA
 388  *      @drive: drive to configure
 389  *
 390  *      Called by the IDE layer when it wants the timings set up.
 391  *      For the CMD680 we also need to set up the PIO timings and
 392  *      enable DMA.
 393  */
 394
 395 static int config_chipset_for_dma (ide_drive_t *drive)
 396 {
 397         u8 speed        = ide_dma_speed(drive, siimage_ratemask(drive));
 398
 399         config_chipset_for_pio(drive, !speed);
 400
 401         if (!speed)
 402                 return 0;
 403
 404         if (siimage_tune_chipset(drive, speed))
 405                 return 0;
 406
 407         return ide_dma_enable(drive);
 408 }
 409
 410 /**
 411  *      siimage_configure_drive_for_dma -       set up for DMA transfers
 412  *      @drive: drive we are going to set up
 413  *
 414  *      Set up the drive for DMA, tune the controller and drive as
 415  *      required. If the drive isn't suitable for DMA or we hit
 416  *      other problems then we will drop down to PIO and set up
 417  *      PIO appropriately
 418  */
 419
 420 static int siimage_config_drive_for_dma (ide_drive_t *drive)
 421 {
 422         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 423                 return 0;
 424
 425         if (ide_use_fast_pio(drive))
 426                 config_chipset_for_pio(drive, 1);
 427
 428         return -1;
 429 }
 430
 431 /* returns 1 if dma irq issued, 0 otherwise */
 432 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
 433 {
 434         ide_hwif_t *hwif        = HWIF(drive);
 435         u8 dma_altstat          = 0;
 436         unsigned long addr      = siimage_selreg(hwif, 1);
 437
 438         /* return 1 if INTR asserted */
 439         if ((hwif->INB(hwif->dma_status) & 4) == 4)
 440                 return 1;
 441
 442         /* return 1 if Device INTR asserted */
 443         pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
 444         if (dma_altstat & 8)
 445                 return 0;       //return 1;
 446         return 0;
 447 }
 448
 449 /**
 450  *      siimage_mmio_ide_dma_test_irq   -       check we caused an IRQ
 451  *      @drive: drive we are testing
 452  *
 453  *      Check if we caused an IDE DMA interrupt. We may also have caused
 454  *      SATA status interrupts, if so we clean them up and continue.
 455  */
 456
 457 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
 458 {
 459         ide_hwif_t *hwif        = HWIF(drive);
 460         unsigned long base      = (unsigned long)hwif->hwif_data;
 461         unsigned long addr      = siimage_selreg(hwif, 0x1);
 462
 463         if (SATA_ERROR_REG) {
 464                 u32 ext_stat = readl((void __iomem *)(base + 0x10));
 465                 u8 watchdog = 0;
 466                 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
 467                         u32 sata_error = readl((void __iomem *)SATA_ERROR_REG);
 468                         writel(sata_error, (void __iomem *)SATA_ERROR_REG);
 469                         watchdog = (sata_error & 0x00680000) ? 1 : 0;
 470                         printk(KERN_WARNING "%s: sata_error = 0x%08x, "
 471                                 "watchdog = %d, %s\n",
 472                                 drive->name, sata_error, watchdog,
 473                                 __FUNCTION__);
 474
 475                 } else {
 476                         watchdog = (ext_stat & 0x8000) ? 1 : 0;
 477                 }
 478                 ext_stat >>= 16;
 479
 480                 if (!(ext_stat & 0x0404) && !watchdog)
 481                         return 0;
 482         }
 483
 484         /* return 1 if INTR asserted */
 485         if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
 486                 return 1;
 487
 488         /* return 1 if Device INTR asserted */
 489         if ((readb((void __iomem *)addr) & 8) == 8)
 490                 return 0;       //return 1;
 491
 492         return 0;
 493 }
 494
 495 /**
 496  *      siimage_busproc         -       bus isolation ioctl
 497  *      @drive: drive to isolate/restore
 498  *      @state: bus state to set
 499  *
 500  *      Used by the SII3112 to handle bus isolation. As this is a
 501  *      SATA controller the work required is quite limited, we
 502  *      just have to clean up the statistics
 503  */
 504
 505 static int siimage_busproc (ide_drive_t * drive, int state)
 506 {
 507         ide_hwif_t *hwif        = HWIF(drive);
 508         u32 stat_config         = 0;
 509         unsigned long addr      = siimage_selreg(hwif, 0);
 510
 511         if (hwif->mmio)
 512                 stat_config = readl((void __iomem *)addr);
 513         else
 514                 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
 515
 516         switch (state) {
 517                 case BUSSTATE_ON:
 518                         hwif->drives[0].failures = 0;
 519                         hwif->drives[1].failures = 0;
 520                         break;
 521                 case BUSSTATE_OFF:
 522                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 523                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 524                         break;
 525                 case BUSSTATE_TRISTATE:
 526                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 527                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 528                         break;
 529                 default:
 530                         return -EINVAL;
 531         }
 532         hwif->bus_state = state;
 533         return 0;
 534 }
 535
 536 /**
 537  *      siimage_reset_poll      -       wait for sata reset
 538  *      @drive: drive we are resetting
 539  *
 540  *      Poll the SATA phy and see whether it has come back from the dead
 541  *      yet.
 542  */
 543
 544 static int siimage_reset_poll (ide_drive_t *drive)
 545 {
 546         if (SATA_STATUS_REG) {
 547                 ide_hwif_t *hwif        = HWIF(drive);
 548
 549                 /* SATA_STATUS_REG is valid only when in MMIO mode */
 550                 if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) {
 551                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 552                                 hwif->name, readl((void __iomem *)SATA_STATUS_REG));
 553                         HWGROUP(drive)->polling = 0;
 554                         return ide_started;
 555                 }
 556                 return 0;
 557         } else {
 558                 return 0;
 559         }
 560 }
 561
 562 /**
 563  *      siimage_pre_reset       -       reset hook
 564  *      @drive: IDE device being reset
 565  *
 566  *      For the SATA devices we need to handle recalibration/geometry
 567  *      differently
 568  */
 569
 570 static void siimage_pre_reset (ide_drive_t *drive)
 571 {
 572         if (drive->media != ide_disk)
 573                 return;
 574
 575         if (is_sata(HWIF(drive)))
 576         {
 577                 drive->special.b.set_geometry = 0;
 578                 drive->special.b.recalibrate = 0;
 579         }
 580 }
 581
 582 /**
 583  *      siimage_reset   -       reset a device on an siimage controller
 584  *      @drive: drive to reset
 585  *
 586  *      Perform a controller level reset fo the device. For
 587  *      SATA we must also check the PHY.
 588  */
 589
 590 static void siimage_reset (ide_drive_t *drive)
 591 {
 592         ide_hwif_t *hwif        = HWIF(drive);
 593         u8 reset                = 0;
 594         unsigned long addr      = siimage_selreg(hwif, 0);
 595
 596         if (hwif->mmio) {
 597                 reset = hwif->INB(addr);
 598                 hwif->OUTB((reset|0x03), addr);
 599                 /* FIXME:posting */
 600                 udelay(25);
 601                 hwif->OUTB(reset, addr);
 602                 (void) hwif->INB(addr);
 603         } else {
 604                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 605                 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
 606                 udelay(25);
 607                 pci_write_config_byte(hwif->pci_dev, addr, reset);
 608                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 609         }
 610
 611         if (SATA_STATUS_REG) {
 612                 /* SATA_STATUS_REG is valid only when in MMIO mode */
 613                 u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG);
 614                 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
 615                         hwif->name, sata_stat, __FUNCTION__);
 616                 if (!(sata_stat)) {
 617                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 618                                 hwif->name, sata_stat);
 619                         drive->failures++;
 620                 }
 621         }
 622
 623 }
 624
 625 /**
 626  *      proc_reports_siimage            -       add siimage controller to proc
 627  *      @dev: PCI device
 628  *      @clocking: SCSC value
 629  *      @name: controller name
 630  *
 631  *      Report the clocking mode of the controller and add it to
 632  *      the /proc interface layer
 633  */
 634
 635 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
 636 {
 637         if (!pdev_is_sata(dev)) {
 638                 printk(KERN_INFO "%s: BASE CLOCK ", name);
 639                 clocking &= 0x03;
 640                 switch (clocking) {
 641                         case 0x03: printk("DISABLED!\n"); break;
 642                         case 0x02: printk("== 2X PCI\n"); break;
 643                         case 0x01: printk("== 133\n"); break;
 644                         case 0x00: printk("== 100\n"); break;
 645                 }
 646         }
 647 }
 648
 649 /**
 650  *      setup_mmio_siimage      -       switch an SI controller into MMIO
 651  *      @dev: PCI device we are configuring
 652  *      @name: device name
 653  *
 654  *      Attempt to put the device into mmio mode. There are some slight
 655  *      complications here with certain systems where the mmio bar isnt
 656  *      mapped so we have to be sure we can fall back to I/O.
 657  */
 658
 659 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
 660 {
 661         unsigned long bar5      = pci_resource_start(dev, 5);
 662         unsigned long barsize   = pci_resource_len(dev, 5);
 663         u8 tmpbyte      = 0;
 664         void __iomem *ioaddr;
 665         u32 tmp, irq_mask;
 666
 667         /*
 668          *      Drop back to PIO if we can't map the mmio. Some
 669          *      systems seem to get terminally confused in the PCI
 670          *      spaces.
 671          */
 672
 673         if(!request_mem_region(bar5, barsize, name))
 674         {
 675                 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
 676                 return 0;
 677         }
 678
 679         ioaddr = ioremap(bar5, barsize);
 680
 681         if (ioaddr == NULL)
 682         {
 683                 release_mem_region(bar5, barsize);
 684                 return 0;
 685         }
 686
 687         pci_set_master(dev);
 688         pci_set_drvdata(dev, (void *) ioaddr);
 689
 690         if (pdev_is_sata(dev)) {
 691                 /* make sure IDE0/1 interrupts are not masked */
 692                 irq_mask = (1 << 22) | (1 << 23);
 693                 tmp = readl(ioaddr + 0x48);
 694                 if (tmp & irq_mask) {
 695                         tmp &= ~irq_mask;
 696                         writel(tmp, ioaddr + 0x48);
 697                         readl(ioaddr + 0x48); /* flush */
 698                 }
 699                 writel(0, ioaddr + 0x148);
 700                 writel(0, ioaddr + 0x1C8);
 701         }
 702
 703         writeb(0, ioaddr + 0xB4);
 704         writeb(0, ioaddr + 0xF4);
 705         tmpbyte = readb(ioaddr + 0x4A);
 706
 707         switch(tmpbyte & 0x30) {
 708                 case 0x00:
 709                         /* In 100 MHz clocking, try and switch to 133 */
 710                         writeb(tmpbyte|0x10, ioaddr + 0x4A);
 711                         break;
 712                 case 0x10:
 713                         /* On 133Mhz clocking */
 714                         break;
 715                 case 0x20:
 716                         /* On PCIx2 clocking */
 717                         break;
 718                 case 0x30:
 719                         /* Clocking is disabled */
 720                         /* 133 clock attempt to force it on */
 721                         writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
 722                         break;
 723         }
 724
 725         writeb(      0x72, ioaddr + 0xA1);
 726         writew(    0x328A, ioaddr + 0xA2);
 727         writel(0x62DD62DD, ioaddr + 0xA4);
 728         writel(0x43924392, ioaddr + 0xA8);
 729         writel(0x40094009, ioaddr + 0xAC);
 730         writeb(      0x72, ioaddr + 0xE1);
 731         writew(    0x328A, ioaddr + 0xE2);
 732         writel(0x62DD62DD, ioaddr + 0xE4);
 733         writel(0x43924392, ioaddr + 0xE8);
 734         writel(0x40094009, ioaddr + 0xEC);
 735
 736         if (pdev_is_sata(dev)) {
 737                 writel(0xFFFF0000, ioaddr + 0x108);
 738                 writel(0xFFFF0000, ioaddr + 0x188);
 739                 writel(0x00680000, ioaddr + 0x148);
 740                 writel(0x00680000, ioaddr + 0x1C8);
 741         }
 742
 743         tmpbyte = readb(ioaddr + 0x4A);
 744
 745         proc_reports_siimage(dev, (tmpbyte>>4), name);
 746         return 1;
 747 }
 748
 749 /**
 750  *      init_chipset_siimage    -       set up an SI device
 751  *      @dev: PCI device
 752  *      @name: device name
 753  *
 754  *      Perform the initial PCI set up for this device. Attempt to switch
 755  *      to 133MHz clocking if the system isn't already set up to do it.
 756  */
 757
 758 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
 759 {
 760         u32 class_rev   = 0;
 761         u8 tmpbyte      = 0;
 762         u8 BA5_EN       = 0;
 763
 764         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 765         class_rev &= 0xff;
 766         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
 767
 768         pci_read_config_byte(dev, 0x8A, &BA5_EN);
 769         if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
 770                 if (setup_mmio_siimage(dev, name)) {
 771                         return 0;
 772                 }
 773         }
 774
 775         pci_write_config_byte(dev, 0x80, 0x00);
 776         pci_write_config_byte(dev, 0x84, 0x00);
 777         pci_read_config_byte(dev, 0x8A, &tmpbyte);
 778         switch(tmpbyte & 0x30) {
 779                 case 0x00:
 780                         /* 133 clock attempt to force it on */
 781                         pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
 782                 case 0x30:
 783                         /* if clocking is disabled */
 784                         /* 133 clock attempt to force it on */
 785                         pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
 786                 case 0x10:
 787                         /* 133 already */
 788                         break;
 789                 case 0x20:
 790                         /* BIOS set PCI x2 clocking */
 791                         break;
 792         }
 793
 794         pci_read_config_byte(dev,   0x8A, &tmpbyte);
 795
 796         pci_write_config_byte(dev,  0xA1, 0x72);
 797         pci_write_config_word(dev,  0xA2, 0x328A);
 798         pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
 799         pci_write_config_dword(dev, 0xA8, 0x43924392);
 800         pci_write_config_dword(dev, 0xAC, 0x40094009);
 801         pci_write_config_byte(dev,  0xB1, 0x72);
 802         pci_write_config_word(dev,  0xB2, 0x328A);
 803         pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
 804         pci_write_config_dword(dev, 0xB8, 0x43924392);
 805         pci_write_config_dword(dev, 0xBC, 0x40094009);
 806
 807         proc_reports_siimage(dev, (tmpbyte>>4), name);
 808         return 0;
 809 }
 810
 811 /**
 812  *      init_mmio_iops_siimage  -       set up the iops for MMIO
 813  *      @hwif: interface to set up
 814  *
 815  *      The basic setup here is fairly simple, we can use standard MMIO
 816  *      operations. However we do have to set the taskfile register offsets
 817  *      by hand as there isnt a standard defined layout for them this
 818  *      time.
 819  *
 820  *      The hardware supports buffered taskfiles and also some rather nice
 821  *      extended PRD tables. For better SI3112 support use the libata driver
 822  */
 823
 824 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
 825 {
 826         struct pci_dev *dev     = hwif->pci_dev;
 827         void *addr              = pci_get_drvdata(dev);
 828         u8 ch                   = hwif->channel;
 829         hw_regs_t               hw;
 830         unsigned long           base;
 831
 832         /*
 833          *      Fill in the basic HWIF bits
 834          */
 835
 836         default_hwif_mmiops(hwif);
 837         hwif->hwif_data                 = addr;
 838
 839         /*
 840          *      Now set up the hw. We have to do this ourselves as
 841          *      the MMIO layout isnt the same as the the standard port
 842          *      based I/O
 843          */
 844
 845         memset(&hw, 0, sizeof(hw_regs_t));
 846
 847         base = (unsigned long)addr;
 848         if (ch)
 849                 base += 0xC0;
 850         else
 851                 base += 0x80;
 852
 853         /*
 854          *      The buffered task file doesn't have status/control
 855          *      so we can't currently use it sanely since we want to
 856          *      use LBA48 mode.
 857          */
 858         hw.io_ports[IDE_DATA_OFFSET]    = base;
 859         hw.io_ports[IDE_ERROR_OFFSET]   = base + 1;
 860         hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
 861         hw.io_ports[IDE_SECTOR_OFFSET]  = base + 3;
 862         hw.io_ports[IDE_LCYL_OFFSET]    = base + 4;
 863         hw.io_ports[IDE_HCYL_OFFSET]    = base + 5;
 864         hw.io_ports[IDE_SELECT_OFFSET]  = base + 6;
 865         hw.io_ports[IDE_STATUS_OFFSET]  = base + 7;
 866         hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
 867
 868         hw.io_ports[IDE_IRQ_OFFSET]     = 0;
 869
 870         if (pdev_is_sata(dev)) {
 871                 base = (unsigned long)addr;
 872                 if (ch)
 873                         base += 0x80;
 874                 hwif->sata_scr[SATA_STATUS_OFFSET]      = base + 0x104;
 875                 hwif->sata_scr[SATA_ERROR_OFFSET]       = base + 0x108;
 876                 hwif->sata_scr[SATA_CONTROL_OFFSET]     = base + 0x100;
 877                 hwif->sata_misc[SATA_MISC_OFFSET]       = base + 0x140;
 878                 hwif->sata_misc[SATA_PHY_OFFSET]        = base + 0x144;
 879                 hwif->sata_misc[SATA_IEN_OFFSET]        = base + 0x148;
 880         }
 881
 882         hw.irq                          = hwif->pci_dev->irq;
 883
 884         memcpy(&hwif->hw, &hw, sizeof(hw));
 885         memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
 886
 887         hwif->irq                       = hw.irq;
 888
 889         base = (unsigned long) addr;
 890
 891         hwif->dma_base                  = base + (ch ? 0x08 : 0x00);
 892
 893         hwif->mmio = 1;
 894 }
 895
 896 static int is_dev_seagate_sata(ide_drive_t *drive)
 897 {
 898         const char *s = &drive->id->model[0];
 899         unsigned len;
 900
 901         if (!drive->present)
 902                 return 0;
 903
 904         len = strnlen(s, sizeof(drive->id->model));
 905
 906         if ((len > 4) && (!memcmp(s, "ST", 2))) {
 907                 if ((!memcmp(s + len - 2, "AS", 2)) ||
 908                     (!memcmp(s + len - 3, "ASL", 3))) {
 909                         printk(KERN_INFO "%s: applying pessimistic Seagate "
 910                                          "errata fix\n", drive->name);
 911                         return 1;
 912                 }
 913         }
 914         return 0;
 915 }
 916
 917 /**
 918  *      siimage_fixup           -       post probe fixups
 919  *      @hwif: interface to fix up
 920  *
 921  *      Called after drive probe we use this to decide whether the
 922  *      Seagate fixup must be applied. This used to be in init_iops but
 923  *      that can occur before we know what drives are present.
 924  */
 925
 926 static void __devinit siimage_fixup(ide_hwif_t *hwif)
 927 {
 928         /* Try and raise the rqsize */
 929         if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
 930                 hwif->rqsize = 128;
 931 }
 932
 933 /**
 934  *      init_iops_siimage       -       set up iops
 935  *      @hwif: interface to set up
 936  *
 937  *      Do the basic setup for the SIIMAGE hardware interface
 938  *      and then do the MMIO setup if we can. This is the first
 939  *      look in we get for setting up the hwif so that we
 940  *      can get the iops right before using them.
 941  */
 942
 943 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
 944 {
 945         struct pci_dev *dev     = hwif->pci_dev;
 946         u32 class_rev           = 0;
 947
 948         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 949         class_rev &= 0xff;
 950
 951         hwif->hwif_data = NULL;
 952
 953         /* Pessimal until we finish probing */
 954         hwif->rqsize = 15;
 955
 956         if (pci_get_drvdata(dev) == NULL)
 957                 return;
 958         init_mmio_iops_siimage(hwif);
 959 }
 960
 961 /**
 962  *      ata66_siimage   -       check for 80 pin cable
 963  *      @hwif: interface to check
 964  *
 965  *      Check for the presence of an ATA66 capable cable on the
 966  *      interface.
 967  */
 968
 969 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
 970 {
 971         unsigned long addr = siimage_selreg(hwif, 0);
 972         if (pci_get_drvdata(hwif->pci_dev) == NULL) {
 973                 u8 ata66 = 0;
 974                 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
 975                 return (ata66 & 0x01) ? 1 : 0;
 976         }
 977
 978         return (hwif->INB(addr) & 0x01) ? 1 : 0;
 979 }
 980
 981 /**
 982  *      init_hwif_siimage       -       set up hwif structs
 983  *      @hwif: interface to set up
 984  *
 985  *      We do the basic set up of the interface structure. The SIIMAGE
 986  *      requires several custom handlers so we override the default
 987  *      ide DMA handlers appropriately
 988  */
 989
 990 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
 991 {
 992         hwif->autodma = 0;
 993
 994         hwif->resetproc = &siimage_reset;
 995         hwif->speedproc = &siimage_tune_chipset;
 996         hwif->tuneproc  = &siimage_tuneproc;
 997         hwif->reset_poll = &siimage_reset_poll;
 998         hwif->pre_reset = &siimage_pre_reset;
 999
1000         if(is_sata(hwif)) {
1001                 static int first = 1;
1002
1003                 hwif->busproc   = &siimage_busproc;
1004
1005                 if (first) {
1006                         printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
1007                         first = 0;
1008                 }
1009         }
1010         if (!hwif->dma_base) {
1011                 hwif->drives[0].autotune = 1;
1012                 hwif->drives[1].autotune = 1;
1013                 return;
1014         }
1015
1016         hwif->ultra_mask = 0x7f;
1017         hwif->mwdma_mask = 0x07;
1018         hwif->swdma_mask = 0x07;
1019
1020         if (!is_sata(hwif))
1021                 hwif->atapi_dma = 1;
1022
1023         hwif->ide_dma_check = &siimage_config_drive_for_dma;
1024         if (!(hwif->udma_four))
1025                 hwif->udma_four = ata66_siimage(hwif);
1026
1027         if (hwif->mmio) {
1028                 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1029         } else {
1030                 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1031         }
1032
1033         /*
1034          *      The BIOS often doesn't set up DMA on this controller
1035          *      so we always do it.
1036          */
1037
1038         hwif->autodma = 1;
1039         hwif->drives[0].autodma = hwif->autodma;
1040         hwif->drives[1].autodma = hwif->autodma;
1041 }
1042
1043 #define DECLARE_SII_DEV(name_str)                       \
1044         {                                               \
1045                 .name           = name_str,             \
1046                 .init_chipset   = init_chipset_siimage, \
1047                 .init_iops      = init_iops_siimage,    \
1048                 .init_hwif      = init_hwif_siimage,    \
1049                 .fixup          = siimage_fixup,        \
1050                 .channels       = 2,                    \
1051                 .autodma        = AUTODMA,              \
1052                 .bootable       = ON_BOARD,             \
1053         }
1054
1055 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1056         /* 0 */ DECLARE_SII_DEV("SiI680"),
1057         /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1058         /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1059 };
1060
1061 /**
1062  *      siimage_init_one        -       pci layer discovery entry
1063  *      @dev: PCI device
1064  *      @id: ident table entry
1065  *
1066  *      Called by the PCI code when it finds an SI680 or SI3112 controller.
1067  *      We then use the IDE PCI generic helper to do most of the work.
1068  */
1069
1070 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1071 {
1072         return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1073 }
1074
1075 static struct pci_device_id siimage_pci_tbl[] = {
1076         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1077 #ifdef CONFIG_BLK_DEV_IDE_SATA
1078         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1079         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1080 #endif
1081         { 0, },
1082 };
1083 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1084
1085 static struct pci_driver driver = {
1086         .name           = "SiI_IDE",
1087         .id_table       = siimage_pci_tbl,
1088         .probe          = siimage_init_one,
1089 };
1090
1091 static int __init siimage_ide_init(void)
1092 {
1093         return ide_pci_register_driver(&driver);
1094 }
1095
1096 module_init(siimage_ide_init);
1097
1098 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1099 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1100 MODULE_LICENSE("GPL");