drivers/infiniband/hw/ipath/ipath_registers.h

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #ifndef _IPATH_REGISTERS_H
  35 #define _IPATH_REGISTERS_H
  36
  37 /*
  38  * This file should only be included by kernel source, and by the diags.  It
  39  * defines the registers, and their contents, for InfiniPath chips.
  40  */
  41
  42 /*
  43  * These are the InfiniPath register and buffer bit definitions,
  44  * that are visible to software, and needed only by the kernel
  45  * and diag code.  A few, that are visible to protocol and user
  46  * code are in ipath_common.h.  Some bits are specific
  47  * to a given chip implementation, and have been moved to the
  48  * chip-specific source file
  49  */
  50
  51 /* kr_revision bits */
  52 #define INFINIPATH_R_CHIPREVMINOR_MASK 0xFF
  53 #define INFINIPATH_R_CHIPREVMINOR_SHIFT 0
  54 #define INFINIPATH_R_CHIPREVMAJOR_MASK 0xFF
  55 #define INFINIPATH_R_CHIPREVMAJOR_SHIFT 8
  56 #define INFINIPATH_R_ARCH_MASK 0xFF
  57 #define INFINIPATH_R_ARCH_SHIFT 16
  58 #define INFINIPATH_R_SOFTWARE_MASK 0xFF
  59 #define INFINIPATH_R_SOFTWARE_SHIFT 24
  60 #define INFINIPATH_R_BOARDID_MASK 0xFF
  61 #define INFINIPATH_R_BOARDID_SHIFT 32
  62
  63 /* kr_control bits */
  64 #define INFINIPATH_C_FREEZEMODE 0x00000002
  65 #define INFINIPATH_C_LINKENABLE 0x00000004
  66 #define INFINIPATH_C_RESET 0x00000001
  67
  68 /* kr_sendctrl bits */
  69 #define INFINIPATH_S_DISARMPIOBUF_SHIFT 16
  70
  71 #define IPATH_S_ABORT           0
  72 #define IPATH_S_PIOINTBUFAVAIL  1
  73 #define IPATH_S_PIOBUFAVAILUPD  2
  74 #define IPATH_S_PIOENABLE       3
  75 #define IPATH_S_DISARM          31
  76
  77 #define INFINIPATH_S_ABORT              (1U << IPATH_S_ABORT)
  78 #define INFINIPATH_S_PIOINTBUFAVAIL     (1U << IPATH_S_PIOINTBUFAVAIL)
  79 #define INFINIPATH_S_PIOBUFAVAILUPD     (1U << IPATH_S_PIOBUFAVAILUPD)
  80 #define INFINIPATH_S_PIOENABLE          (1U << IPATH_S_PIOENABLE)
  81 #define INFINIPATH_S_DISARM             (1U << IPATH_S_DISARM)
  82
  83 /* kr_rcvctrl bits */
  84 #define INFINIPATH_R_PORTENABLE_SHIFT 0
  85 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
  86 #define INFINIPATH_R_TAILUPD   0x80000000
  87
  88 /* kr_intstatus, kr_intclear, kr_intmask bits */
  89 #define INFINIPATH_I_RCVURG_SHIFT 0
  90 #define INFINIPATH_I_RCVAVAIL_SHIFT 12
  91 #define INFINIPATH_I_ERROR        0x80000000
  92 #define INFINIPATH_I_SPIOSENT     0x40000000
  93 #define INFINIPATH_I_SPIOBUFAVAIL 0x20000000
  94 #define INFINIPATH_I_GPIO         0x10000000
  95
  96 /* kr_errorstatus, kr_errorclear, kr_errormask bits */
  97 #define INFINIPATH_E_RFORMATERR      0x0000000000000001ULL
  98 #define INFINIPATH_E_RVCRC           0x0000000000000002ULL
  99 #define INFINIPATH_E_RICRC           0x0000000000000004ULL
 100 #define INFINIPATH_E_RMINPKTLEN      0x0000000000000008ULL
 101 #define INFINIPATH_E_RMAXPKTLEN      0x0000000000000010ULL
 102 #define INFINIPATH_E_RLONGPKTLEN     0x0000000000000020ULL
 103 #define INFINIPATH_E_RSHORTPKTLEN    0x0000000000000040ULL
 104 #define INFINIPATH_E_RUNEXPCHAR      0x0000000000000080ULL
 105 #define INFINIPATH_E_RUNSUPVL        0x0000000000000100ULL
 106 #define INFINIPATH_E_REBP            0x0000000000000200ULL
 107 #define INFINIPATH_E_RIBFLOW         0x0000000000000400ULL
 108 #define INFINIPATH_E_RBADVERSION     0x0000000000000800ULL
 109 #define INFINIPATH_E_RRCVEGRFULL     0x0000000000001000ULL
 110 #define INFINIPATH_E_RRCVHDRFULL     0x0000000000002000ULL
 111 #define INFINIPATH_E_RBADTID         0x0000000000004000ULL
 112 #define INFINIPATH_E_RHDRLEN         0x0000000000008000ULL
 113 #define INFINIPATH_E_RHDR            0x0000000000010000ULL
 114 #define INFINIPATH_E_RIBLOSTLINK     0x0000000000020000ULL
 115 #define INFINIPATH_E_SMINPKTLEN      0x0000000020000000ULL
 116 #define INFINIPATH_E_SMAXPKTLEN      0x0000000040000000ULL
 117 #define INFINIPATH_E_SUNDERRUN       0x0000000080000000ULL
 118 #define INFINIPATH_E_SPKTLEN         0x0000000100000000ULL
 119 #define INFINIPATH_E_SDROPPEDSMPPKT  0x0000000200000000ULL
 120 #define INFINIPATH_E_SDROPPEDDATAPKT 0x0000000400000000ULL
 121 #define INFINIPATH_E_SPIOARMLAUNCH   0x0000000800000000ULL
 122 #define INFINIPATH_E_SUNEXPERRPKTNUM 0x0000001000000000ULL
 123 #define INFINIPATH_E_SUNSUPVL        0x0000002000000000ULL
 124 #define INFINIPATH_E_IBSTATUSCHANGED 0x0001000000000000ULL
 125 #define INFINIPATH_E_INVALIDADDR     0x0002000000000000ULL
 126 #define INFINIPATH_E_RESET           0x0004000000000000ULL
 127 #define INFINIPATH_E_HARDWARE        0x0008000000000000ULL
 128
 129 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 130 /* TXEMEMPARITYERR bit 0: PIObuf, 1: PIOpbc, 2: launchfifo
 131  * RXEMEMPARITYERR bit 0: rcvbuf, 1: lookupq, 2: eagerTID, 3: expTID
 132  *              bit 4: flag buffer, 5: datainfo, 6: header info */
 133 #define INFINIPATH_HWE_TXEMEMPARITYERR_MASK 0xFULL
 134 #define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40
 135 #define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL
 136 #define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44
 137 #define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL
 138 #define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL
 139 /* txe mem parity errors (shift by INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) */
 140 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF   0x1ULL
 141 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC   0x2ULL
 142 #define INFINIPATH_HWE_TXEMEMPARITYERR_PIOLAUNCHFIFO 0x4ULL
 143 /* rxe mem parity errors (shift by INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) */
 144 #define INFINIPATH_HWE_RXEMEMPARITYERR_RCVBUF   0x01ULL
 145 #define INFINIPATH_HWE_RXEMEMPARITYERR_LOOKUPQ  0x02ULL
 146 #define INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID 0x04ULL
 147 #define INFINIPATH_HWE_RXEMEMPARITYERR_EXPTID   0x08ULL
 148 #define INFINIPATH_HWE_RXEMEMPARITYERR_FLAGBUF  0x10ULL
 149 #define INFINIPATH_HWE_RXEMEMPARITYERR_DATAINFO 0x20ULL
 150 #define INFINIPATH_HWE_RXEMEMPARITYERR_HDRINFO  0x40ULL
 151 /* waldo specific -- find the rest in ipath_6110.c */
 152 #define INFINIPATH_HWE_RXDSYNCMEMPARITYERR  0x0000000400000000ULL
 153 /* monty specific -- find the rest in ipath_6120.c */
 154 #define INFINIPATH_HWE_MEMBISTFAILED    0x0040000000000000ULL
 155
 156 /* kr_hwdiagctrl bits */
 157 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL
 158 #define INFINIPATH_DC_FORCETXEMEMPARITYERR_SHIFT 40
 159 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_MASK 0x7FULL
 160 #define INFINIPATH_DC_FORCERXEMEMPARITYERR_SHIFT 44
 161 #define INFINIPATH_DC_FORCERXDSYNCMEMPARITYERR  0x0000000400000000ULL
 162 #define INFINIPATH_DC_COUNTERDISABLE            0x1000000000000000ULL
 163 #define INFINIPATH_DC_COUNTERWREN               0x2000000000000000ULL
 164 #define INFINIPATH_DC_FORCEIBCBUSTOSPCPARITYERR 0x4000000000000000ULL
 165 #define INFINIPATH_DC_FORCEIBCBUSFRSPCPARITYERR 0x8000000000000000ULL
 166
 167 /* kr_ibcctrl bits */
 168 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_MASK 0xFFULL
 169 #define INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT 0
 170 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_MASK 0xFFULL
 171 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8
 172 #define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL
 173 #define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1
 174 /* cycle through TS1/TS2 till OK */
 175 #define INFINIPATH_IBCC_LINKINITCMD_POLL 2
 176 /* wait for TS1, then go on */
 177 #define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3
 178 #define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
 179 #define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
 180 #define INFINIPATH_IBCC_LINKCMD_INIT 1  /* move to 0x11 */
 181 #define INFINIPATH_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
 182 #define INFINIPATH_IBCC_LINKCMD_ACTIVE 3        /* move to 0x31 */
 183 #define INFINIPATH_IBCC_LINKCMD_SHIFT 18
 184 #define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL
 185 #define INFINIPATH_IBCC_MAXPKTLEN_SHIFT 20
 186 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK 0xFULL
 187 #define INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT 32
 188 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_MASK 0xFULL
 189 #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT 36
 190 #define INFINIPATH_IBCC_CREDITSCALE_MASK 0x7ULL
 191 #define INFINIPATH_IBCC_CREDITSCALE_SHIFT 40
 192 #define INFINIPATH_IBCC_LOOPBACK             0x8000000000000000ULL
 193 #define INFINIPATH_IBCC_LINKDOWNDEFAULTSTATE 0x4000000000000000ULL
 194
 195 /* kr_ibcstatus bits */
 196 #define INFINIPATH_IBCS_LINKTRAININGSTATE_MASK 0xF
 197 #define INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT 0
 198 #define INFINIPATH_IBCS_LINKSTATE_MASK 0x7
 199 #define INFINIPATH_IBCS_LINKSTATE_SHIFT 4
 200 #define INFINIPATH_IBCS_TXREADY       0x40000000
 201 #define INFINIPATH_IBCS_TXCREDITOK    0x80000000
 202 /* link training states (shift by
 203    INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
 204 #define INFINIPATH_IBCS_LT_STATE_DISABLED       0x00
 205 #define INFINIPATH_IBCS_LT_STATE_LINKUP         0x01
 206 #define INFINIPATH_IBCS_LT_STATE_POLLACTIVE     0x02
 207 #define INFINIPATH_IBCS_LT_STATE_POLLQUIET      0x03
 208 #define INFINIPATH_IBCS_LT_STATE_SLEEPDELAY     0x04
 209 #define INFINIPATH_IBCS_LT_STATE_SLEEPQUIET     0x05
 210 #define INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE    0x08
 211 #define INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG     0x09
 212 #define INFINIPATH_IBCS_LT_STATE_CFGWAITRMT     0x0a
 213 #define INFINIPATH_IBCS_LT_STATE_CFGIDLE        0x0b
 214 #define INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN 0x0c
 215 #define INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT 0x0e
 216 #define INFINIPATH_IBCS_LT_STATE_RECOVERIDLE    0x0f
 217 /* link state machine states (shift by INFINIPATH_IBCS_LINKSTATE_SHIFT) */
 218 #define INFINIPATH_IBCS_L_STATE_DOWN            0x0
 219 #define INFINIPATH_IBCS_L_STATE_INIT            0x1
 220 #define INFINIPATH_IBCS_L_STATE_ARM             0x2
 221 #define INFINIPATH_IBCS_L_STATE_ACTIVE          0x3
 222 #define INFINIPATH_IBCS_L_STATE_ACT_DEFER       0x4
 223
 224 /* combination link status states that we use with some frequency */
 225 #define IPATH_IBSTATE_MASK ((INFINIPATH_IBCS_LINKTRAININGSTATE_MASK \
 226                 << INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) | \
 227                 (INFINIPATH_IBCS_LINKSTATE_MASK \
 228                 <<INFINIPATH_IBCS_LINKSTATE_SHIFT))
 229 #define IPATH_IBSTATE_INIT ((INFINIPATH_IBCS_L_STATE_INIT \
 230                 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
 231                 (INFINIPATH_IBCS_LT_STATE_LINKUP \
 232                 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
 233 #define IPATH_IBSTATE_ARM ((INFINIPATH_IBCS_L_STATE_ARM \
 234                 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
 235                 (INFINIPATH_IBCS_LT_STATE_LINKUP \
 236                 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
 237 #define IPATH_IBSTATE_ACTIVE ((INFINIPATH_IBCS_L_STATE_ACTIVE \
 238                 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
 239                 (INFINIPATH_IBCS_LT_STATE_LINKUP \
 240                 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
 241
 242 /* kr_extstatus bits */
 243 #define INFINIPATH_EXTS_SERDESPLLLOCK 0x1
 244 #define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL
 245 #define INFINIPATH_EXTS_GPIOIN_SHIFT 48
 246
 247 /* kr_extctrl bits */
 248 #define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL
 249 #define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32
 250 #define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL
 251 #define INFINIPATH_EXTC_GPIOOE_SHIFT 48
 252 #define INFINIPATH_EXTC_SERDESENABLE         0x80000000ULL
 253 #define INFINIPATH_EXTC_SERDESCONNECT        0x40000000ULL
 254 #define INFINIPATH_EXTC_SERDESENTRUNKING     0x20000000ULL
 255 #define INFINIPATH_EXTC_SERDESDISRXFIFO      0x10000000ULL
 256 #define INFINIPATH_EXTC_SERDESENPLPBK1       0x08000000ULL
 257 #define INFINIPATH_EXTC_SERDESENPLPBK2       0x04000000ULL
 258 #define INFINIPATH_EXTC_SERDESENENCDEC       0x02000000ULL
 259 #define INFINIPATH_EXTC_LED1SECPORT_ON       0x00000020ULL
 260 #define INFINIPATH_EXTC_LED2SECPORT_ON       0x00000010ULL
 261 #define INFINIPATH_EXTC_LED1PRIPORT_ON       0x00000008ULL
 262 #define INFINIPATH_EXTC_LED2PRIPORT_ON       0x00000004ULL
 263 #define INFINIPATH_EXTC_LEDGBLOK_ON          0x00000002ULL
 264 #define INFINIPATH_EXTC_LEDGBLERR_OFF        0x00000001ULL
 265
 266 /* kr_mdio bits */
 267 #define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL
 268 #define INFINIPATH_MDIO_CLKDIV_SHIFT 32
 269 #define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL
 270 #define INFINIPATH_MDIO_COMMAND_SHIFT 26
 271 #define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL
 272 #define INFINIPATH_MDIO_DEVADDR_SHIFT 21
 273 #define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL
 274 #define INFINIPATH_MDIO_REGADDR_SHIFT 16
 275 #define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL
 276 #define INFINIPATH_MDIO_DATA_SHIFT 0
 277 #define INFINIPATH_MDIO_CMDVALID    0x0000000040000000ULL
 278 #define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL
 279
 280 /* kr_partitionkey bits */
 281 #define INFINIPATH_PKEY_SIZE 16
 282 #define INFINIPATH_PKEY_MASK 0xFFFF
 283 #define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF
 284
 285 /* kr_serdesconfig0 bits */
 286 #define INFINIPATH_SERDC0_RESET_MASK  0xfULL    /* overal reset bits */
 287 #define INFINIPATH_SERDC0_RESET_PLL   0x10000000ULL     /* pll reset */
 288 /* tx idle enables (per lane) */
 289 #define INFINIPATH_SERDC0_TXIDLE      0xF000ULL
 290 /* rx detect enables (per lane) */
 291 #define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL
 292 /* L1 Power down; use with RXDETECT, Otherwise not used on IB side */
 293 #define INFINIPATH_SERDC0_L1PWR_DN       0xF0ULL
 294
 295 /* kr_xgxsconfig bits */
 296 #define INFINIPATH_XGXS_RESET          0x7ULL
 297 #define INFINIPATH_XGXS_MDIOADDR_MASK  0xfULL
 298 #define INFINIPATH_XGXS_MDIOADDR_SHIFT 4
 299 #define INFINIPATH_XGXS_RX_POL_SHIFT 19
 300 #define INFINIPATH_XGXS_RX_POL_MASK 0xfULL
 301
 302 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
 303
 304 /* TID entries (memory), HT-only */
 305 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
 306 #define INFINIPATH_RT_ADDR_SHIFT 0
 307 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFF
 308 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
 309
 310 /*
 311  * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our
 312  * PIO send buffers.  This is well beyond anything currently
 313  * defined in the InfiniBand spec.
 314  */
 315 #define IPATH_PIO_MAXIBHDR 128
 316
 317 typedef u64 ipath_err_t;
 318
 319 /* The following change with the type of device, so
 320  * need to be part of the ipath_devdata struct, or
 321  * we could have problems plugging in devices of
 322  * different types (e.g. one HT, one PCIE)
 323  * in one system, to be managed by one driver.
 324  * On the other hand, this file is may also be included
 325  * by other code, so leave the declarations here
 326  * temporarily. Minor footprint issue if common-model
 327  * linker used, none if C89+ linker used.
 328  */
 329
 330 /* mask of defined bits for various registers */
 331 extern u64 infinipath_i_bitsextant;
 332 extern ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant;
 333
 334 /* masks that are different in various chips, or only exist in some chips */
 335 extern u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask;
 336
 337 /*
 338  * These are the infinipath general register numbers (not offsets).
 339  * The kernel registers are used directly, those beyond the kernel
 340  * registers are calculated from one of the base registers.  The use of
 341  * an integer type doesn't allow type-checking as thorough as, say,
 342  * an enum but allows for better hiding of chip differences.
 343  */
 344 typedef const u16 ipath_kreg,   /* infinipath general registers */
 345  ipath_creg,                    /* infinipath counter registers */
 346  ipath_sreg;                    /* kernel-only, infinipath send registers */
 347
 348 /*
 349  * These are the chip registers common to all infinipath chips, and
 350  * used both by the kernel and the diagnostics or other user code.
 351  * They are all implemented such that 64 bit accesses work.
 352  * Some implement no more than 32 bits.  Because 64 bit reads
 353  * require 2 HT cmds on opteron, we access those with 32 bit
 354  * reads for efficiency (they are written as 64 bits, since
 355  * the extra 32 bits are nearly free on writes, and it slightly reduces
 356  * complexity).  The rest are all accessed as 64 bits.
 357  */
 358 struct ipath_kregs {
 359         /* These are the 32 bit group */
 360         ipath_kreg kr_control;
 361         ipath_kreg kr_counterregbase;
 362         ipath_kreg kr_intmask;
 363         ipath_kreg kr_intstatus;
 364         ipath_kreg kr_pagealign;
 365         ipath_kreg kr_portcnt;
 366         ipath_kreg kr_rcvtidbase;
 367         ipath_kreg kr_rcvtidcnt;
 368         ipath_kreg kr_rcvegrbase;
 369         ipath_kreg kr_rcvegrcnt;
 370         ipath_kreg kr_scratch;
 371         ipath_kreg kr_sendctrl;
 372         ipath_kreg kr_sendpiobufbase;
 373         ipath_kreg kr_sendpiobufcnt;
 374         ipath_kreg kr_sendpiosize;
 375         ipath_kreg kr_sendregbase;
 376         ipath_kreg kr_userregbase;
 377         /* These are the 64 bit group */
 378         ipath_kreg kr_debugport;
 379         ipath_kreg kr_debugportselect;
 380         ipath_kreg kr_errorclear;
 381         ipath_kreg kr_errormask;
 382         ipath_kreg kr_errorstatus;
 383         ipath_kreg kr_extctrl;
 384         ipath_kreg kr_extstatus;
 385         ipath_kreg kr_gpio_clear;
 386         ipath_kreg kr_gpio_mask;
 387         ipath_kreg kr_gpio_out;
 388         ipath_kreg kr_gpio_status;
 389         ipath_kreg kr_hwdiagctrl;
 390         ipath_kreg kr_hwerrclear;
 391         ipath_kreg kr_hwerrmask;
 392         ipath_kreg kr_hwerrstatus;
 393         ipath_kreg kr_ibcctrl;
 394         ipath_kreg kr_ibcstatus;
 395         ipath_kreg kr_intblocked;
 396         ipath_kreg kr_intclear;
 397         ipath_kreg kr_interruptconfig;
 398         ipath_kreg kr_mdio;
 399         ipath_kreg kr_partitionkey;
 400         ipath_kreg kr_rcvbthqp;
 401         ipath_kreg kr_rcvbufbase;
 402         ipath_kreg kr_rcvbufsize;
 403         ipath_kreg kr_rcvctrl;
 404         ipath_kreg kr_rcvhdrcnt;
 405         ipath_kreg kr_rcvhdrentsize;
 406         ipath_kreg kr_rcvhdrsize;
 407         ipath_kreg kr_rcvintmembase;
 408         ipath_kreg kr_rcvintmemsize;
 409         ipath_kreg kr_revision;
 410         ipath_kreg kr_sendbuffererror;
 411         ipath_kreg kr_sendpioavailaddr;
 412         ipath_kreg kr_serdesconfig0;
 413         ipath_kreg kr_serdesconfig1;
 414         ipath_kreg kr_serdesstatus;
 415         ipath_kreg kr_txintmembase;
 416         ipath_kreg kr_txintmemsize;
 417         ipath_kreg kr_xgxsconfig;
 418         ipath_kreg kr_ibpllcfg;
 419         /* use these two (and the following N ports) only with
 420          * ipath_k*_kreg64_port(); not *kreg64() */
 421         ipath_kreg kr_rcvhdraddr;
 422         ipath_kreg kr_rcvhdrtailaddr;
 423
 424         /* remaining registers are not present on all types of infinipath
 425            chips  */
 426         ipath_kreg kr_rcvpktledcnt;
 427         ipath_kreg kr_pcierbuftestreg0;
 428         ipath_kreg kr_pcierbuftestreg1;
 429         ipath_kreg kr_pcieq0serdesconfig0;
 430         ipath_kreg kr_pcieq0serdesconfig1;
 431         ipath_kreg kr_pcieq0serdesstatus;
 432         ipath_kreg kr_pcieq1serdesconfig0;
 433         ipath_kreg kr_pcieq1serdesconfig1;
 434         ipath_kreg kr_pcieq1serdesstatus;
 435 };
 436
 437 struct ipath_cregs {
 438         ipath_creg cr_badformatcnt;
 439         ipath_creg cr_erricrccnt;
 440         ipath_creg cr_errlinkcnt;
 441         ipath_creg cr_errlpcrccnt;
 442         ipath_creg cr_errpkey;
 443         ipath_creg cr_errrcvflowctrlcnt;
 444         ipath_creg cr_err_rlencnt;
 445         ipath_creg cr_errslencnt;
 446         ipath_creg cr_errtidfull;
 447         ipath_creg cr_errtidvalid;
 448         ipath_creg cr_errvcrccnt;
 449         ipath_creg cr_ibstatuschange;
 450         ipath_creg cr_intcnt;
 451         ipath_creg cr_invalidrlencnt;
 452         ipath_creg cr_invalidslencnt;
 453         ipath_creg cr_lbflowstallcnt;
 454         ipath_creg cr_iblinkdowncnt;
 455         ipath_creg cr_iblinkerrrecovcnt;
 456         ipath_creg cr_ibsymbolerrcnt;
 457         ipath_creg cr_pktrcvcnt;
 458         ipath_creg cr_pktrcvflowctrlcnt;
 459         ipath_creg cr_pktsendcnt;
 460         ipath_creg cr_pktsendflowcnt;
 461         ipath_creg cr_portovflcnt;
 462         ipath_creg cr_rcvebpcnt;
 463         ipath_creg cr_rcvovflcnt;
 464         ipath_creg cr_rxdroppktcnt;
 465         ipath_creg cr_senddropped;
 466         ipath_creg cr_sendstallcnt;
 467         ipath_creg cr_sendunderruncnt;
 468         ipath_creg cr_unsupvlcnt;
 469         ipath_creg cr_wordrcvcnt;
 470         ipath_creg cr_wordsendcnt;
 471 };
 472
 473 #endif                          /* _IPATH_REGISTERS_H */