| blob | 2bc70c5b9415be15d75e9234cc2a48270ae474e5 |
1 /*
2 * DO NOT EDIT THIS FILE
3 * This file is under version control at
4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE
7 *
8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the Clear BSD license.
10 */
12 /* This file should be up to date with:
13 * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
14 */
16 #ifndef _MACH_ANOMALY_H_
17 #define _MACH_ANOMALY_H_
19 /* We do not support 0.1 silicon - sorry */
20 #if __SILICON_REVISION__ < 2
21 # error will not work on BF537 silicon version 0.0 or 0.1
22 #endif
24 #if defined(__ADSPBF534__)
25 # define ANOMALY_BF534 1
26 #else
27 # define ANOMALY_BF534 0
28 #endif
29 #if defined(__ADSPBF536__)
30 # define ANOMALY_BF536 1
31 #else
32 # define ANOMALY_BF536 0
33 #endif
34 #if defined(__ADSPBF537__)
35 # define ANOMALY_BF537 1
36 #else
37 # define ANOMALY_BF537 0
38 #endif
40 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
41 #define ANOMALY_05000074 (1)
42 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
43 #define ANOMALY_05000119 (1)
44 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
45 #define ANOMALY_05000122 (1)
46 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
47 #define ANOMALY_05000180 (1)
48 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
49 #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
50 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
51 #define ANOMALY_05000245 (1)
52 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
53 #define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
54 /* EMAC TX DMA Error After an Early Frame Abort */
55 #define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
56 /* Maximum External Clock Speed for Timers */
57 #define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
58 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
59 #define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
60 /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
61 #define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
62 /* EMAC MDIO Input Latched on Wrong MDC Edge */
63 #define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
64 /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
65 #define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
66 /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
67 #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
68 /* ICPLB_STATUS MMR Register May Be Corrupted */
69 #define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
70 /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
71 #define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
72 /* Stores To Data Cache May Be Lost */
73 #define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
74 /* Hardware Loop Corrupted When Taking an ICPLB Exception */
75 #define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
76 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
77 #define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
78 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
79 #define ANOMALY_05000265 (1)
80 /* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
81 #define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
82 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
83 #define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
84 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
85 #define ANOMALY_05000272 (1)
86 /* Writes to Synchronous SDRAM Memory May Be Lost */
87 #define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
88 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
89 #define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
90 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
91 #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
92 /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
93 #define ANOMALY_05000280 (1)
94 /* False Hardware Error when ISR Context Is Not Restored */
95 #define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
96 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
97 #define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
98 /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
99 #define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
100 /* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
101 #define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
102 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
103 #define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
104 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
105 #define ANOMALY_05000301 (1)
106 /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
107 #define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
108 /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
109 #define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
110 /* SCKELOW Bit Does Not Maintain State Through Hibernate */
111 #define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
112 /* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
113 #define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
114 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
115 #define ANOMALY_05000310 (1)
116 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
117 #define ANOMALY_05000312 (1)
118 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
119 #define ANOMALY_05000313 (1)
120 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
121 #define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
122 /* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
123 #define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
124 /* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
125 #define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
126 /* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
127 #define ANOMALY_05000322 (1)
128 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
129 #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
130 /* UART Gets Disabled after UART Boot */
131 #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
132 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
133 #define ANOMALY_05000355 (1)
134 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
135 #define ANOMALY_05000357 (1)
136 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
137 #define ANOMALY_05000359 (1)
138 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
139 #define ANOMALY_05000366 (1)
140 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
141 #define ANOMALY_05000371 (1)
142 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
143 #define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
144 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
145 #define ANOMALY_05000403 (1)
146 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
147 #define ANOMALY_05000416 (1)
148 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
149 #define ANOMALY_05000425 (1)
150 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
151 #define ANOMALY_05000426 (1)
152 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
153 #define ANOMALY_05000443 (1)
154 /* False Hardware Error when RETI Points to Invalid Memory */
155 #define ANOMALY_05000461 (1)
156 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
157 #define ANOMALY_05000462 (1)
158 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
159 #define ANOMALY_05000473 (1)
160 /* Possible Lockup Condition when Modifying PLL from External Memory */
161 #define ANOMALY_05000475 (1)
162 /* TESTSET Instruction Cannot Be Interrupted */
163 #define ANOMALY_05000477 (1)
164 /* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
165 #define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
166 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
167 #define ANOMALY_05000481 (1)
168 /* PLL May Latch Incorrect Values Coming Out of Reset */
169 #define ANOMALY_05000489 (1)
170 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
171 #define ANOMALY_05000491 (1)
172 /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
173 #define ANOMALY_05000494 (1)
174 /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
175 #define ANOMALY_05000501 (1)
177 /*
178 * These anomalies have been "phased" out of analog.com anomaly sheets and are
179 * here to show running on older silicon just isn't feasible.
180 */
182 /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
183 #define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
184 /* Instruction Cache Is Not Functional */
185 #define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
186 /* Buffered CLKIN Output Is Disabled by Default */
187 #define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
189 /* Anomalies that don't exist on this proc */
190 #define ANOMALY_05000099 (0)
191 #define ANOMALY_05000120 (0)
192 #define ANOMALY_05000125 (0)
193 #define ANOMALY_05000149 (0)
194 #define ANOMALY_05000158 (0)
195 #define ANOMALY_05000171 (0)
196 #define ANOMALY_05000179 (0)
197 #define ANOMALY_05000182 (0)
198 #define ANOMALY_05000183 (0)
199 #define ANOMALY_05000189 (0)
200 #define ANOMALY_05000198 (0)
201 #define ANOMALY_05000202 (0)
202 #define ANOMALY_05000215 (0)
203 #define ANOMALY_05000219 (0)
204 #define ANOMALY_05000220 (0)
205 #define ANOMALY_05000227 (0)
206 #define ANOMALY_05000230 (0)
207 #define ANOMALY_05000231 (0)
208 #define ANOMALY_05000233 (0)
209 #define ANOMALY_05000234 (0)
210 #define ANOMALY_05000242 (0)
211 #define ANOMALY_05000248 (0)
212 #define ANOMALY_05000266 (0)
213 #define ANOMALY_05000274 (0)
214 #define ANOMALY_05000287 (0)
215 #define ANOMALY_05000311 (0)
216 #define ANOMALY_05000323 (0)
217 #define ANOMALY_05000353 (1)
218 #define ANOMALY_05000362 (1)
219 #define ANOMALY_05000363 (0)
220 #define ANOMALY_05000364 (0)
221 #define ANOMALY_05000380 (0)
222 #define ANOMALY_05000383 (0)
223 #define ANOMALY_05000386 (1)
224 #define ANOMALY_05000389 (0)
225 #define ANOMALY_05000400 (0)
226 #define ANOMALY_05000412 (0)
227 #define ANOMALY_05000430 (0)
228 #define ANOMALY_05000432 (0)
229 #define ANOMALY_05000435 (0)
230 #define ANOMALY_05000440 (0)
231 #define ANOMALY_05000447 (0)
232 #define ANOMALY_05000448 (0)
233 #define ANOMALY_05000456 (0)
234 #define ANOMALY_05000450 (0)
235 #define ANOMALY_05000465 (0)
236 #define ANOMALY_05000467 (0)
237 #define ANOMALY_05000474 (0)
238 #define ANOMALY_05000485 (0)
239 #define ANOMALY_16000030 (0)
241 #endif